Consolidate the initialization routines and change the include guard to
conform with the coding guidelines as a preparation for the following
commits which add support for the SPI interface.
Signed-off-by: Leonard Pollak <leonardp@tr-host.de>
This fixes the constant for the mem page and replaces a
magic number with the already defined `BME680_LEN_COEFF2` constant.
Signed-off-by: Leonard Pollak <leonardp@tr-host.de>
PWM has a single set function now, macros like PWM_USEC() can be used to
specify other units than nanoseconds. This conversion was missed during
API updates.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The pwm field in struct args_index was missed when pwm was renamed to
channel in all drivers. As a result, the PWM shell could no longer be
built.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The it8xxx2 watchdog Kconfig options are always shown, for every type
of device, they should only be shown when an it8xxx2 device is being
targeted.
Signed-off-by: Jamie McCrae <spam@helper3000.net>
Includes several driver fixes and improvement to leverage
scatter/gather mode of DMA. Loads multiple DMA blocks into TCDs.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
RX FIFO watermark setting causing issue where last 16 words received
were stuck in FIFO, and not requesting DMA to move to buffer. Fixed by
setting watermark to 0.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
driver config settings were getting overwritten by APIs that set
default settings, like SAI_GetClassicI2SConfig(). Moved config code
after those APIs.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
stream_disable()'s should not always purge buffers.
And i2s_rx_stream_disable() needs separate control for
purging in_queue and out_queue since app owns buffers
after placed in out_queue for i2s_read()
Signed-off-by: Derek Snell <derek.snell@nxp.com>
MCP4728 is a 12-bit, Quad Digital-to-Analog Converter with EEPROM Memory.
Controlled via I2C interface.
Signed-off-by: Marek Janus <marek.janus@grinn-global.com>
In order to be consistent with what is possible in Devicetree, always
take a period in nanoseconds. Other scales or units may be specified by
using, e.g., the PWM_MSEC() macros (all of them converting down to
nanoseconds). This change then deletes the "_nsec" and "_usec" versions
of the pwm_set call.
Note that this change limits the period to UINT32_MAX nanoseconds,
~4.3s. PWM is, in generali, used with periods below the second so it
should not be a problem.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Simplify the driver by using pwm_dt_spec.
TODO: decide if pwm_dt_spec should also store period.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In a first place, the PWM API operates on "channels", not "pins". While
the API calls could have been changed by _channel, this patch takes the
approach of just dropping _pin. The main reason is that all API calls
operate by definition on a channel basis, so it is a bit redundant to
make this part of the name. Because the `_dt` variants of the calls are
going to be introduced soon, the change to `_channels` + `_dt` would
make API function names quite long.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The variable indicating the PWM channel is now names "channel" instead
of "pwm", adjust all drivers.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The timer registers are accessible via the device config field, driver
code was wrong in one case (pwm is the variable indicating PWM channel).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Multiple if/else blocks had missing braces, add them as this violates
Zephyr coding guidelines.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Implement the set_top_value. This reserves one of the Match channels
to set the top value and to reset the counter.
Therefore the number of channels available to the user is reduced by 1.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
After change in RD into 64-bit time, target time must be express in
absolute 64-bit time. Upper layer e.g. OpenThread still utilizes only
LSB of the RD time therefore the conversion is required.
Make sure that target time is absolute 64-bit target time.
Signed-off-by: Lukasz Maciejonczyk <lukasz.maciejonczyk@nordicsemi.no>
Add DT option to configure the data ready interrupt mode.
Latched is the default; pulsed can be enabled through
the drdy-pulsed DT, if desired.
Signed-off-by: Maxime Vincent <maxime@veemax.be>
Add optional threshold interrupt support.
Implemented using SENSOR_TRIG_THRESHOLD sensor trigger type.
The features can be optionally enabled through Kconfig,
or disabled for smaller code size.
Signed-off-by: Maxime Vincent <maxime@veemax.be>
Add FDS (Filtered Data Type Selection) + High-Pass reference mode support
(FDS in CTRL6, HP_REF_MODE in CTRL7)
Values are configurable through DT per instance.
Signed-off-by: Maxime Vincent <maxime@veemax.be>
Old code only create one pl011 device instance though there are two or
more pl011 device defined in devicetree. This patch can fix this issue.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
sensor_channel_get() API should return -ENOTSUP when requested channel
is not supported. This behavior allows to use `sensor get DEVNAME` shell
command easily, as all unsupported channels are filtered out.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
An application with the following config fails to link on nrf53 app
core:
```
CONFIG_BT=y
CONFIG_BT_HCI_RAW=y
CONFIG_ENTROPY_GENERATOR=y
```
This happens because `entropy_bt_hci.c` uses functions from
`hci_core.c`, which is only compiled if `BT_HCI_HOST` is selected.
Signed-off-by: Herman Berget <herman.berget@nordicsemi.no>
Enables the Intel TLB driver by default when the MM driver class is
enabled (CONFIG_MM_DRV=y) and a compatible devicetree node
("intel,adsp-tlb") is enabled.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Introduce has-interrupt-mask-reg DTS property for nxp,pca95xx driver.
This additionnal property allow to specify that the gpio expander has an
interrupt mask register that must be configured by the driver.
This allow to use this driver with PCAL95xx.
This fixes issue #44834.
Signed-off-by: Xavier Chapron <xavier.chapron@stimio.fr>
NXP LPUART IP supports loopback mode, where TX is internally connected
to RX input. Allow setting loopback mode up via the "nxp,loopback" dts
property.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
SOCs using the EDMA IP that supported caching must locate EDMA transfer
control descriptors (TCDs) in non cacheable memory. For M7 cores, this
can simply use the "nocache" section. For M4 cores, where the nocache
section does not exist, the chosen SRAM section must be a tightly
coupled memory block which cannot be cached. Add a note to all boards
with M4 SOCs that support caching explaining this issue, and enable EDMA
driver to locate TCDs in SRAM.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
LPUART driver should use shared ISR for all possible use cases,
including ASYNC API, so that multiple features requiring ISR can be
enabled simultaneously.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for inverting of PWM channel outputs in the pwm_nrf5_sw
driver by properly handling the `PWM_POLARITY_INVERTED` flag.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Align with other PWM drivers and treat the `pwm` parameter (described
ambiguously as "PWM pin") of the `pwm_pin_set_cycles` function as a PWM
channel, not an SoC pin. This will also make the driver consistent with
the `pwm-cells` property definition in the "nordic,nrf-sw-pwm" binding
and with related `DT_PWMS_*` macros.
The change described above requires also providing a way to specify
SoC pins that are to be assigned to the PWM channels. Hence, the commit
introduces in the "nordic,nrf-sw-pwm" binding the `channel-gpios`
property that replaces the `channel-count` one.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for inverting of PWM channel outputs in the pwm_nrfx driver
by properly handling the `PWM_POLARITY_INVERTED` flag.
The dts properties that were used so far for inverting of the outputs
("nordic,invert" and "chX-inverted") are kept as they are needed for
setting of the initial polarity, i.e. for setting the inactive state
of the outputs before any PWM signal generation is requested for them.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Align with other PWM drivers and treat the `pwm` parameter (described
ambiguously as "PWM pin") of the `pwm_pin_set_cycles` function as a PWM
channel, not an SoC pin. This will also make the driver consistent with
the `pwm-cells` property definition in the "nordic,nrf-pwm" binding
and with related `DT_PWMS_*` macros.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Handle PECI command PING properly, also get Write FCS Byte as a check.
Now it is possible to perform a PECI Ping without crashing the bus or
blocking it for subsequent PECI transactions.
It is also possible to check whether the Ping was sucessful
or not with the Write FCS Byte.
Signed-off-by: Johannes Meister <johannes.meister@kontron.com>
STM32H7 series offer alias addresses to access some registers that could
be accessed by the M4 core on dual core variants.
For instance RCC_AHB3ENR could be accessed at following offsets:
- 0x0D4: Accessible from both cores
- 0x134: Accessible from C1 (M7) core
- 0x194: Accessible from C2 (M4) core (if any)
For most single core H7 variants, the two first addresses were accessible,
but for some others (stm32h7ax/stm32h7bx), only the 'C1 accessible'
was available.
This fact used to be hidden by the use of LL API to access these registers,
providing the required abstraction (an mainly using the first alias
when possible to simplify implementation).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Instead of computing hclk freq use for flash latency setting after
setting the PLLs, do it right at the beginning of the function.
Indeed, first step of PLL configuration is to switch back sysclock
to HSI source (in case it was initially PLL).
In that case, flash latency is theoretically set in consistency with PLL
driver hclk. So we should "measure" hclk freq at that step rather than
once sysclock is back on HSI.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC is the actual hclk freq (ie core clock);
Remove use of intermediate new_hclk_freq to fix and simplify code.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Some specific F1 variants don't handle flash latency.
Put flash latency dealing code under dedicated switch.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
