michaelh/zephyr
1
0
Fork 0
Code Releases Activity

drivers: edma: allow transfer descriptors to be placed in SRAM

Browse source 
SOCs using the EDMA IP that supported caching must locate EDMA transfer
control descriptors (TCDs) in non cacheable memory. For M7 cores, this
can simply use the "nocache" section. For M4 cores, where the nocache
section does not exist, the chosen SRAM section must be a tightly
coupled memory block which cannot be cached. Add a note to all boards
with M4 SOCs that support caching explaining this issue, and enable EDMA
driver to locate TCDs in SRAM.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2022-04-19 18:11:43 -05:00 • committed by Carles Cufí
commit 17d9bea474
6 changed files with 48 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

11
drivers/dma/dma_mcux_edma.c
View file

@ -47,7 +47,16 @@ struct dma_mcux_edma_config {
#elif defined(CONFIG_NOCACHE_MEMORY)
#define EDMA_TCDPOOL_CACHE_ATTR __nocache
#else
#error tcdpool could not be located in cacheable memory, a requirement for proper EDMA operation.
/*
* Note: the TCD pool *must* be in non cacheable memory. All of the NXP SOCs
* that support caching memory have their default SRAM regions defined as a
* non cached memory region, but if the default SRAM region is changed EDMA
* TCD pools would be moved to cacheable memory, resulting in DMA cache
* coherency issues.
*/
#define EDMA_TCDPOOL_CACHE_ATTR
#endif /* CONFIG_DMA_MCUX_USE_DTCM_FOR_DMA_DESCRIPTORS */
#else /* CONFIG_HAS_MCUX_CACHE */