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drivers: pwm: make all drivers use channel variable name

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The variable indicating the PWM channel is now names "channel" instead
of "pwm", adjust all drivers.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit is contained in:
Gerard Marull-Paretas 2022-04-04 16:35:22 +02:00 • committed by Carles Cufí
commit fbf73334f3
26 changed files with 271 additions and 270 deletions
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32
drivers/pwm/pwm_b91.c
View file

@ -56,14 +56,14 @@ static int pwm_b91_init(const struct device *dev)
}
/* API implementation: pin_set */
static int pwm_b91_pin_set(const struct device *dev, uint32_t pwm,
static int pwm_b91_pin_set(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
ARG_UNUSED(dev);
/* check pwm channel */
if (pwm >= NUM_OF_CHANNELS) {
if (channel >= NUM_OF_CHANNELS) {
return -EINVAL;
}
@ -75,39 +75,39 @@ static int pwm_b91_pin_set(const struct device *dev, uint32_t pwm,
/* set polarity */
if (flags & PWM_POLARITY_INVERTED) {
pwm_invert_en(pwm);
pwm_invert_en(channel);
} else {
pwm_invert_dis(pwm);
pwm_invert_dis(channel);
}
/* set pulse and period */
pwm_set_tcmp(pwm, pulse_cycles);
pwm_set_tmax(pwm, period_cycles);
pwm_set_tcmp(channel, pulse_cycles);
pwm_set_tmax(channel, period_cycles);
/* start pwm */
pwm_start(pwm);
pwm_start(channel);
return 0;
}
/* API implementation: get_cycles_per_sec */
static int pwm_b91_get_cycles_per_sec(const struct device *dev, uint32_t pwm,
uint64_t *cycles)
static int pwm_b91_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
ARG_UNUSED(dev);
/* check pwm channel */
if (pwm >= NUM_OF_CHANNELS) {
if (channel >= NUM_OF_CHANNELS) {
return -EINVAL;
}
if (
((pwm == 0u) && DT_INST_PROP(0, clk32k_ch0_enable)) ||
((pwm == 1u) && DT_INST_PROP(0, clk32k_ch1_enable)) ||
((pwm == 2u) && DT_INST_PROP(0, clk32k_ch2_enable)) ||
((pwm == 3u) && DT_INST_PROP(0, clk32k_ch3_enable)) ||
((pwm == 4u) && DT_INST_PROP(0, clk32k_ch4_enable)) ||
((pwm == 5u) && DT_INST_PROP(0, clk32k_ch5_enable))
((channel == 0u) && DT_INST_PROP(0, clk32k_ch0_enable)) ||
((channel == 1u) && DT_INST_PROP(0, clk32k_ch1_enable)) ||
((channel == 2u) && DT_INST_PROP(0, clk32k_ch2_enable)) ||
((channel == 3u) && DT_INST_PROP(0, clk32k_ch3_enable)) ||
((channel == 4u) && DT_INST_PROP(0, clk32k_ch4_enable)) ||
((channel == 5u) && DT_INST_PROP(0, clk32k_ch5_enable))
) {
*cycles = 32000u;
} else {

12
drivers/pwm/pwm_capture.c
View file

@ -19,7 +19,7 @@ struct z_pwm_pin_capture_cb_data {
};
static void z_pwm_pin_capture_cycles_callback(const struct device *dev,
uint32_t pwm,
uint32_t channel,
uint32_t period_cycles,
uint32_t pulse_cycles,
int status,
@ -34,7 +34,7 @@ static void z_pwm_pin_capture_cycles_callback(const struct device *dev,
k_sem_give(&data->sem);
}
int z_impl_pwm_pin_capture_cycles(const struct device *dev, uint32_t pwm,
int z_impl_pwm_pin_capture_cycles(const struct device *dev, uint32_t channel,
pwm_flags_t flags, uint32_t *period,
uint32_t *pulse, k_timeout_t timeout)
{
@ -49,7 +49,7 @@ int z_impl_pwm_pin_capture_cycles(const struct device *dev, uint32_t pwm,
flags |= PWM_CAPTURE_MODE_SINGLE;
k_sem_init(&data.sem, 0, 1);
err = pwm_pin_configure_capture(dev, pwm, flags,
err = pwm_pin_configure_capture(dev, channel, flags,
z_pwm_pin_capture_cycles_callback,
&data);
if (err) {
@ -57,7 +57,7 @@ int z_impl_pwm_pin_capture_cycles(const struct device *dev, uint32_t pwm,
return err;
}
err = pwm_pin_enable_capture(dev, pwm);
err = pwm_pin_enable_capture(dev, channel);
if (err) {
LOG_ERR("failed to enable pwm capture");
return err;
@ -65,8 +65,8 @@ int z_impl_pwm_pin_capture_cycles(const struct device *dev, uint32_t pwm,
err = k_sem_take(&data.sem, timeout);
if (err == -EAGAIN) {
(void)pwm_pin_disable_capture(dev, pwm);
(void)pwm_pin_configure_capture(dev, pwm, flags, NULL, NULL);
(void)pwm_pin_disable_capture(dev, channel);
(void)pwm_pin_configure_capture(dev, channel, flags, NULL, NULL);
LOG_WRN("pwm capture timed out");
return err;
}

26
drivers/pwm/pwm_gd32.c
View file

@ -132,13 +132,13 @@ static uint32_t pwm_gd32_get_tim_clk(const struct device *dev)
#endif /* RCU_CFG1_TIMERSEL */
}
static int pwm_gd32_pin_set(const struct device *dev, uint32_t pwm,
static int pwm_gd32_pin_set(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
const struct pwm_gd32_config *config = dev->config;
if (pwm >= config->channels) {
if (channel >= config->channels) {
return -EINVAL;
}
@ -149,19 +149,19 @@ static int pwm_gd32_pin_set(const struct device *dev, uint32_t pwm,
/* disable channel output if period is zero */
if (period_cycles == 0U) {
TIMER_CHCTL2(config->reg) &= ~TIMER_CHCTL2_CHXEN(pwm);
TIMER_CHCTL2(config->reg) &= ~TIMER_CHCTL2_CHXEN(channel);
return 0;
}
/* update polarity */
if ((flags & PWM_POLARITY_INVERTED) != 0U) {
TIMER_CHCTL2(config->reg) |= TIMER_CHCTL2_CHXP(pwm);
TIMER_CHCTL2(config->reg) |= TIMER_CHCTL2_CHXP(channel);
} else {
TIMER_CHCTL2(config->reg) &= ~TIMER_CHCTL2_CHXP(pwm);
TIMER_CHCTL2(config->reg) &= ~TIMER_CHCTL2_CHXP(channel);
}
/* update pulse */
switch (pwm) {
switch (channel) {
case 0U:
TIMER_CH0CV(config->reg) = pulse_cycles;
break;
@ -183,22 +183,22 @@ static int pwm_gd32_pin_set(const struct device *dev, uint32_t pwm,
TIMER_CAR(config->reg) = period_cycles;
/* channel not enabled: configure it */
if ((TIMER_CHCTL2(config->reg) & TIMER_CHCTL2_CHXEN(pwm)) == 0U) {
if ((TIMER_CHCTL2(config->reg) & TIMER_CHCTL2_CHXEN(channel)) == 0U) {
volatile uint32_t *chctl;
/* select PWM1 mode, enable OC shadowing */
if (pwm < 2U) {
if (channel < 2U) {
chctl = &TIMER_CHCTL0(config->reg);
} else {
chctl = &TIMER_CHCTL1(config->reg);
}
*chctl &= ~TIMER_CHCTLX_MSK(pwm);
*chctl &= ~TIMER_CHCTLX_MSK(channel);
*chctl |= (TIMER_OC_MODE_PWM1 | TIMER_OC_SHADOW_ENABLE) <<
(8U * (pwm % 2U));
(8U * (channel % 2U));
/* enable channel output */
TIMER_CHCTL2(config->reg) |= TIMER_CHCTL2_CHXEN(pwm);
TIMER_CHCTL2(config->reg) |= TIMER_CHCTL2_CHXEN(channel);
/* generate update event (to load shadow values) */
TIMER_SWEVG(config->reg) |= TIMER_SWEVG_UPG;
@ -207,8 +207,8 @@ static int pwm_gd32_pin_set(const struct device *dev, uint32_t pwm,
return 0;
}
static int pwm_gd32_get_cycles_per_sec(const struct device *dev, uint32_t pwm,
uint64_t *cycles)
static int pwm_gd32_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
struct pwm_gd32_data *data = dev->data;
const struct pwm_gd32_config *config = dev->config;

22
drivers/pwm/pwm_gecko.c
View file

@ -23,47 +23,47 @@ struct pwm_gecko_config {
uint8_t pin;
};
static int pwm_gecko_pin_set(const struct device *dev, uint32_t pwm,
static int pwm_gecko_pin_set(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
TIMER_InitCC_TypeDef compare_config = TIMER_INITCC_DEFAULT;
const struct pwm_gecko_config *cfg = dev->config;
if (BUS_RegMaskedRead(&cfg->timer->CC[pwm].CTRL,
if (BUS_RegMaskedRead(&cfg->timer->CC[channel].CTRL,
_TIMER_CC_CTRL_MODE_MASK) != timerCCModePWM) {
#ifdef _TIMER_ROUTE_MASK
BUS_RegMaskedWrite(&cfg->timer->ROUTE,
_TIMER_ROUTE_LOCATION_MASK,
cfg->location << _TIMER_ROUTE_LOCATION_SHIFT);
BUS_RegMaskedSet(&cfg->timer->ROUTE, 1 << pwm);
BUS_RegMaskedSet(&cfg->timer->ROUTE, 1 << channel);
#elif defined(_TIMER_ROUTELOC0_MASK)
BUS_RegMaskedWrite(&cfg->timer->ROUTELOC0,
_TIMER_ROUTELOC0_CC0LOC_MASK << (pwm * _TIMER_ROUTELOC0_CC1LOC_SHIFT),
cfg->location << (pwm * _TIMER_ROUTELOC0_CC1LOC_SHIFT));
BUS_RegMaskedSet(&cfg->timer->ROUTEPEN, 1 << pwm);
_TIMER_ROUTELOC0_CC0LOC_MASK <<
(channel * _TIMER_ROUTELOC0_CC1LOC_SHIFT),
cfg->location << (channel * _TIMER_ROUTELOC0_CC1LOC_SHIFT));
BUS_RegMaskedSet(&cfg->timer->ROUTEPEN, 1 << channel);
#else
#error Unsupported device
#endif
compare_config.mode = timerCCModePWM;
TIMER_InitCC(cfg->timer, pwm, &compare_config);
TIMER_InitCC(cfg->timer, channel, &compare_config);
}
cfg->timer->CC[pwm].CTRL |= (flags & PWM_POLARITY_INVERTED) ?
cfg->timer->CC[channel].CTRL |= (flags & PWM_POLARITY_INVERTED) ?
TIMER_CC_CTRL_OUTINV : 0;
TIMER_TopSet(cfg->timer, period_cycles);
TIMER_CompareBufSet(cfg->timer, pwm, pulse_cycles);
TIMER_CompareBufSet(cfg->timer, channel, pulse_cycles);
return 0;
}
static int pwm_gecko_get_cycles_per_sec(const struct device *dev,
uint32_t pwm,
uint64_t *cycles)
uint32_t channel, uint64_t *cycles)
{
const struct pwm_gecko_config *cfg = dev->config;

29
drivers/pwm/pwm_handlers.c
View file

@ -9,48 +9,49 @@
#include <drivers/pwm.h>
static inline int z_vrfy_pwm_pin_set_cycles(const struct device *dev,
uint32_t pwm,
uint32_t period, uint32_t pulse,
pwm_flags_t flags)
uint32_t channel, uint32_t period,
uint32_t pulse, pwm_flags_t flags)
{
Z_OOPS(Z_SYSCALL_DRIVER_PWM(dev, pin_set));
return z_impl_pwm_pin_set_cycles((const struct device *)dev, pwm,
period,
pulse, flags);
return z_impl_pwm_pin_set_cycles((const struct device *)dev, channel,
period, pulse, flags);
}
#include <syscalls/pwm_pin_set_cycles_mrsh.c>
static inline int z_vrfy_pwm_get_cycles_per_sec(const struct device *dev,
uint32_t pwm,
uint32_t channel,
uint64_t *cycles)
{
Z_OOPS(Z_SYSCALL_DRIVER_PWM(dev, get_cycles_per_sec));
Z_OOPS(Z_SYSCALL_MEMORY_WRITE(cycles, sizeof(uint64_t)));
return z_impl_pwm_get_cycles_per_sec((const struct device *)dev,
pwm, (uint64_t *)cycles);
channel, (uint64_t *)cycles);
}
#include <syscalls/pwm_get_cycles_per_sec_mrsh.c>
#ifdef CONFIG_PWM_CAPTURE
static inline int z_vrfy_pwm_pin_enable_capture(const struct device *dev,
uint32_t pwm)
uint32_t channel)
{
Z_OOPS(Z_SYSCALL_DRIVER_PWM(dev, pin_enable_capture));
return z_impl_pwm_pin_enable_capture((const struct device *)dev, pwm);
return z_impl_pwm_pin_enable_capture((const struct device *)dev,
channel);
}
#include <syscalls/pwm_pin_enable_capture_mrsh.c>
static inline int z_vrfy_pwm_pin_disable_capture(const struct device *dev,
uint32_t pwm)
uint32_t channel)
{
Z_OOPS(Z_SYSCALL_DRIVER_PWM(dev, pin_disable_capture));
return z_impl_pwm_pin_disable_capture((const struct device *)dev, pwm);
return z_impl_pwm_pin_disable_capture((const struct device *)dev,
channel);
}
#include <syscalls/pwm_pin_disable_capture_mrsh.c>
static inline int z_vrfy_pwm_pin_capture_cycles(const struct device *dev,
uint32_t pwm, pwm_flags_t flags,
uint32_t channel,
pwm_flags_t flags,
uint32_t *period_cycles,
uint32_t *pulse_cycles,
k_timeout_t timeout)
@ -63,7 +64,7 @@ static inline int z_vrfy_pwm_pin_capture_cycles(const struct device *dev,
Z_OOPS(Z_SYSCALL_DRIVER_PWM(dev, pin_enable_capture));
Z_OOPS(Z_SYSCALL_DRIVER_PWM(dev, pin_disable_capture));
err = z_impl_pwm_pin_capture_cycles((const struct device *)dev, pwm,
err = z_impl_pwm_pin_capture_cycles((const struct device *)dev, channel,
flags, &period, &pulse, timeout);
if (period_cycles != NULL) {
Z_OOPS(z_user_to_copy(period_cycles, &period,

2
drivers/pwm/pwm_imx.c
View file

@ -47,7 +47,7 @@ static int imx_pwm_get_cycles_per_sec(const struct device *dev, uint32_t pwm,
return 0;
}
static int imx_pwm_pin_set(const struct device *dev, uint32_t pwm,
static int imx_pwm_pin_set(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{

12
drivers/pwm/pwm_ite_it8xxx2.c
View file

@ -68,9 +68,9 @@ static void pwm_enable(const struct device *dev, int enabled)
}
static int pwm_it8xxx2_get_cycles_per_sec(const struct device *dev,
uint32_t pwm, uint64_t *cycles)
uint32_t channel, uint64_t *cycles)
{
ARG_UNUSED(pwm);
ARG_UNUSED(channel);
/*
* There are three ways to call pwm_it8xxx2_pin_set() from pwm api:
@ -95,9 +95,9 @@ static int pwm_it8xxx2_get_cycles_per_sec(const struct device *dev,
return 0;
}
static int pwm_it8xxx2_pin_set(const struct device *dev,
uint32_t pwm, uint32_t period_cycles,
uint32_t pulse_cycles, pwm_flags_t flags)
static int pwm_it8xxx2_pin_set(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
const struct pwm_it8xxx2_cfg *config = dev->config;
struct pwm_it8xxx2_regs *const inst = config->base;
@ -125,7 +125,7 @@ static int pwm_it8xxx2_pin_set(const struct device *dev,
return 0;
}
pwm_it8xxx2_get_cycles_per_sec(dev, pwm, &pwm_clk_src);
pwm_it8xxx2_get_cycles_per_sec(dev, channel, &pwm_clk_src);
target_freq = ((uint32_t) pwm_clk_src) / period_cycles;
/*

15
drivers/pwm/pwm_led_esp32.c
View file

@ -295,8 +295,10 @@ static int pwm_led_esp32_timer_set(int speed_mode, int timer,
/* period_cycles is not used, set frequency on menuconfig instead. */
static int pwm_led_esp32_pin_set_cycles(const struct device *dev,
uint32_t pwm, uint32_t period_cycles,
uint32_t pulse_cycles, pwm_flags_t flags)
uint32_t channel,
uint32_t period_cycles,
uint32_t pulse_cycles,
pwm_flags_t flags)
{
int speed_mode;
int channel;
@ -312,7 +314,7 @@ static int pwm_led_esp32_pin_set_cycles(const struct device *dev,
return -ENOTSUP;
}
channel = pwm_led_esp32_get_gpio_config(pwm, config->ch_cfg);
channel = pwm_led_esp32_get_gpio_config(channel, config->ch_cfg);
if (channel < 0) {
return -EINVAL;
}
@ -338,7 +340,7 @@ static int pwm_led_esp32_pin_set_cycles(const struct device *dev,
}
/* Set channel */
ret = pwm_led_esp32_channel_set(pwm, speed_mode, channel, 0, timer);
ret = pwm_led_esp32_channel_set(channel, speed_mode, channel, 0, timer);
if (ret < 0) {
return ret;
}
@ -349,8 +351,7 @@ static int pwm_led_esp32_pin_set_cycles(const struct device *dev,
}
static int pwm_led_esp32_get_cycles_per_sec(const struct device *dev,
uint32_t pwm,
uint64_t *cycles)
uint32_t channel, uint64_t *cycles)
{
const struct pwm_led_esp32_config *config;
int channel;
@ -359,7 +360,7 @@ static int pwm_led_esp32_get_cycles_per_sec(const struct device *dev,
config = (const struct pwm_led_esp32_config *) dev->config;
channel = pwm_led_esp32_get_gpio_config(pwm, config->ch_cfg);
channel = pwm_led_esp32_get_gpio_config(channel, config->ch_cfg);
if (channel < 0) {
return -EINVAL;
}

8
drivers/pwm/pwm_litex.c
View file

@ -45,13 +45,13 @@ int pwm_litex_init(const struct device *dev)
return 0;
}
int pwm_litex_pin_set(const struct device *dev, uint32_t pwm,
int pwm_litex_pin_set(const struct device *dev, uint32_t channel,
uint32_t period_cycles,
uint32_t pulse_cycles, pwm_flags_t flags)
{
const struct pwm_litex_cfg *cfg = dev->config;
if (pwm >= NUMBER_OF_CHANNELS) {
if (channel >= NUMBER_OF_CHANNELS) {
return -EINVAL;
}
@ -63,10 +63,10 @@ int pwm_litex_pin_set(const struct device *dev, uint32_t pwm,
return 0;
}
int pwm_litex_get_cycles_per_sec(const struct device *dev, uint32_t pwm,
int pwm_litex_get_cycles_per_sec(const struct device *dev, uint32_t channel,
uint64_t *cycles)
{
if (pwm >= NUMBER_OF_CHANNELS) {
if (channel >= NUMBER_OF_CHANNELS) {
return -EINVAL;
}

10
drivers/pwm/pwm_mchp_xec.c
View file

@ -313,7 +313,7 @@ done:
regs->CONFIG = cfgval;
}
static int pwm_xec_pin_set(const struct device *dev, uint32_t pwm,
static int pwm_xec_pin_set(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
@ -322,7 +322,7 @@ static int pwm_xec_pin_set(const struct device *dev, uint32_t pwm,
uint32_t target_freq;
uint32_t on, off;
if (pwm > 0) {
if (channel > 0) {
return -EIO;
}
@ -355,12 +355,12 @@ static int pwm_xec_pin_set(const struct device *dev, uint32_t pwm,
return 0;
}
static int pwm_xec_get_cycles_per_sec(const struct device *dev, uint32_t pwm,
uint64_t *cycles)
static int pwm_xec_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
ARG_UNUSED(dev);
if (pwm > 0) {
if (channel > 0) {
return -EIO;
}

16
drivers/pwm/pwm_mcux.c
View file

@ -34,7 +34,7 @@ struct pwm_mcux_data {
pwm_signal_param_t channel[CHANNEL_COUNT];
};
static int mcux_pwm_pin_set(const struct device *dev, uint32_t pwm,
static int mcux_pwm_pin_set(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
@ -42,7 +42,7 @@ static int mcux_pwm_pin_set(const struct device *dev, uint32_t pwm,
struct pwm_mcux_data *data = dev->data;
uint8_t duty_cycle;
if (pwm >= CHANNEL_COUNT) {
if (channel >= CHANNEL_COUNT) {
LOG_ERR("Invalid channel");
return -EINVAL;
}
@ -68,12 +68,12 @@ static int mcux_pwm_pin_set(const struct device *dev, uint32_t pwm,
duty_cycle = 100 * pulse_cycles / period_cycles;
/* FIXME: Force re-setup even for duty-cycle update */
if (period_cycles != data->period_cycles[pwm]) {
if (period_cycles != data->period_cycles[channel]) {
uint32_t clock_freq;
uint32_t pwm_freq;
status_t status;
data->period_cycles[pwm] = period_cycles;
data->period_cycles[channel] = period_cycles;
LOG_DBG("SETUP dutycycle to %u\n", duty_cycle);
@ -91,7 +91,7 @@ static int mcux_pwm_pin_set(const struct device *dev, uint32_t pwm,
PWM_StopTimer(config->base, 1U << config->index);
data->channel[pwm].dutyCyclePercent = duty_cycle;
data->channel[channel].dutyCyclePercent = duty_cycle;
status = PWM_SetupPwm(config->base, config->index,
&data->channel[0], CHANNEL_COUNT,
@ -106,7 +106,7 @@ static int mcux_pwm_pin_set(const struct device *dev, uint32_t pwm,
PWM_StartTimer(config->base, 1U << config->index);
} else {
PWM_UpdatePwmDutycycle(config->base, config->index,
(pwm == 0) ? kPWM_PwmA : kPWM_PwmB,
(channel == 0) ? kPWM_PwmA : kPWM_PwmB,
config->mode, duty_cycle);
PWM_SetPwmLdok(config->base, 1U << config->index, true);
}
@ -114,8 +114,8 @@ static int mcux_pwm_pin_set(const struct device *dev, uint32_t pwm,
return 0;
}
static int mcux_pwm_get_cycles_per_sec(const struct device *dev, uint32_t pwm,
uint64_t *cycles)
static int mcux_pwm_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
const struct pwm_mcux_config *config = dev->config;
uint32_t clock_freq;

47
drivers/pwm/pwm_mcux_ftm.c
View file

@ -58,7 +58,7 @@ struct mcux_ftm_data {
#endif /* CONFIG_PWM_CAPTURE */
};
static int mcux_ftm_pin_set(const struct device *dev, uint32_t pwm,
static int mcux_ftm_pin_set(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
@ -66,7 +66,7 @@ static int mcux_ftm_pin_set(const struct device *dev, uint32_t pwm,
struct mcux_ftm_data *data = dev->data;
status_t status;
#ifdef CONFIG_PWM_CAPTURE
uint32_t pair = pwm / 2U;
uint32_t pair = channel / 2U;
uint32_t irqs;
#endif /* CONFIG_PWM_CAPTURE */
@ -75,7 +75,7 @@ static int mcux_ftm_pin_set(const struct device *dev, uint32_t pwm,
return -ENOTSUP;
}
if (pwm >= config->channel_count) {
if (channel >= config->channel_count) {
LOG_ERR("Invalid channel");
return -ENOTSUP;
}
@ -88,12 +88,12 @@ static int mcux_ftm_pin_set(const struct device *dev, uint32_t pwm,
}
#endif /* CONFIG_PWM_CAPTURE */
data->channel[pwm].dutyValue = pulse_cycles;
data->channel[channel].dutyValue = pulse_cycles;
if ((flags & PWM_POLARITY_INVERTED) == 0) {
data->channel[pwm].level = kFTM_HighTrue;
data->channel[channel].level = kFTM_HighTrue;
} else {
data->channel[pwm].level = kFTM_LowTrue;
data->channel[channel].level = kFTM_LowTrue;
}
LOG_DBG("pulse_cycles=%d, period_cycles=%d, flags=%d",
@ -137,17 +137,16 @@ static int mcux_ftm_pin_set(const struct device *dev, uint32_t pwm,
#ifdef CONFIG_PWM_CAPTURE
static int mcux_ftm_pin_configure_capture(const struct device *dev,
uint32_t pwm,
pwm_flags_t flags,
uint32_t channel, pwm_flags_t flags,
pwm_capture_callback_handler_t cb,
void *user_data)
{
const struct mcux_ftm_config *config = dev->config;
struct mcux_ftm_data *data = dev->data;
ftm_dual_edge_capture_param_t *param;
uint32_t pair = pwm / 2U;
uint32_t pair = channel / 2U;
if (pwm & 0x1U) {
if (channel & 0x1U) {
LOG_ERR("PWM capture only supported on even channels");
return -ENOTSUP;
}
@ -207,13 +206,14 @@ static int mcux_ftm_pin_configure_capture(const struct device *dev,
return 0;
}
static int mcux_ftm_pin_enable_capture(const struct device *dev, uint32_t pwm)
static int mcux_ftm_pin_enable_capture(const struct device *dev,
uint32_t channel)
{
const struct mcux_ftm_config *config = dev->config;
struct mcux_ftm_data *data = dev->data;
uint32_t pair = pwm / 2U;
uint32_t pair = channel / 2U;
if (pwm & 0x1U) {
if (channel & 0x1U) {
LOG_ERR("PWM capture only supported on even channels");
return -ENOTSUP;
}
@ -245,13 +245,14 @@ static int mcux_ftm_pin_enable_capture(const struct device *dev, uint32_t pwm)
return 0;
}
static int mcux_ftm_pin_disable_capture(const struct device *dev, uint32_t pwm)
static int mcux_ftm_pin_disable_capture(const struct device *dev,
uint32_t channel)
{
const struct mcux_ftm_config *config = dev->config;
struct mcux_ftm_data *data = dev->data;
uint32_t pair = pwm / 2U;
uint32_t pair = channel / 2U;
if (pwm & 0x1U) {
if (channel & 0x1U) {
LOG_ERR("PWM capture only supported on even channels");
return -ENOTSUP;
}
@ -271,12 +272,13 @@ static int mcux_ftm_pin_disable_capture(const struct device *dev, uint32_t pwm)
return 0;
}
static void mcux_ftm_capture_first_edge(const struct device *dev, uint32_t pwm)
static void mcux_ftm_capture_first_edge(const struct device *dev,
uint32_t channel)
{
const struct mcux_ftm_config *config = dev->config;
struct mcux_ftm_data *data = dev->data;
struct mcux_ftm_capture_data *capture;
uint32_t pair = pwm / 2U;
uint32_t pair = channel / 2U;
__ASSERT_NO_MSG(pair < ARRAY_SIZE(data->capture));
capture = &data->capture[pair];
@ -285,13 +287,14 @@ static void mcux_ftm_capture_first_edge(const struct device *dev, uint32_t pwm)
capture->first_edge_overflows = data->overflows;
}
static void mcux_ftm_capture_second_edge(const struct device *dev, uint32_t pwm)
static void mcux_ftm_capture_second_edge(const struct device *dev,
uint32_t channel)
{
const struct mcux_ftm_config *config = dev->config;
struct mcux_ftm_data *data = dev->data;
uint32_t second_edge_overflows = data->overflows;
struct mcux_ftm_capture_data *capture;
uint32_t pair = pwm / 2U;
uint32_t pair = channel / 2U;
uint32_t overflows;
uint32_t first_cnv;
uint32_t second_cnv;
@ -373,8 +376,8 @@ static void mcux_ftm_isr(const struct device *dev)
}
#endif /* CONFIG_PWM_CAPTURE */
static int mcux_ftm_get_cycles_per_sec(const struct device *dev, uint32_t pwm,
uint64_t *cycles)
static int mcux_ftm_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
const struct mcux_ftm_config *config = dev->config;
struct mcux_ftm_data *data = dev->data;

33
drivers/pwm/pwm_mcux_pwt.c
View file

@ -50,12 +50,12 @@ static inline bool mcux_pwt_is_active(const struct device *dev)
return !!(config->base->CS & PWT_CS_PWTEN_MASK);
}
static int mcux_pwt_pin_set(const struct device *dev, uint32_t pwm,
static int mcux_pwt_pin_set(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
ARG_UNUSED(dev);
ARG_UNUSED(pwm);
ARG_UNUSED(channel);
ARG_UNUSED(period_cycles);
ARG_UNUSED(pulse_cycles);
ARG_UNUSED(flags);
@ -66,16 +66,15 @@ static int mcux_pwt_pin_set(const struct device *dev, uint32_t pwm,
}
static int mcux_pwt_pin_configure_capture(const struct device *dev,
uint32_t pwm,
pwm_flags_t flags,
uint32_t channel, pwm_flags_t flags,
pwm_capture_callback_handler_t cb,
void *user_data)
{
const struct mcux_pwt_config *config = dev->config;
struct mcux_pwt_data *data = dev->data;
if (pwm >= PWT_INPUTS) {
LOG_ERR("invalid channel %d", pwm);
if (channel >= PWT_INPUTS) {
LOG_ERR("invalid channel %d", channel);
return -EINVAL;
}
@ -87,7 +86,7 @@ static int mcux_pwt_pin_configure_capture(const struct device *dev,
data->callback = cb;
data->user_data = user_data;
data->pwt_config.inputSelect = pwm;
data->pwt_config.inputSelect = channel;
data->continuous =
(flags & PWM_CAPTURE_MODE_MASK) == PWM_CAPTURE_MODE_CONTINUOUS;
@ -102,13 +101,14 @@ static int mcux_pwt_pin_configure_capture(const struct device *dev,
return 0;
}
static int mcux_pwt_pin_enable_capture(const struct device *dev, uint32_t pwm)
static int mcux_pwt_pin_enable_capture(const struct device *dev,
uint32_t channel)
{
const struct mcux_pwt_config *config = dev->config;
struct mcux_pwt_data *data = dev->data;
if (pwm >= PWT_INPUTS) {
LOG_ERR("invalid channel %d", pwm);
if (channel >= PWT_INPUTS) {
LOG_ERR("invalid channel %d", channel);
return -EINVAL;
}
@ -130,12 +130,13 @@ static int mcux_pwt_pin_enable_capture(const struct device *dev, uint32_t pwm)
return 0;
}
static int mcux_pwt_pin_disable_capture(const struct device *dev, uint32_t pwm)
static int mcux_pwt_pin_disable_capture(const struct device *dev,
uint32_t channel)
{
const struct mcux_pwt_config *config = dev->config;
if (pwm >= PWT_INPUTS) {
LOG_ERR("invalid channel %d", pwm);
if (channel >= PWT_INPUTS) {
LOG_ERR("invalid channel %d", channel);
return -EINVAL;
}
@ -263,13 +264,13 @@ static void mcux_pwt_isr(const struct device *dev)
}
}
static int mcux_pwt_get_cycles_per_sec(const struct device *dev, uint32_t pwm,
uint64_t *cycles)
static int mcux_pwt_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
const struct mcux_pwt_config *config = dev->config;
struct mcux_pwt_data *data = dev->data;
ARG_UNUSED(pwm);
ARG_UNUSED(channel);
*cycles = data->clock_freq >> config->prescale;

35
drivers/pwm/pwm_mcux_sctimer.c
View file

@ -35,7 +35,7 @@ struct pwm_mcux_sctimer_data {
sctimer_pwm_signal_param_t channel[CHANNEL_COUNT];
};
static int mcux_sctimer_pwm_pin_set(const struct device *dev, uint32_t pwm,
static int mcux_sctimer_pwm_pin_set(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
@ -43,7 +43,7 @@ static int mcux_sctimer_pwm_pin_set(const struct device *dev, uint32_t pwm,
struct pwm_mcux_sctimer_data *data = dev->data;
uint8_t duty_cycle;
if (pwm >= CHANNEL_COUNT) {
if (channel >= CHANNEL_COUNT) {
LOG_ERR("Invalid channel");
return -EINVAL;
}
@ -54,9 +54,9 @@ static int mcux_sctimer_pwm_pin_set(const struct device *dev, uint32_t pwm,
}
if ((flags & PWM_POLARITY_INVERTED) == 0) {
data->channel[pwm].level = kSCTIMER_HighTrue;
data->channel[channel].level = kSCTIMER_HighTrue;
} else {
data->channel[pwm].level = kSCTIMER_LowTrue;
data->channel[channel].level = kSCTIMER_LowTrue;
}
duty_cycle = 100 * pulse_cycles / period_cycles;
@ -67,25 +67,25 @@ static int mcux_sctimer_pwm_pin_set(const struct device *dev, uint32_t pwm,
SCTIMER_StopTimer(config->base, kSCTIMER_Counter_U);
/* Set the output to inactive State */
if (data->channel[pwm].level == kSCTIMER_HighTrue) {
base->OUTPUT &= ~(1UL << pwm);
if (data->channel[channel].level == kSCTIMER_HighTrue) {
base->OUTPUT &= ~(1UL << channel);
} else {
base->OUTPUT |= (1UL << pwm);
base->OUTPUT |= (1UL << channel);
}
/* Make sure the PWM is setup */
if (data->period_cycles[pwm] != 0) {
if (data->period_cycles[channel] != 0) {
SCTIMER_StartTimer(config->base, kSCTIMER_Counter_U);
}
return 0;
}
if (period_cycles != data->period_cycles[pwm]) {
if (period_cycles != data->period_cycles[channel]) {
uint32_t clock_freq;
uint32_t pwm_freq;
data->period_cycles[pwm] = period_cycles;
data->period_cycles[channel] = period_cycles;
/*
* Do not divide by the prescale factor as this is accounted for in
@ -102,23 +102,26 @@ static int mcux_sctimer_pwm_pin_set(const struct device *dev, uint32_t pwm,
SCTIMER_StopTimer(config->base, kSCTIMER_Counter_U);
LOG_DBG("SETUP dutycycle to %u\n", duty_cycle);
data->channel[pwm].dutyCyclePercent = duty_cycle;
if (SCTIMER_SetupPwm(config->base, &data->channel[pwm], kSCTIMER_EdgeAlignedPwm,
pwm_freq, clock_freq, &data->event_number[pwm]) == kStatus_Fail) {
data->channel[channel].dutyCyclePercent = duty_cycle;
if (SCTIMER_SetupPwm(config->base, &data->channel[channel],
kSCTIMER_EdgeAlignedPwm, pwm_freq,
clock_freq, &data->event_number[channel]) == kStatus_Fail) {
LOG_ERR("Could not set up pwm");
return -ENOTSUP;
}
SCTIMER_StartTimer(config->base, kSCTIMER_Counter_U);
} else {
SCTIMER_UpdatePwmDutycycle(config->base, pwm, duty_cycle, data->event_number[pwm]);
SCTIMER_UpdatePwmDutycycle(config->base, channel, duty_cycle,
data->event_number[channel]);
}
return 0;
}
static int mcux_sctimer_pwm_get_cycles_per_sec(const struct device *dev, uint32_t pwm,
uint64_t *cycles)
static int mcux_sctimer_pwm_get_cycles_per_sec(const struct device *dev,
uint32_t channel,
uint64_t *cycles)
{
const struct pwm_mcux_sctimer_config *config = dev->config;

20
drivers/pwm/pwm_mcux_tpm.c
View file

@ -41,7 +41,7 @@ struct mcux_tpm_data {
tpm_chnl_pwm_signal_param_t channel[MAX_CHANNELS];
};
static int mcux_tpm_pin_set(const struct device *dev, uint32_t pwm,
static int mcux_tpm_pin_set(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
@ -54,18 +54,18 @@ static int mcux_tpm_pin_set(const struct device *dev, uint32_t pwm,
return -ENOTSUP;
}
if (pwm >= config->channel_count) {
if (channel >= config->channel_count) {
LOG_ERR("Invalid channel");
return -ENOTSUP;
}
duty_cycle = pulse_cycles * 100U / period_cycles;
data->channel[pwm].dutyCyclePercent = duty_cycle;
data->channel[channel].dutyCyclePercent = duty_cycle;
if ((flags & PWM_POLARITY_INVERTED) == 0) {
data->channel[pwm].level = kTPM_HighTrue;
data->channel[channel].level = kTPM_HighTrue;
} else {
data->channel[pwm].level = kTPM_LowTrue;
data->channel[channel].level = kTPM_LowTrue;
}
LOG_DBG("pulse_cycles=%d, period_cycles=%d, duty_cycle=%d, flags=%d",
@ -108,17 +108,17 @@ static int mcux_tpm_pin_set(const struct device *dev, uint32_t pwm,
}
TPM_StartTimer(config->base, config->tpm_clock_source);
} else {
TPM_UpdateChnlEdgeLevelSelect(config->base, pwm,
data->channel[pwm].level);
TPM_UpdatePwmDutycycle(config->base, pwm, config->mode,
TPM_UpdateChnlEdgeLevelSelect(config->base, channel,
data->channel[channel].level);
TPM_UpdatePwmDutycycle(config->base, channel, config->mode,
duty_cycle);
}
return 0;
}
static int mcux_tpm_get_cycles_per_sec(const struct device *dev, uint32_t pwm,
uint64_t *cycles)
static int mcux_tpm_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
const struct mcux_tpm_config *config = dev->config;
struct mcux_tpm_data *data = dev->data;

10
drivers/pwm/pwm_npcx.c
View file

@ -88,12 +88,12 @@ static void pwm_npcx_configure(const struct device *dev, int clk_bus)
}
/* PWM api functions */
static int pwm_npcx_pin_set(const struct device *dev, uint32_t pwm,
static int pwm_npcx_pin_set(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
/* Single channel for each pwm device */
ARG_UNUSED(pwm);
ARG_UNUSED(channel);
struct pwm_npcx_data *const data = dev->data;
struct pwm_reg *const inst = HAL_INSTANCE(dev);
int prescaler;
@ -160,11 +160,11 @@ static int pwm_npcx_pin_set(const struct device *dev, uint32_t pwm,
return 0;
}
static int pwm_npcx_get_cycles_per_sec(const struct device *dev, uint32_t pwm,
uint64_t *cycles)
static int pwm_npcx_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
/* Single channel for each pwm device */
ARG_UNUSED(pwm);
ARG_UNUSED(channel);
struct pwm_npcx_data *const data = dev->data;
*cycles = data->cycles_per_sec;

6
drivers/pwm/pwm_nrf5_sw.c
View file

@ -107,7 +107,7 @@ static uint32_t pwm_period_check(struct pwm_data *data, uint8_t map_size,
return 0;
}
static int pwm_nrf5_sw_pin_set(const struct device *dev, uint32_t pwm,
static int pwm_nrf5_sw_pin_set(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
@ -116,7 +116,6 @@ static int pwm_nrf5_sw_pin_set(const struct device *dev, uint32_t pwm,
NRF_RTC_Type *rtc = pwm_config_rtc(config);
struct pwm_data *data = dev->data;
uint32_t ppi_mask;
uint8_t channel = pwm;
uint8_t active_level;
uint8_t psel_ch;
uint8_t gpiote_ch;
@ -277,8 +276,7 @@ static int pwm_nrf5_sw_pin_set(const struct device *dev, uint32_t pwm,
}
static int pwm_nrf5_sw_get_cycles_per_sec(const struct device *dev,
uint32_t pwm,
uint64_t *cycles)
uint32_t channel, uint64_t *cycles)
{
const struct pwm_config *config = dev->config;

5
drivers/pwm/pwm_nrfx.c
View file

@ -121,7 +121,7 @@ static bool channel_psel_get(uint32_t channel, uint32_t *psel,
== PWM_PSEL_OUT_CONNECT_Connected);
}
static int pwm_nrfx_pin_set(const struct device *dev, uint32_t pwm,
static int pwm_nrfx_pin_set(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
@ -132,7 +132,6 @@ static int pwm_nrfx_pin_set(const struct device *dev, uint32_t pwm,
*/
const struct pwm_nrfx_config *config = dev->config;
struct pwm_nrfx_data *data = dev->data;
uint8_t channel = pwm;
bool inverted = (flags & PWM_POLARITY_INVERTED);
bool was_stopped;
@ -227,7 +226,7 @@ static int pwm_nrfx_pin_set(const struct device *dev, uint32_t pwm,
return 0;
}
static int pwm_nrfx_get_cycles_per_sec(const struct device *dev, uint32_t pwm,
static int pwm_nrfx_get_cycles_per_sec(const struct device *dev, uint32_t channel,
uint64_t *cycles)
{
/* TODO: Since this function might be removed, we will always return

19
drivers/pwm/pwm_rv32m1_tpm.c
View file

@ -38,7 +38,7 @@ struct rv32m1_tpm_data {
tpm_chnl_pwm_signal_param_t channel[MAX_CHANNELS];
};
static int rv32m1_tpm_pin_set(const struct device *dev, uint32_t pwm,
static int rv32m1_tpm_pin_set(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
@ -51,18 +51,18 @@ static int rv32m1_tpm_pin_set(const struct device *dev, uint32_t pwm,
return -ENOTSUP;
}
if (pwm >= config->channel_count) {
if (channel >= config->channel_count) {
LOG_ERR("Invalid channel");
return -ENOTSUP;
}
duty_cycle = pulse_cycles * 100U / period_cycles;
data->channel[pwm].dutyCyclePercent = duty_cycle;
data->channel[channel].dutyCyclePercent = duty_cycle;
if ((flags & PWM_POLARITY_INVERTED) == 0) {
data->channel[pwm].level = kTPM_HighTrue;
data->channel[channel].level = kTPM_HighTrue;
} else {
data->channel[pwm].level = kTPM_LowTrue;
data->channel[channel].level = kTPM_LowTrue;
}
LOG_DBG("pulse_cycles=%d, period_cycles=%d, duty_cycle=%d, flags=%d",
@ -105,9 +105,9 @@ static int rv32m1_tpm_pin_set(const struct device *dev, uint32_t pwm,
}
TPM_StartTimer(config->base, config->tpm_clock_source);
} else {
TPM_UpdateChnlEdgeLevelSelect(config->base, pwm,
data->channel[pwm].level);
TPM_UpdatePwmDutycycle(config->base, pwm, config->mode,
TPM_UpdateChnlEdgeLevelSelect(config->base, channel,
data->channel[channel].level);
TPM_UpdatePwmDutycycle(config->base, channel, config->mode,
duty_cycle);
}
@ -115,8 +115,7 @@ static int rv32m1_tpm_pin_set(const struct device *dev, uint32_t pwm,
}
static int rv32m1_tpm_get_cycles_per_sec(const struct device *dev,
uint32_t pwm,
uint64_t *cycles)
uint32_t channel, uint64_t *cycles)
{
const struct rv32m1_tpm_config *config = dev->config;
struct rv32m1_tpm_data *data = dev->data;

16
drivers/pwm/pwm_sam.c
View file

@ -24,8 +24,8 @@ struct sam_pwm_config {
uint8_t divider;
};
static int sam_pwm_get_cycles_per_sec(const struct device *dev, uint32_t pwm,
uint64_t *cycles)
static int sam_pwm_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
const struct sam_pwm_config *config = dev->config;
uint8_t prescaler = config->prescaler;
@ -37,7 +37,7 @@ static int sam_pwm_get_cycles_per_sec(const struct device *dev, uint32_t pwm,
return 0;
}
static int sam_pwm_pin_set(const struct device *dev, uint32_t ch,
static int sam_pwm_pin_set(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
@ -45,7 +45,7 @@ static int sam_pwm_pin_set(const struct device *dev, uint32_t ch,
Pwm * const pwm = config->regs;
if (ch >= PWMCHNUM_NUMBER) {
if (channel >= PWMCHNUM_NUMBER) {
return -EINVAL;
}
@ -63,16 +63,16 @@ static int sam_pwm_pin_set(const struct device *dev, uint32_t ch,
}
/* Select clock A */
pwm->PWM_CH_NUM[ch].PWM_CMR = PWM_CMR_CPRE_CLKA_Val;
pwm->PWM_CH_NUM[channel].PWM_CMR = PWM_CMR_CPRE_CLKA_Val;
/* Update period and pulse using the update registers, so that the
* change is triggered at the next PWM period.
*/
pwm->PWM_CH_NUM[ch].PWM_CPRDUPD = period_cycles;
pwm->PWM_CH_NUM[ch].PWM_CDTYUPD = pulse_cycles;
pwm->PWM_CH_NUM[channel].PWM_CPRDUPD = period_cycles;
pwm->PWM_CH_NUM[channel].PWM_CDTYUPD = pulse_cycles;
/* Enable the output */
pwm->PWM_ENA = 1 << ch;
pwm->PWM_ENA = 1 << channel;
return 0;
}

16
drivers/pwm/pwm_sam0_tcc.c
View file

@ -43,12 +43,12 @@ static void wait_synchronization(Tcc *regs)
}
}
static int pwm_sam0_get_cycles_per_sec(const struct device *dev, uint32_t ch,
uint64_t *cycles)
static int pwm_sam0_get_cycles_per_sec(const struct device *dev,
uint32_t channel, uint64_t *cycles)
{
const struct pwm_sam0_config *const cfg = dev->config;
if (ch >= cfg->channels) {
if (channel >= cfg->channels) {
return -EINVAL;
}
*cycles = cfg->freq;
@ -56,18 +56,18 @@ static int pwm_sam0_get_cycles_per_sec(const struct device *dev, uint32_t ch,
return 0;
}
static int pwm_sam0_pin_set(const struct device *dev, uint32_t ch,
static int pwm_sam0_pin_set(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
const struct pwm_sam0_config *const cfg = dev->config;
Tcc *regs = cfg->regs;
uint32_t top = 1 << cfg->counter_size;
uint32_t invert_mask = 1 << ch;
uint32_t invert_mask = 1 << channel;
bool invert = ((flags & PWM_POLARITY_INVERTED) != 0);
bool inverted = ((regs->DRVCTRL.vec.INVEN & invert_mask) != 0);
if (ch >= cfg->channels) {
if (channel >= cfg->channels) {
return -EINVAL;
}
if (period_cycles >= top || pulse_cycles >= top) {
@ -80,11 +80,11 @@ static int pwm_sam0_pin_set(const struct device *dev, uint32_t ch,
*/
#ifdef TCC_PERBUF_PERBUF
/* SAME51 naming */
regs->CCBUF[ch].reg = TCC_CCBUF_CCBUF(pulse_cycles);
regs->CCBUF[channel].reg = TCC_CCBUF_CCBUF(pulse_cycles);
regs->PERBUF.reg = TCC_PERBUF_PERBUF(period_cycles);
#else
/* SAMD21 naming */
regs->CCB[ch].reg = TCC_CCB_CCB(pulse_cycles);
regs->CCB[channel].reg = TCC_CCB_CCB(pulse_cycles);
regs->PERB.reg = TCC_PERB_PERB(period_cycles);
#endif

26
drivers/pwm/pwm_shell.c
View file

@ -23,7 +23,7 @@ struct args_index {
static const struct args_index args_indx = {
.device = 1,
.pwm = 2,
.channel = 2,
.period = 3,
.pulse = 4,
.flags = 5,
@ -35,7 +35,7 @@ static int cmd_cycles(const struct shell *shell, size_t argc, char **argv)
const struct device *dev;
uint32_t period;
uint32_t pulse;
uint32_t pwm;
uint32_t channel;
int err;
dev = device_get_binding(argv[args_indx.device]);
@ -44,7 +44,7 @@ static int cmd_cycles(const struct shell *shell, size_t argc, char **argv)
return -EINVAL;
}
pwm = strtoul(argv[args_indx.pwm], NULL, 0);
channel = strtoul(argv[args_indx.channel], NULL, 0);
period = strtoul(argv[args_indx.period], NULL, 0);
pulse = strtoul(argv[args_indx.pulse], NULL, 0);
@ -52,7 +52,7 @@ static int cmd_cycles(const struct shell *shell, size_t argc, char **argv)
flags = strtoul(argv[args_indx.flags], NULL, 0);
}
err = pwm_pin_set_cycles(dev, pwm, period, pulse, flags);
err = pwm_pin_set_cycles(dev, channel, period, pulse, flags);
if (err) {
shell_error(shell, "failed to setup PWM (err %d)",
err);
@ -68,7 +68,7 @@ static int cmd_usec(const struct shell *shell, size_t argc, char **argv)
const struct device *dev;
uint32_t period;
uint32_t pulse;
uint32_t pwm;
uint32_t channel;
int err;
dev = device_get_binding(argv[args_indx.device]);
@ -77,7 +77,7 @@ static int cmd_usec(const struct shell *shell, size_t argc, char **argv)
return -EINVAL;
}
pwm = strtoul(argv[args_indx.pwm], NULL, 0);
channel = strtoul(argv[args_indx.channel], NULL, 0);
period = strtoul(argv[args_indx.period], NULL, 0);
pulse = strtoul(argv[args_indx.pulse], NULL, 0);
@ -85,7 +85,7 @@ static int cmd_usec(const struct shell *shell, size_t argc, char **argv)
flags = strtoul(argv[args_indx.flags], NULL, 0);
}
err = pwm_pin_set_usec(dev, pwm, period, pulse, flags);
err = pwm_pin_set_usec(dev, channel, period, pulse, flags);
if (err) {
shell_error(shell, "failed to setup PWM (err %d)", err);
return err;
@ -100,7 +100,7 @@ static int cmd_nsec(const struct shell *shell, size_t argc, char **argv)
const struct device *dev;
uint32_t period;
uint32_t pulse;
uint32_t pwm;
uint32_t channel;
int err;
dev = device_get_binding(argv[args_indx.device]);
@ -109,7 +109,7 @@ static int cmd_nsec(const struct shell *shell, size_t argc, char **argv)
return -EINVAL;
}
pwm = strtoul(argv[args_indx.pwm], NULL, 0);
channel = strtoul(argv[args_indx.channel], NULL, 0);
period = strtoul(argv[args_indx.period], NULL, 0);
pulse = strtoul(argv[args_indx.pulse], NULL, 0);
@ -117,7 +117,7 @@ static int cmd_nsec(const struct shell *shell, size_t argc, char **argv)
flags = strtoul(argv[args_indx.flags], NULL, 0);
}
err = pwm_pin_set_nsec(dev, pwm, period, pulse, flags);
err = pwm_pin_set_nsec(dev, channel, period, pulse, flags);
if (err) {
shell_error(shell, "failed to setup PWM (err %d)", err);
return err;
@ -127,11 +127,11 @@ static int cmd_nsec(const struct shell *shell, size_t argc, char **argv)
}
SHELL_STATIC_SUBCMD_SET_CREATE(pwm_cmds,
SHELL_CMD_ARG(cycles, NULL, "<device> <pwm> <period in cycles> "
SHELL_CMD_ARG(cycles, NULL, "<device> <channel> <period in cycles> "
"<pulse width in cycles> [flags]", cmd_cycles, 5, 1),
SHELL_CMD_ARG(usec, NULL, "<device> <pwm> <period in usec> "
SHELL_CMD_ARG(usec, NULL, "<device> <channel> <period in usec> "
"<pulse width in usec> [flags]", cmd_usec, 5, 1),
SHELL_CMD_ARG(nsec, NULL, "<device> <pwm> <period in nsec> "
SHELL_CMD_ARG(nsec, NULL, "<device> <channel> <period in nsec> "
"<pulse width in nsec> [flags]", cmd_nsec, 5, 1),
SHELL_SUBCMD_SET_END
);

23
drivers/pwm/pwm_sifive.c
View file

@ -106,10 +106,8 @@ static int pwm_sifive_init(const struct device *dev)
return 0;
}
static int pwm_sifive_pin_set(const struct device *dev,
uint32_t pwm,
uint32_t period_cycles,
uint32_t pulse_cycles,
static int pwm_sifive_pin_set(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
const struct pwm_sifive_cfg *config = dev->config;
@ -122,13 +120,13 @@ static int pwm_sifive_pin_set(const struct device *dev,
return -ENOTSUP;
}
if (pwm >= SF_NUMCHANNELS) {
LOG_ERR("The requested PWM channel %d is invalid\n", pwm);
if (channel >= SF_NUMCHANNELS) {
LOG_ERR("The requested PWM channel %d is invalid\n", channel);
return -EINVAL;
}
/* Channel 0 sets the period, we can't output PWM with it */
if (pwm == 0U) {
if (channel == 0U) {
LOG_ERR("PWM channel 0 cannot be configured\n");
return -ENOTSUP;
}
@ -170,21 +168,20 @@ static int pwm_sifive_pin_set(const struct device *dev,
/* Set the duty cycle by setting pwmcmpX */
sys_write32((pulse_cycles >> pwmscale),
PWM_REG(config, REG_PWMCMP(pwm)));
PWM_REG(config, REG_PWMCMP(channel)));
LOG_DBG("channel: %d, pwmscale: %d, pwmcmp0: %d, pwmcmp%d: %d",
pwm,
channel,
pwmscale,
(period_cycles >> pwmscale),
pwm,
channel,
(pulse_cycles >> pwmscale));
return 0;
}
static int pwm_sifive_get_cycles_per_sec(const struct device *dev,
uint32_t pwm,
uint64_t *cycles)
uint32_t channel, uint64_t *cycles)
{
const struct pwm_sifive_cfg *config;
@ -200,7 +197,7 @@ static int pwm_sifive_get_cycles_per_sec(const struct device *dev,
}
/* Fail if we don't have that channel */
if (pwm >= SF_NUMCHANNELS) {
if (channel >= SF_NUMCHANNELS) {
return -EINVAL;
}

81
drivers/pwm/pwm_stm32.c
View file

@ -231,17 +231,17 @@ static int get_tim_clk(const struct stm32_pclken *pclken, uint32_t *tim_clk)
return 0;
}
static int pwm_stm32_pin_set(const struct device *dev, uint32_t pwm,
static int pwm_stm32_pin_set(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
const struct pwm_stm32_config *cfg = dev->config;
uint32_t channel;
uint32_t current_channel; /* complementary output if used */
uint32_t ll_channel;
uint32_t current_ll_channel; /* complementary output if used */
if (pwm < 1u || pwm > TIMER_MAX_CH) {
LOG_ERR("Invalid channel (%d)", pwm);
if (channel < 1u || channel > TIMER_MAX_CH) {
LOG_ERR("Invalid channel (%d)", channel);
return -EINVAL;
}
@ -270,7 +270,7 @@ static int pwm_stm32_pin_set(const struct device *dev, uint32_t pwm,
}
#ifdef CONFIG_PWM_CAPTURE
if ((pwm == 1u) || (pwm == 2u)) {
if ((channel == 1u) || (channel == 2u)) {
if (LL_TIM_IsEnabledIT_CC1(cfg->timer) ||
LL_TIM_IsEnabledIT_CC2(cfg->timer)) {
LOG_ERR("Cannot set PWM output, capture in progress");
@ -279,28 +279,28 @@ static int pwm_stm32_pin_set(const struct device *dev, uint32_t pwm,
}
#endif /* CONFIG_PWM_CAPTURE */
channel = ch2ll[pwm - 1u];
ll_channel = ch2ll[channel - 1u];
/* in LL_TIM_CC_DisableChannel and LL_TIM_CC_IsEnabledChannel,
* the channel param could be the complementary one
*/
if ((flags & PWM_STM32_COMPLEMENTARY_MASK) == PWM_STM32_COMPLEMENTARY) {
if (pwm > ARRAY_SIZE(ch2ll_n)) {
if (channel > ARRAY_SIZE(ch2ll_n)) {
/* setting a flag on a channel that has not this capability */
LOG_ERR("Channel %d has NO complementary output", pwm);
LOG_ERR("Channel %d has NO complementary output", channel);
return -EINVAL;
}
current_channel = ch2ll_n[pwm - 1u];
current_ll_channel = ch2ll_n[channel - 1u];
} else {
current_channel = channel;
current_ll_channel = ll_channel;
}
if (period_cycles == 0u) {
LL_TIM_CC_DisableChannel(cfg->timer, current_channel);
LL_TIM_CC_DisableChannel(cfg->timer, current_ll_channel);
return 0;
}
if (!LL_TIM_CC_IsEnabledChannel(cfg->timer, current_channel)) {
if (!LL_TIM_CC_IsEnabledChannel(cfg->timer, current_ll_channel)) {
LL_TIM_OC_InitTypeDef oc_init;
LL_TIM_OC_StructInit(&oc_init);
@ -333,20 +333,20 @@ static int pwm_stm32_pin_set(const struct device *dev, uint32_t pwm,
#endif /* CONFIG_PWM_CAPTURE */
/* in LL_TIM_OC_Init, the channel is always the non-complementary */
if (LL_TIM_OC_Init(cfg->timer, channel, &oc_init) != SUCCESS) {
if (LL_TIM_OC_Init(cfg->timer, ll_channel, &oc_init) != SUCCESS) {
LOG_ERR("Could not initialize timer channel output");
return -EIO;
}
LL_TIM_EnableARRPreload(cfg->timer);
/* in LL_TIM_OC_EnablePreload, the channel is always the non-complementary */
LL_TIM_OC_EnablePreload(cfg->timer, channel);
LL_TIM_OC_EnablePreload(cfg->timer, ll_channel);
LL_TIM_SetAutoReload(cfg->timer, period_cycles);
LL_TIM_GenerateEvent_UPDATE(cfg->timer);
} else {
/* in LL_TIM_OC_SetPolarity, the channel could be the complementary one */
LL_TIM_OC_SetPolarity(cfg->timer, current_channel, get_polarity(flags));
set_timer_compare[pwm - 1u](cfg->timer, pulse_cycles);
LL_TIM_OC_SetPolarity(cfg->timer, current_ll_channel, get_polarity(flags));
set_timer_compare[channel - 1u](cfg->timer, pulse_cycles);
LL_TIM_SetAutoReload(cfg->timer, period_cycles);
}
@ -354,8 +354,8 @@ static int pwm_stm32_pin_set(const struct device *dev, uint32_t pwm,
}
#ifdef CONFIG_PWM_CAPTURE
static int init_capture_channel(const struct device *dev, uint32_t pwm,
pwm_flags_t flags, uint32_t channel)
static int init_capture_channel(const struct device *dev, uint32_t channel,
pwm_flags_t flags, uint32_t ll_channel)
{
const struct pwm_stm32_config *cfg = dev->config;
bool is_inverted = (flags & PWM_POLARITY_MASK) == PWM_POLARITY_INVERTED;
@ -365,8 +365,8 @@ static int init_capture_channel(const struct device *dev, uint32_t pwm,
ic.ICPrescaler = TIM_ICPSC_DIV1;
ic.ICFilter = LL_TIM_IC_FILTER_FDIV1;
if (channel == LL_TIM_CHANNEL_CH1) {
if (pwm == 1u) {
if (ll_channel == LL_TIM_CHANNEL_CH1) {
if (channel == 1u) {
ic.ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
ic.ICPolarity = is_inverted ? LL_TIM_IC_POLARITY_FALLING
: LL_TIM_IC_POLARITY_RISING;
@ -376,7 +376,7 @@ static int init_capture_channel(const struct device *dev, uint32_t pwm,
: LL_TIM_IC_POLARITY_FALLING;
}
} else {
if (pwm == 1u) {
if (channel == 1u) {
ic.ICActiveInput = LL_TIM_ACTIVEINPUT_INDIRECTTI;
ic.ICPolarity = is_inverted ? LL_TIM_IC_POLARITY_RISING
: LL_TIM_IC_POLARITY_FALLING;
@ -387,7 +387,7 @@ static int init_capture_channel(const struct device *dev, uint32_t pwm,
}
}
if (LL_TIM_IC_Init(cfg->timer, channel, &ic) != SUCCESS) {
if (LL_TIM_IC_Init(cfg->timer, ll_channel, &ic) != SUCCESS) {
LOG_ERR("Could not initialize channel for PWM capture");
return -EIO;
}
@ -395,9 +395,9 @@ static int init_capture_channel(const struct device *dev, uint32_t pwm,
return 0;
}
static int pwm_stm32_pin_configure_capture(const struct device *dev,
uint32_t pwm, pwm_flags_t flags,
pwm_capture_callback_handler_t cb, void *user_data)
static int pwm_stm32_pin_configure_capture(
const struct device *dev, uint32_t channel, pwm_flags_t flags,
pwm_capture_callback_handler_t cb, void *user_data)
{
/*
@ -412,7 +412,7 @@ static int pwm_stm32_pin_configure_capture(const struct device *dev,
struct pwm_stm32_capture_data *cpt = &data->capture;
int ret;
if ((pwm != 1u) && (pwm != 2u)) {
if ((channel != 1u) && (channel != 2u)) {
LOG_ERR("PWM capture only supported on first two channels");
return -ENOTSUP;
}
@ -442,17 +442,17 @@ static int pwm_stm32_pin_configure_capture(const struct device *dev,
/* Prevents faulty behavior while making changes */
LL_TIM_SetSlaveMode(cfg->timer, LL_TIM_SLAVEMODE_DISABLED);
ret = init_capture_channel(dev, pwm, flags, LL_TIM_CHANNEL_CH1);
ret = init_capture_channel(dev, channel, flags, LL_TIM_CHANNEL_CH1);
if (ret < 0) {
return ret;
}
ret = init_capture_channel(dev, pwm, flags, LL_TIM_CHANNEL_CH2);
ret = init_capture_channel(dev, channel, flags, LL_TIM_CHANNEL_CH2);
if (ret < 0) {
return ret;
}
if (pwm == 1u) {
if (channel == 1u) {
LL_TIM_SetTriggerInput(cfg->timer, LL_TIM_TS_TI1FP1);
} else {
LL_TIM_SetTriggerInput(cfg->timer, LL_TIM_TS_TI2FP2);
@ -470,12 +470,13 @@ static int pwm_stm32_pin_configure_capture(const struct device *dev,
return 0;
}
static int pwm_stm32_pin_enable_capture(const struct device *dev, uint32_t pwm)
static int pwm_stm32_pin_enable_capture(const struct device *dev,
uint32_t channel)
{
const struct pwm_stm32_config *cfg = dev->config;
struct pwm_stm32_data *data = dev->data;
if ((pwm != 1u) && (pwm != 2u)) {
if ((channel != 1u) && (channel != 2u)) {
LOG_ERR("PWM capture only supported on first two channels");
return -EINVAL;
}
@ -498,7 +499,7 @@ static int pwm_stm32_pin_enable_capture(const struct device *dev, uint32_t pwm)
LL_TIM_ClearFlag_UPDATE(cfg->timer);
LL_TIM_SetUpdateSource(cfg->timer, LL_TIM_UPDATESOURCE_COUNTER);
if (pwm == 1u) {
if (channel == 1u) {
LL_TIM_EnableIT_CC1(cfg->timer);
} else {
LL_TIM_EnableIT_CC2(cfg->timer);
@ -510,17 +511,18 @@ static int pwm_stm32_pin_enable_capture(const struct device *dev, uint32_t pwm)
return 0;
}
static int pwm_stm32_pin_disable_capture(const struct device *dev, uint32_t pwm)
static int pwm_stm32_pin_disable_capture(const struct device *dev,
uint32_t channel)
{
const struct pwm_stm32_config *cfg = dev->config;
if ((pwm != 1u) && (pwm != 2u)) {
if ((channel != 1u) && (channel != 2u)) {
LOG_ERR("PWM capture only supported on first two channels");
return -EINVAL;
}
LL_TIM_SetUpdateSource(cfg->timer, LL_TIM_UPDATESOURCE_REGULAR);
if (pwm == 1u) {
if (channel == 1u) {
LL_TIM_DisableIT_CC1(cfg->timer);
} else {
LL_TIM_DisableIT_CC2(cfg->timer);
@ -532,13 +534,13 @@ static int pwm_stm32_pin_disable_capture(const struct device *dev, uint32_t pwm)
return 0;
}
static void get_pwm_capture(const struct device *dev, uint32_t pwm)
static void get_pwm_capture(const struct device *dev, uint32_t channel)
{
const struct pwm_stm32_config *cfg = dev->config;
struct pwm_stm32_data *data = dev->data;
struct pwm_stm32_capture_data *cpt = &data->capture;
if (pwm == 1u) {
if (channel == 1u) {
cpt->period = LL_TIM_IC_GetCaptureCH1(cfg->timer);
cpt->pulse = LL_TIM_IC_GetCaptureCH2(cfg->timer);
} else {
@ -602,8 +604,7 @@ static void pwm_stm32_isr(const struct device *dev)
#endif /* CONFIG_PWM_CAPTURE */
static int pwm_stm32_get_cycles_per_sec(const struct device *dev,
uint32_t pwm,
uint64_t *cycles)
uint32_t channel, uint64_t *cycles)
{
struct pwm_stm32_data *data = dev->data;
const struct pwm_stm32_config *cfg = dev->config;

12
drivers/pwm/pwm_test.c
View file

@ -15,7 +15,7 @@
#define DT_DRV_COMPAT vnd_pwm
static int vnd_pwm_pin_set(const struct device *dev, uint32_t pwm,
static int vnd_pwm_pin_set(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
@ -24,8 +24,7 @@ static int vnd_pwm_pin_set(const struct device *dev, uint32_t pwm,
#ifdef CONFIG_PWM_CAPTURE
static int vnd_pwm_pin_configure_capture(const struct device *dev,
uint32_t pwm,
pwm_flags_t flags,
uint32_t channel, pwm_flags_t flags,
pwm_capture_callback_handler_t cb,
void *user_data)
{
@ -33,21 +32,20 @@ static int vnd_pwm_pin_configure_capture(const struct device *dev,
}
static int vnd_pwm_pin_enable_capture(const struct device *dev,
uint32_t pwm)
uint32_t channel)
{
return -ENOTSUP;
}
static int vnd_pwm_pin_disable_capture(const struct device *dev,
uint32_t pwm)
uint32_t channel)
{
return -ENOTSUP;
}
#endif /* CONFIG_PWM_CAPTURE */
static int vnd_pwm_get_cycles_per_sec(const struct device *dev,
uint32_t pwm,
uint64_t *cycles)
uint32_t channel, uint64_t *cycles)
{
return -ENOTSUP;
}

8
drivers/pwm/pwm_xlnx_axi_timer.c
View file

@ -60,7 +60,7 @@ static inline void xlnx_axi_timer_write32(const struct device *dev,
sys_write32(value, config->base + offset);
}
static int xlnx_axi_timer_pin_set(const struct device *dev, uint32_t pwm,
static int xlnx_axi_timer_pin_set(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
@ -70,7 +70,7 @@ static int xlnx_axi_timer_pin_set(const struct device *dev, uint32_t pwm,
uint32_t tlr0;
uint32_t tlr1;
if (pwm != 0) {
if (channel != 0) {
return -ENOTSUP;
}
@ -159,11 +159,11 @@ static int xlnx_axi_timer_pin_set(const struct device *dev, uint32_t pwm,
}
static int xlnx_axi_timer_get_cycles_per_sec(const struct device *dev,
uint32_t pwm, uint64_t *cycles)
uint32_t channel, uint64_t *cycles)
{
const struct xlnx_axi_timer_config *config = dev->config;
ARG_UNUSED(pwm);
ARG_UNUSED(channel);
*cycles = config->freq;