Add board support (and documentation) for the Intel Gordon Peak
Module Reference Board, a dev board based on the Apollo Lake SoC.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
These events aren't errors at all, but rather part of normal operation.
They shouldn't trigger error messages, especially given that the console
gets absolutely flooded with them if power management is activated.
Signed-off-by: Benjamin Lindqvist <benjamin.lindqvist@endian.se>
1. Add flash partitions.
2. Add macro DT_START_UP_ENTRY_OFFSET. The entry of the RV32M1 is
not the start of the vector table. Add the macro to inform the
entry offset.
3. Update linker file to support MCUboot
a. For normal cases (CONFIG_BOOTLOADER_MCUBOOT is cleared), the
vector table is located last 256bytes of the flash.
b. If CONFIG_BOOTLOADER_MCUBOOT is set, the vector table is located
after the image header of MCUboot.
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
stm32wb55rg is a dual core SoC (M4/M0) with a radio/protocol stack
running on M0 core. M0 FW starts at flash address 0x80CB000.
So flash size available to zephyr is 812K instead of 1M.
Configure package size to reflect this (flash size is now 812K)
and update MPU setting to exclude M0 FW. From MPU point of view,
we set flash size to 512K since we should chose a size being a power
of 2.
If we consider there will be 2 images partitions in a FOTA scheme,
512 K is beyond image-0 and hence is sufficient to cover application
image.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32WB HCI driver requires definition of 2 RAM regions to support
use of 3 shared memory sections: MAPPING_TABLE, MB_MEM1 and MB_MEM2.
In linker.ld, under conditions of HCI driver to be enabled,
define SRAM1 and SRAM2 based on input defined in stm32wb linker.
Then define the 3 sections MAPPING_TABLE, MB_MEM1 and MB_MEM
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The Apollo Lake SoC no longer uses the legacy PCI driver, so remove
references and supporting code.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
While enabling specific I2C ports does indeed belong at the board
level Kconfig, the selection of driver (I2C_DW) is an SoC-level
choice, so it is moved accordingly.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Which UARTs are broken out from the SoC on a particular board is
board-specific; don't enable UARTs blindly in the SoC Kconfig.
Also, the default UART options are specified in the driver Kconfig, so
the same defaults specified in the SoC Kconfig are redundant. Removed.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
The UART references in dts_fixup.h are actually SoC-specific, not
board-specific, so they are moved. Since this leaves the board fixups
empty, the file is removed.
The SoC fixups are expanded to include the additional two ports that
are present on some revisions of the Apollo Lake.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Several customer configuration (CCFG) settings are useful for
development and deployment. This commit adds support for setting CCFG
values via Kconfig. It follows TI's recommendation of setting CCFG
values and then including the TI provided CCFG. This commit includes
support for enabling the ROM bootloader and additional settings can be
added as needed.
Signed-off-by: Brett Witherspoon <spoonb@cdspooner.com>
The HiFive1 and HiFive1 Rev B share the same clock initialization
code, so put it in soc/riscv32/riscv-privilege/sifive-freedom.
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
The HiFive1 Rev B adds the following features to the
original HiFive1:
- A second UART peripheral 'uart_1'
- A hardware I2C peripheral 'i2c_0'
- Segger J-Link OB
- An ESP32-WROOM attached to the 'spi_1' peripheral bus
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
soc_register.h is available in most of stm32 series.
It is sometime empty or contains includes to flash_registers.h,
which is included directly with direct reference in flash driver.
soc_register.h is also included in stm32 clock drivers, but this
driver do not use direct reference to any register anymore.
Clean up these files.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
tests/drivers/i2c/i2c_api wants to have CONFIG_I2C_0_NAME defined.
Add it to dts_fixup.h as was done for Watchdog and & timer.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
This adds support for the basic timer counter (TC) found on SAM0
series parts. This driver only supports running the counter
in 32 bit wide mode. Since this mode explicitly slaves the odd
counters to the even ones, only instances of the even ones are
defined.
Tested with tests/drivers/counter/counter_basic_api on SAMD21.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
Define pinmux base addresses from gpio bases. Pinmux
and gpio functionality are located in the same PCR register
for each pin.
Introduce pinmux Kconfig switches for the SOC.
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
This commit enforces platform-specific initialization
for nRF SoC family. The specific platform initialization
hook is invoked directly after reset and calls the nRFx
SystemInit() function.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
If the QMSI is not configured in (in the west manifest) we get kconfig
whitelisting errors because the type is declared within the module
itself.
Change default to def_bool to set the type.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add support for the Low Power Inter-Integrated Circuit (LPI2C)
controllers found in the NXP Kinetis KE1xF SoC series.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add option for enabling the Code Cache present on the NXP Kinetis
KE1xF SoC series and enable it by default.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The Apollo Lake devicetree is augmented with its 8 I2C interfaces.
The default number of dynamic IRQ stubs is increased to deal with
these new interfaces having IRQ vector detection at runtime.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
The legacy PCI support in the DesignWare I2C driver is replaced with
the new PCIe support. The Intel Quark X1000 SoC and the galileo board
configurations are updated accordingly.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This needs to be pushed down to the SoC level, as it's an Apollo Lake
feature, not a feature of the UpSquared. Remove the Apollo Lake
references to the PCI devices because these will not be used when I2C
support is restored.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Allows snippets to be placed in different locations:
- The noinit, rwdata and rodata output sections
- Two different locations for placing custom output sections,
one location for RAM and another for all other sections.
Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
Unlike Cortex-M3 and Cortex-M4, in Cortex-M7 the number of
MPU regions may vary based on the implementation. This commit
adds a DTS node for the ARM MPU peripheral in the device tree
of Cortex-M7 SoCs and updates the fixup files, so we may extract
the number of MPU regions at build time. SoCs:
- nxp_rt
- same70
- stm32f7
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds a DTS node for the ARM MPU peripheral in the
device tree of ARMv8-M SoCs (for the secure and the non-secure
DTS descriptions) and updates the fixup files. SoCs:
- nrf9160
- musca_a
- musca_b1
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
In kernel_arch_init() we initialize the ARM core (interrupt
setup, fault init, etc.) so we can also move z_clearfaults()
in the same function and skip invoking it in the SoC init
functions.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Sample walk through:
1. CPU 0 will wake up CPU 1 after initialization
2. CPU 1 will send to CPU 0 an interrupt over MHU0
3. CPU 0 return the same to CPU 1 when received MHU0 interrupt
4. Test done when CPU 1 received MHU0 interrupt
The wake up second core and private core ID are soc specific.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
Add LiteX with softcore CPU VexRiscV SoC definitions and default
configurations.
Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
The CONFIG_CLOCK_CONTROL and CONFIG_NRF_RTC_TIMER were
unconditionally selected when enabling any nRF SoC. But since
timers can be disabled in the kernel, depend instead on
CONFIG_SYS_CLOCK_EXISTS, which is only defined when kernel
timer support is included.
Note that ideally we would enable CONFIG_NRF_RTC_TIMER only, and
that would select CONFIG_CLOCK_CONTROL (on which the RTC timer
depends) but there is a circular Kconfig dependency that prevents
us from doing so.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Add support for NXP MCUX LPUART devices with separate IRQ lines for
transmit and receive status interrupts (e.g. the Kinetis KE1xF SoC
series).
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
