gpio_pin_interrupt_configure asserts that one of GPIO_INT_ENABLE or
_DISABLE is specified by the caller, and also that GPIO_INT_EDGE is
requested if both states (GPIO_INT_TRIG_BOTH) should interrupt. This
change corrects the misuses in it8xxx2 drivers that cause assertion
failures.
When assertions are disabled the existing code works correctly because
the it8xxx2 GPIO driver assumes that a pin interrupt should be enabled
if _DISABLE is not requested, and the driver only supports edge
triggers but assumes the absence of GPIO_INT_MODE_LEVEL indicates
an edge trigger was requested.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I1aaee190ec4cf063f36e25c0c293a91d280e71bb
On 32bit compiler the BIT_MASK(32) generate a warning,
after discussion on #42226 and #42163, advise was to use
BIT64_MASK instead.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
These definitions are required to be able to use GICv3
interrupts controller on an ARMv8 AArch32 processor.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
When using DMA to transfer over the spi, the spi_stm32_cs_control
is done after enabling the SPI. The same sequence applies
in the transceive_dma function as in transceive function
Signed-off-by: Francois Ramu <francois.ramu@st.com>
I2C clock and I2C gpio could be on same gpio group.
Remove assertion that required them to be on different
group.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Reserve the upper 8 bits of gpio_dt_flags_t for SoC specific flags and
move the non-standard, hardware-specific GPIO devicetree flags (IO
voltage level, drive strength, debounce filter) from the generic
dt-bindings/gpio/gpio.h header to SoC specific dt-bindings headers.
Some of the SoC specific dt-bindings flags take up more bits than
necessary in order to retain backwards compatibility with the deprecated
GPIO flags. The width of these fields can be reduced/optimized once the
deprecated flags are removed.
Remove hardcoded use of GPIO_INT_DEBOUNCE in GPIO client drivers. This
flag can now be set in the devicetree for boards/SoCs with debounce
filter support. The SoC specific debounce flags have had the _INT part
of their name removed since these flag must be passed to
gpio_pin_configure(), not gpio_pin_interrupt_configure().
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The function eth_stm32_hal_set_config() located in
drivers/ethernet/eth_stm32_hal.c always returns -ENOTSUP,
even if everything is fine. This commit fixes the return statement
so that the real result (ret) will be returned.
Signed-off-by: Bernd Weiberg <bernd.weiberg@siemens.com>
Set up a c2_reset procedure in order to allow sequential
open/close/open calls and keep c2_reset done at init (required
for flash access).
Move reinit out of the reset procedure, so flash could be
accessed after bt_disable().
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Handle eSPI periperal channel error to avoid continous interrupt
beyond the bus error.
Whenever an eSPI access causes an internal bus error,
PC_BUS_ERROR bit is set, it remains set until cleared by written
with an 1.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Moves the nios2 msgdma driver device config struct to the device data
struct for mutable data. The config struct is expected to be const.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Moves the nios2 msgdma driver device config struct to the device data
struct for mutable data. The config struct is expected to be const.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
According to Kconfig guidelines, boolean prompts must not start with
"Enable...". The following command has been used to automate the changes
in this patch:
sed -i "s/bool \"[Ee]nables\? \(\w\)/bool \"\U\1/g" **/Kconfig*
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Ignore the flag instead of rejecting it with -ENOTSUP, as this is what
the GPIO API expects from drivers that do not support debouncing.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the I2C drivers that handle
the nRF TWI and TWIM peripherals. Update code of the drivers and
related devicetree bindings.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the SPI drivers that handle
the nRF SPI, SPIM, and SPIS peripherals. Update code of the drivers
and related devicetree bindings.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
- clean up registration of the drivers with the logging subsystem
- use consistent naming of local variables accessing configuration
and runtime data of driver instances, for easier code maintenance
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for configuring pins of the following nRF peripherals:
SPI, SPIM, SPIS, TWI, and TWIM.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add build assertions that will ensure that every peripheral for
which a driver instance is created has some pins assigned to it.
Neither pinctrl-0 nor *-pin properties can be currently marked as
required in devicetree, so these assertions will help users avoid
invalid configurations where it could be hard to figure out why
the UART is not working.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
fix incorrect gpio driver struct used in driver data.
This should not have caused any issue as currently
sizeof(gpio_driver_data) == sizeof(gpio_driver_config).
Signed-off-by: Simon Frank <simon.frank@lohmega.com>
This commit adds a USB Type-C Port Controller Driver for
the STM32 USB Type-C / USB Power Delivery (UCPD) peripheral
Signed-off-by: Sam Hurst <sbh1187@gmail.com>
by default, a global trigger thread was enabled in kconfig but
the thread priority and stack size depended on a local thread
being enabled.
the local thread option was never used anywhere so it is removed.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@escolifesciences.com>
Indirect ISR automatically calls power management functions, which GPT
timer direct ISR was not calling. Calling these functions means that the
kernel will recognize that it is exiting low power mode when the GPT
timer interrupt fires that wakes the SOC up, and will call
pm_power_state_exit_post_ops, which can in turn raise the clock
frequencies and voltage of the SOC as early as possible.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
System entering sleep state before uart tx is complete can result in
characters being dropped from the transmission. Add pm constraint
setting to the lpuart driver to prevent character drops
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
1. Check I2C Clock and Data is high through GPIO driver instead
of the I2C bitbang registers
2. i2c_xec_poll_write() and i2c_xec_poll_read() will poll to
check I2C clock and data lines are high before initiating the
transaction. The polling will be every 25us for a cumulative
max of 2.5ms
3. wait_completion() will not call recover_from_error() to reset
the controller. Instead will poll for 10ms for the PIN bit to
clear before returning error.
4. wait_completion() will send STOP if the 9th bit is NACK
5. If any errors with current transaction:
(a) Set error_seen flag.
(b) In the next transaction do the recovery process (reset the
i2c controller) if the clk and data lines are high.
Note: error_seen flag is set for Address NACK with Repeated
Start as well.
6. If timeout error occurs in wait_completion():
(a) Set timeout_seen flag;
(b) Wait till the slave will release the clock.
(c) Once slave releases clock send STOP on the bus. If the
timeout occurred while master read, read the I2C DATA register
for the hardware to proceed.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
spi_dt_spec structure initialization should not be done
in the runtime during spi bus initialization because it
causes kernel panic.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
The RTC user channel count is increased contitionally to 2 when
nrf_802154 radio driver is enabled.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
The response of a KTCPSND has two phases. According to documentation by
wireless the timeout is 60 seconds. The fix respects the timeout on the
second phase, too (waiting for OK or errors from modem). Previously only
the first phase used 60 seconds and the second phase used 5 seconds.
Without this fix the hl7800 will lock the tcp stack for the current
socket indefinitely if another socket operation is performed before the
response from the modem is received.
Additionally all timeouts are adjusted to be at least one second longer
as the documented timeout from wireless. This avoids races between the
hl7800 and the driver.
Signed-off-by: Rene Bredlau <git@unrelated.de>
Shims for nrfx drivers should only connect the related IRQ handlers,
they should not enable the IRQs, as this could lead to a situation
where the interrupt handler is called before the driver had a chance
to properly initialize the peripheral and install the provided event
handler. nrfx drivers will enable the interrupts appropriately on
their own by calling the NRFX_IRQ_ENABLE macro which is implemented
in nrfx_glue.h as a call to irq_enable().
This commit fixes the above issue spotted in the following shims:
- dmic_nrfx_pdm
- clock_control_nrf
- i2s_nrfx
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Instead of reading registers query the info on sysclock configuration
from existing configuration symbols.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Rework clock start up functions in order to allow configuration
and enabling of individual clocks.
This way, each clock defined with a "okay" status will be enabled
even if not part of the sysclock clock tree.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add STM32_FOO_ENABLED and STM32_FOO_FREQ to STM32 fixed clocks:
HSI, HSE, MSI(S), CSI, LSI, LSE..
Replace STM32_LSE_CLOCK by STM32_LSE_FREQ and when possible
replace by new STM32_LSE_ENABLED when making sense.
Fix STM32_PLL3_FOO_ENABLE to STM32_PLL3_FOO_ENABLED
Additionally, add STM32_PLL_FOO_ENABLED definitions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
PLL3 setting should also be protected CFG_HW_RCC_SEMID.
Move semaphore unlock after we're done with PLL3.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
