drivers: serial: fix typos
Typos were found with codespell utility. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
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4828fa0649
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1155d4679b
6 changed files with 15 additions and 15 deletions
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@ -73,7 +73,7 @@ static int uart_imx_init(const struct device *dev)
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UART_Init(uart, &initConfig);
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/* Set UART build-in hardware FIFO Watermark. */
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/* Set UART built-in hardware FIFO Watermark. */
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UART_SetTxFifoWatermark(uart, 2);
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UART_SetRxFifoWatermark(uart, 1);
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@ -165,7 +165,7 @@ struct lpc11u6x_uartx_regs {
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volatile uint32_t brg; /* Baud rate generator */
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volatile const uint32_t int_stat; /* Interrupt status */
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volatile uint32_t osr; /* Oversample selection */
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volatile uint32_t addr; /* Address regiser*/
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volatile uint32_t addr; /* Address register*/
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};
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struct lpc11u6x_uartx_config {
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@ -195,7 +195,7 @@ struct lpc11u6x_uartx_data {
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/* Since UART1 and UART4 share the same IRQ (as well as UART2 and UART3),
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* we need to give the ISR a way to know all the devices that should be
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* notified when said IRQ is raied
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* notified when said IRQ is raised
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*/
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struct lpc11u6x_uartx_shared_irq {
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const struct device *devices[LPC11U6X_UARTX_DEVICE_PER_IRQ];
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@ -91,8 +91,8 @@ static void mcux_lpuart_poll_out(const struct device *dev, unsigned char c)
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#ifdef CONFIG_PM
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/*
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* We must keep the part from entering lower power mode until the
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* tranmission completes. Set the power constraint, and enable
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* the tranmission complete interrupt so we know when tranmission is
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* transmission completes. Set the power constraint, and enable
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* the transmission complete interrupt so we know when transmission is
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* completed.
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*/
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if (!data->tx_poll_stream_on && !data->tx_int_stream_on) {
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@ -1077,7 +1077,7 @@ static void rx_timeout(struct k_timer *timer)
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}
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/* Check for current buffer being full.
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* if the UART receives characters before the the ENDRX is handled
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* if the UART receives characters before the ENDRX is handled
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* and the 'next' buffer is set up, then the SHORT between ENDRX and
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* STARTRX will mean that data will be going into to the 'next' buffer
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* until the ENDRX event gets a chance to be handled.
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@ -1102,7 +1102,7 @@ static void rx_timeout(struct k_timer *timer)
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data->async->rx_timeout_slab;
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}
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/* If theres nothing left to report until the buffers are
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/* If there's nothing left to report until the buffers are
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* switched then the timer can be stopped
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*/
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if (clipped) {
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@ -79,7 +79,7 @@ struct pl011_data {
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/* PL011 Receive status register / error clear register */
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#define PL011_RSR_ECR_FE BIT(0) /* framing error */
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#define PL011_RSR_ECR_PE BIT(1) /* parity erorr */
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#define PL011_RSR_ECR_PE BIT(1) /* parity error */
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#define PL011_RSR_ECR_BE BIT(2) /* break error */
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#define PL011_RSR_ECR_OE BIT(3) /* overrun error */
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@ -108,7 +108,7 @@ struct pl011_data {
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/* PL011 Control Register */
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#define PL011_CR_UARTEN BIT(0) /* enable uart operations */
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#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */
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#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */
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#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */
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#define PL011_CR_LBE BIT(7) /* loop back enable */
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#define PL011_CR_TXE BIT(8) /* transmit enable */
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@ -134,10 +134,10 @@ struct pl011_data {
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#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */
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#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */
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#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt mask */
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#define PL011_IMSC_FEIM BIT(7) /* framine error interrupt mask */
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#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt mask */
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#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask */
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#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask */
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#define PL011_IMSC_OEIM BIT(10) /* overrun error interrutpt mask */
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#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt mask */
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#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \
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PL011_IMSC_PEIM | PL011_IMSC_BEIM | \
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@ -967,14 +967,14 @@ static void uart_stm32_isr(const struct device *dev)
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LL_USART_IsActiveFlag_TC(config->usart)) {
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if (data->tx_poll_stream_on) {
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/* A poll stream transmition just completed,
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/* A poll stream transmission just completed,
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* allow system to suspend
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*/
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LL_USART_DisableIT_TC(config->usart);
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data->tx_poll_stream_on = false;
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uart_stm32_pm_constraint_release(dev);
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}
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/* Stream transmition was either async or IRQ based,
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/* Stream transmission was either async or IRQ based,
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* constraint will be released at the same time TC IT
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* is disabled
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*/
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@ -1103,7 +1103,7 @@ static int uart_stm32_async_rx_disable(const struct device *dev)
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data->rx_next_buffer = NULL;
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data->rx_next_buffer_len = 0;
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/* When async rx is disabled, enable interruptable instance of uart to function normally*/
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/* When async rx is disabled, enable interruptible instance of uart to function normally */
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LL_USART_EnableIT_RXNE(config->usart);
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LOG_DBG("rx: disabled");
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@ -1142,7 +1142,7 @@ static void uart_stm32_dma_replace_buffer(const struct device *dev)
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const struct uart_stm32_config *config = dev->config;
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struct uart_stm32_data *data = dev->data;
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/* Replace the buffer and relod the DMA */
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/* Replace the buffer and reload the DMA */
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LOG_DBG("Replacing RX buffer: %d", data->rx_next_buffer_len);
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/* reload DMA */
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