Some specific F1 variants don't handle flash latency.
Put flash latency dealing code under dedicated switch.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
According to board documentation: "By default System
clock is driven by the MSI clock at 48MHz."
This is in line with rcc node dts configuration:
&rcc {
[...]
clocks = <&clk_msi>;
[...]
};
Though pll node is currently enabled, which is not in line with
current dts clocks description scheme and results to compilation
issue in clock_control driver.
Remove pll node configuration to fix this.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add new scheme clock bindings for 'common' series:
- stm32f1_clock.h > compatible with f0/f1/f3 series
- stm32f4_clock.h > compatible with f2/f4/f7 series
- stm32l0_clock.h > compatible with l0 series
- stm32l1_clock.h > compatible with l1 series
- stm32l4_clock.h > compatible with g4/l4/l5/wb series
- stm32wl_clock.h > compatible with wl series
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Review code style in set_up_fixed_clock_sources() for better
readability.
Use of 'if (IS_ENABLED(STM32_MSI_ENABLED))' inside '#if STM32_MSI_ENABLED'
is redundant but intentional as it is in line with remaining part of the
function (HSE/HSI cases).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
On some parts, it could be required to use steps before applying
highest frequencies.
This was previously done as part of LL_PLL_ConfigSystemClock_FOO
utility functions which are no more used.
Use device tree to mention when this is required and implement it
in stm32_clock_control_init().
Additionally, fix the calls tp LL_RCC_SetAHBPrescaler, which require
use of ahb_prescaler helper.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Introduce a set_up_pll configuration function and make PLL configuration
an elementary step of the whole system clock configuration.
To implement this new, function make use of the existing series specific
files which allows series specific configuration when required.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Group fixed clocks inits in a unique set_up function.
Each clock is initialized depending on its dts status.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Simplify and clean up driver code using STM32 clocks DT based macros.
Added STM32_FLASH_PRESCALER macro for this purpose.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Factorize setting of frequency for busses.
Additionally, factorize SysCoreClock update.
The operations are now done twice in case of PLL since they are part
of LL utils PLL configuration function, but they are removed in next
commits.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Take advantage of previous work to configure PLL and remove
usage of LL_PLL1_ConfigSystemClock_FOO utils functions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Now that fixed clocks are enabled in a single function, a
bunch of functions could now be removed.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move fixed clocks initialization to a single function.
Benefit is they could now be enabled independently of the
main clock configuration based on dts status and then be
used by peripherals even is not part of the main clock tree.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Flash latency setting could be factorized in a single location,
rather than split in each clock setting function.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move prescaler settings to the clock_control_init function.
At this step they will be set up twice in PLL case, this will
be fixed in a next step.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Introduce a new scheme to define clock bingings on u5.
In a next steps, this new scheme will allow to provide u5 specific
alternate and complementary device clocks.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
On some series (H7, U5), it is possible define clock configuration
with disabled PLL outputs.
In that case, it is legit that matching pll property is not available.
Define corresponding STM32_PLLX_Y_DIVISOR macros using DT_PROP_OR
to avoid build issues in case prop is not available.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Set bus binding values using registers offset values.
As a consequence update driver to take this into account
in clock_on and clock_off functions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This new binding allows to work on providing stm32h7 specific
alternate and complementary device clocks.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
If a Zephyr binary is booted on the Zynq-7000 not via JTAG download,
but via u-boot's ELF boot function instead, Zephyr will have to revert
certain changes made by u-boot in order to boot properly:
- clear the ICache/DCache enable, branch prediction enable and
strict alignment enforcement enable bits in the SCTLR register.
By default, u-boot will also set up the MMU prior to Zephyr
doing so as well, this can be avoided by changing the u-boot
build configuration. Therefore, the MMU enable bit is not changed
at this point.
- set the VBAR register to 0. U-boot moves the interrupt vector
table to a non-standard location using the VBAR register (no
change is made by u-boot for SCTLR.V, only VBAR is changed
to a non-zero memory location).
Without these changes, Zephyr will crash upon the first context
switch at latest, when SVC is invoked and u-boot's vector table
is used rather than the vectors copied to address zero by Zephyr.
In order to perform these changes before coming anwhere near the
MMU / device driver / kernel initialization stages or even the
first context switch, the z_arm_platform_init hook is used, which
is now enabled for the Zynq via the Kconfig.defconfig file.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Add a check to avoid invalidating the cache when the latter is disabled.
Indeed, doing so can lead to a bus fault.
Signed-off-by: Thomas Altenbach <taltenbach@witekio.com>
Add a guide section on how to use semihosting with an example code
section on opening a file to read data from it.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
With SEMIHOST_CONSOLE now being supported on all ARM, ARM64 and RISC-V
architectures, extend the testing to cover these cases.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Update the semihost_console implementation to use the semihost API
instead of manually constructing the supervisor calls.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add an API that utilizes the ARM semihosting mechanism to interact with
the host system when a device is being emulated or run under a debugger.
RISCV is implemented in terms of the ARM implementation, and therefore
the ARM definitions cross enough architectures to be defined 'common'.
Functionality is exposed as a separate API instead of syscall
implementations (`_lseek`, `_open`, etc) due to various quirks with
the ARM mechanisms that means function arguments are not standard.
For more information see:
https://developer.arm.com/documentation/dui0471/m/what-is-semihosting-
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
impl
Control the usage of semihosting with a dedicated symbol, instead of
implying semihosting from the usage of `SEMIHOST_CONSOLE`. This allows
semihosting to be used without the semihost console.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Move where the default value of `CONFIG_UART_CONSOLE` is set from
`Kconfig.defconfig` to `qemu_cortex_a9_defconfig`. This conforms to
the standard location and lets the default be overridden by
applications.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Nucleo F030R8 has some board revision.
Add revision configuration to support C-01 board version.
This commit add revision '1' and '2'.
Defaultly uses revision '2' that is for C-02 (or later).
This is uses existing configuration.
Set board name in west command option as 'nucleo_f030r8@1'
to use C-01 board.
C-01 has no supply clock to HSE, Must use HSI for SYSCLK.
nucleo_f030r8 clock configuration is
8MHz (HSE freq) / 1 (PLL prediv) * 6 (PLL mul) = 48MHz (SYSCLK)
In case of using HSI (added as nucleo_f030r8_ver_c01),
8MHz (HSI freq) / 2 (PLL prediv) * 12 (PLL mul) = 48MHz (SYSCLK)
PLL prediv is must take 2 if using HSI.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Do not soft-reset device when changing timing parameters as the
soft-reset will discard the configured CAN controller mode.
Fixes: #44837
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
gpio_dev is being deprecated in favor of gpio_dt_spec gpio member
so let's use it instead of that one.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
Rename CONFIG_CAN_STM32_CLOCK_DIVISOR to
CONFIG_CAN_STM32FD_CLOCK_DIVISOR to match driver Kconfig name.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add support for selecting the CAN clock source. Change previously
hardcoded value of PCLK1 to HSE.
Fixes: #44985
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Print the CAN core clock frequency along with the device name to aid in
debugging CAN timing test case errors.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Removes an unnecessary schedule lock/unlock pair from k_mutex_unlock().
Rationale: Given that only the current thread (which would also be the
mutex owner) will be able to modify the mutex object AND that a
recursive unlock ought never trigger any reschedule (as it does not
touch the pend queue), then performing a schedule lock is not needed
prior to testing for a recursive unlock.
Furthermore, even if it is not a recursive unlock, then a schedule lock
is superfluous as the existing spinlock provides sufficient protection.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Add a new gitlint user rule to block unwanted commit tags, and set it up
to block Gerrit Change-Id tags.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
