drivers: pinctrl: nrf: Add support for SPI and TWI peripherals
Add support for configuring pins of the following nRF peripherals: SPI, SPIM, SPIS, TWI, and TWIM. Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
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2 changed files with 89 additions and 0 deletions
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@ -33,6 +33,26 @@ BUILD_ASSERT(((NRF_DRIVE_S0S1 == NRF_GPIO_PIN_S0S1) &&
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#define NRF_PSEL_UART(reg, line) ((NRF_UARTE_Type *)reg)->PSEL.line
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#endif
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#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spi)
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#define NRF_PSEL_SPIM(reg, line) ((NRF_SPI_Type *)reg)->PSEL##line
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#elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spim)
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#define NRF_PSEL_SPIM(reg, line) ((NRF_SPIM_Type *)reg)->PSEL.line
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#endif
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#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spis)
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#if defined(NRF51)
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#define NRF_PSEL_SPIS(reg, line) ((NRF_SPIS_Type *)reg)->PSEL##line
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#else
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#define NRF_PSEL_SPIS(reg, line) ((NRF_SPIS_Type *)reg)->PSEL.line
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#endif
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spis) */
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#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_twi)
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#define NRF_PSEL_TWIM(reg, line) ((NRF_TWI_Type *)reg)->PSEL##line
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#elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_twim)
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#define NRF_PSEL_TWIM(reg, line) ((NRF_TWIM_Type *)reg)->PSEL.line
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#endif
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/**
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* @brief Configure pin settings.
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*
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@ -83,6 +103,57 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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NRF_GPIO_PIN_INPUT_CONNECT);
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break;
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#endif /* defined(NRF_PSEL_UART) */
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#if defined(NRF_PSEL_SPIM)
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case NRF_FUN_SPIM_SCK:
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NRF_PSEL_SPIM(reg, SCK) = NRF_GET_PIN(pins[i]);
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nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
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NRF_GPIO_PIN_INPUT_CONNECT);
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break;
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case NRF_FUN_SPIM_MOSI:
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NRF_PSEL_SPIM(reg, MOSI) = NRF_GET_PIN(pins[i]);
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nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
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NRF_GPIO_PIN_INPUT_DISCONNECT);
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break;
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case NRF_FUN_SPIM_MISO:
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NRF_PSEL_SPIM(reg, MISO) = NRF_GET_PIN(pins[i]);
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nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
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NRF_GPIO_PIN_INPUT_CONNECT);
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break;
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#endif /* defined(NRF_PSEL_SPIM) */
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#if defined(NRF_PSEL_SPIS)
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case NRF_FUN_SPIS_SCK:
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NRF_PSEL_SPIS(reg, SCK) = NRF_GET_PIN(pins[i]);
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nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
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NRF_GPIO_PIN_INPUT_CONNECT);
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break;
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case NRF_FUN_SPIS_MOSI:
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NRF_PSEL_SPIS(reg, MOSI) = NRF_GET_PIN(pins[i]);
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nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
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NRF_GPIO_PIN_INPUT_CONNECT);
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break;
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case NRF_FUN_SPIS_MISO:
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NRF_PSEL_SPIS(reg, MISO) = NRF_GET_PIN(pins[i]);
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nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
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NRF_GPIO_PIN_INPUT_DISCONNECT);
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break;
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case NRF_FUN_SPIS_CSN:
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NRF_PSEL_SPIS(reg, CSN) = NRF_GET_PIN(pins[i]);
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nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
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NRF_GPIO_PIN_INPUT_CONNECT);
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break;
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#endif /* defined(NRF_PSEL_SPIS) */
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#if defined(NRF_PSEL_TWIM)
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case NRF_FUN_TWIM_SCL:
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NRF_PSEL_TWIM(reg, SCL) = NRF_GET_PIN(pins[i]);
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nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
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NRF_GPIO_PIN_INPUT_CONNECT);
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break;
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case NRF_FUN_TWIM_SDA:
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NRF_PSEL_TWIM(reg, SDA) = NRF_GET_PIN(pins[i]);
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nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
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NRF_GPIO_PIN_INPUT_CONNECT);
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break;
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#endif /* defined(NRF_PSEL_TWIM) */
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default:
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return -ENOTSUP;
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}
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@ -59,6 +59,24 @@
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#define NRF_FUN_UART_RTS 2U
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/** UART CTS */
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#define NRF_FUN_UART_CTS 3U
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/** SPI master SCK */
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#define NRF_FUN_SPIM_SCK 4U
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/** SPI master MOSI */
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#define NRF_FUN_SPIM_MOSI 5U
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/** SPI master MISO */
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#define NRF_FUN_SPIM_MISO 6U
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/** SPI slave SCK */
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#define NRF_FUN_SPIS_SCK 7U
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/** SPI slave MOSI */
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#define NRF_FUN_SPIS_MOSI 8U
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/** SPI slave MISO */
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#define NRF_FUN_SPIS_MISO 9U
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/** SPI slave CSN */
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#define NRF_FUN_SPIS_CSN 10U
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/** TWI master SCL */
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#define NRF_FUN_TWIM_SCL 11U
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/** TWI master SDA */
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#define NRF_FUN_TWIM_SDA 12U
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/** @} */
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