michaelh/zephyr
1
0
Fork 0
Code Releases Activity

drivers: pinctrl: nrf: Add support for SPI and TWI peripherals

Browse source 
Add support for configuring pins of the following nRF peripherals:
SPI, SPIM, SPIS, TWI, and TWIM.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit is contained in:
Andrzej Głąbek 2022-02-24 15:34:15 +01:00 • committed by Carles Cufí
commit fa22634880
2 changed files with 89 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

71
drivers/pinctrl/pinctrl_nrf.c
View file

@ -33,6 +33,26 @@ BUILD_ASSERT(((NRF_DRIVE_S0S1 == NRF_GPIO_PIN_S0S1) &&
#define NRF_PSEL_UART(reg, line) ((NRF_UARTE_Type *)reg)->PSEL.line
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spi)
#define NRF_PSEL_SPIM(reg, line) ((NRF_SPI_Type *)reg)->PSEL##line
#elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spim)
#define NRF_PSEL_SPIM(reg, line) ((NRF_SPIM_Type *)reg)->PSEL.line
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spis)
#if defined(NRF51)
#define NRF_PSEL_SPIS(reg, line) ((NRF_SPIS_Type *)reg)->PSEL##line
#else
#define NRF_PSEL_SPIS(reg, line) ((NRF_SPIS_Type *)reg)->PSEL.line
#endif
#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spis) */
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_twi)
#define NRF_PSEL_TWIM(reg, line) ((NRF_TWI_Type *)reg)->PSEL##line
#elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_twim)
#define NRF_PSEL_TWIM(reg, line) ((NRF_TWIM_Type *)reg)->PSEL.line
#endif
/**
* @brief Configure pin settings.
*
@ -83,6 +103,57 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
NRF_GPIO_PIN_INPUT_CONNECT);
break;
#endif /* defined(NRF_PSEL_UART) */
#if defined(NRF_PSEL_SPIM)
case NRF_FUN_SPIM_SCK:
NRF_PSEL_SPIM(reg, SCK) = NRF_GET_PIN(pins[i]);
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
NRF_GPIO_PIN_INPUT_CONNECT);
break;
case NRF_FUN_SPIM_MOSI:
NRF_PSEL_SPIM(reg, MOSI) = NRF_GET_PIN(pins[i]);
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
NRF_GPIO_PIN_INPUT_DISCONNECT);
break;
case NRF_FUN_SPIM_MISO:
NRF_PSEL_SPIM(reg, MISO) = NRF_GET_PIN(pins[i]);
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
NRF_GPIO_PIN_INPUT_CONNECT);
break;
#endif /* defined(NRF_PSEL_SPIM) */
#if defined(NRF_PSEL_SPIS)
case NRF_FUN_SPIS_SCK:
NRF_PSEL_SPIS(reg, SCK) = NRF_GET_PIN(pins[i]);
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
NRF_GPIO_PIN_INPUT_CONNECT);
break;
case NRF_FUN_SPIS_MOSI:
NRF_PSEL_SPIS(reg, MOSI) = NRF_GET_PIN(pins[i]);
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
NRF_GPIO_PIN_INPUT_CONNECT);
break;
case NRF_FUN_SPIS_MISO:
NRF_PSEL_SPIS(reg, MISO) = NRF_GET_PIN(pins[i]);
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
NRF_GPIO_PIN_INPUT_DISCONNECT);
break;
case NRF_FUN_SPIS_CSN:
NRF_PSEL_SPIS(reg, CSN) = NRF_GET_PIN(pins[i]);
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
NRF_GPIO_PIN_INPUT_CONNECT);
break;
#endif /* defined(NRF_PSEL_SPIS) */
#if defined(NRF_PSEL_TWIM)
case NRF_FUN_TWIM_SCL:
NRF_PSEL_TWIM(reg, SCL) = NRF_GET_PIN(pins[i]);
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
NRF_GPIO_PIN_INPUT_CONNECT);
break;
case NRF_FUN_TWIM_SDA:
NRF_PSEL_TWIM(reg, SDA) = NRF_GET_PIN(pins[i]);
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
NRF_GPIO_PIN_INPUT_CONNECT);
break;
#endif /* defined(NRF_PSEL_TWIM) */
default:
return -ENOTSUP;
}

18
include/dt-bindings/pinctrl/nrf-pinctrl.h
View file

@ -59,6 +59,24 @@
#define NRF_FUN_UART_RTS 2U
/** UART CTS */
#define NRF_FUN_UART_CTS 3U
/** SPI master SCK */
#define NRF_FUN_SPIM_SCK 4U
/** SPI master MOSI */
#define NRF_FUN_SPIM_MOSI 5U
/** SPI master MISO */
#define NRF_FUN_SPIM_MISO 6U
/** SPI slave SCK */
#define NRF_FUN_SPIS_SCK 7U
/** SPI slave MOSI */
#define NRF_FUN_SPIS_MOSI 8U
/** SPI slave MISO */
#define NRF_FUN_SPIS_MISO 9U
/** SPI slave CSN */
#define NRF_FUN_SPIS_CSN 10U
/** TWI master SCL */
#define NRF_FUN_TWIM_SCL 11U
/** TWI master SDA */
#define NRF_FUN_TWIM_SDA 12U
/** @} */