include/drivers/clock_control: stm32: Add XXX_ENABLED and XXX_FREQ
Add STM32_FOO_ENABLED and STM32_FOO_FREQ to STM32 fixed clocks: HSI, HSE, MSI(S), CSI, LSI, LSE.. Replace STM32_LSE_CLOCK by STM32_LSE_FREQ and when possible replace by new STM32_LSE_ENABLED when making sense. Fix STM32_PLL3_FOO_ENABLE to STM32_PLL3_FOO_ENABLED Additionally, add STM32_PLL_FOO_ENABLED definitions. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
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348070e4ea
commit
ceb8579854
7 changed files with 68 additions and 46 deletions
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@ -393,7 +393,7 @@ static void start_ble_rf(void)
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LL_RCC_ReleaseBackupDomainReset();
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}
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#if STM32_LSE_CLOCK
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#if STM32_LSE_ENABLED
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/* Select LSE clock */
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LL_RCC_LSE_Enable();
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while (!LL_RCC_LSE_IsReady()) {
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@ -452,7 +452,7 @@ int stm32_clock_control_init(const struct device *dev)
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#if STM32_MSI_PLL_MODE
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#ifndef STM32_LSE_CLOCK
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#ifndef STM32_LSE_ENABLED
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#error "MSI Hardware auto calibration requires LSE clock activation"
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#endif
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/* Enable MSI hardware auto calibration */
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@ -44,25 +44,13 @@
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/* This check should only be performed for the M7 core code */
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#ifdef CONFIG_CPU_CORTEX_M7
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/* Define primary oscillator frequencies */
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/* Suppress the cast to uint32_t which */
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/* prevents from compare with #if > operator*/
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/* original defines in stm32h7xx_hal_conf.h*/
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#define HSI_FREQ 64000000UL /* HSI_VALUE ((uint32_t)64000000) */
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/* HSE_VALUE overridden by the build system without C cast to uint*/
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/* Build system doesn't provide the UL type suffix for HSE_VALUE */
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/* Force HSE_FREQ to be cast to preprocessor UL to prevent overflow*/
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/* Only use these constants in preprocessor expressions */
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#define HSE_FREQ HSE_VALUE
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#define CSI_FREQ 4000000UL /* CSI_VALUE ((uint32_t)4000000) */
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/* Choose PLL SRC */
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#if defined(STM32_PLL_SRC_HSI)
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#define PLLSRC_FREQ ((HSI_FREQ)/(STM32_HSI_DIVISOR))
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#define PLLSRC_FREQ ((STM32_HSI_FREQ)/(STM32_HSI_DIVISOR))
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#elif defined(STM32_PLL_SRC_CSI)
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#define PLLSRC_FREQ CSI_FREQ
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#define PLLSRC_FREQ STM32_CSI_FREQ
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#elif defined(STM32_PLL_SRC_HSE)
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#define PLLSRC_FREQ HSE_FREQ
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#define PLLSRC_FREQ STM32_HSE_FREQ
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#else
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#define PLLSRC_FREQ 0
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#endif
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@ -82,11 +70,11 @@
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#if defined(STM32_SYSCLK_SRC_PLL)
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#define SYSCLKSRC_FREQ PLLP_VALUE
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#elif defined(STM32_SYSCLK_SRC_HSI)
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#define SYSCLKSRC_FREQ ((HSI_FREQ)/(STM32_HSI_DIVISOR))
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#define SYSCLKSRC_FREQ ((STM32_HSI_FREQ)/(STM32_HSI_DIVISOR))
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#elif defined(STM32_SYSCLK_SRC_CSI)
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#define SYSCLKSRC_FREQ CSI_FREQ
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#define SYSCLKSRC_FREQ STM32_CSI_FREQ
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#elif defined(STM32_SYSCLK_SRC_HSE)
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#define SYSCLKSRC_FREQ HSE_FREQ
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#define SYSCLKSRC_FREQ STM32_HSE_FREQ
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#endif
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/* ARM Sys CPU Clock before HPRE prescaler */
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@ -176,11 +164,11 @@ static inline uint32_t get_pllsrc_frequency(void)
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{
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switch (LL_RCC_PLL_GetSource()) {
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case LL_RCC_PLLSOURCE_HSI:
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return HSI_VALUE;
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return STM32_HSI_FREQ;
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case LL_RCC_PLLSOURCE_CSI:
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return CSI_VALUE;
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return STM32_CSI_FREQ;
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case LL_RCC_PLLSOURCE_HSE:
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return HSE_VALUE;
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return STM32_HSE_FREQ;
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case LL_RCC_PLLSOURCE_NONE:
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default:
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return 0;
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@ -213,13 +201,13 @@ static uint32_t get_hclk_frequency(void)
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/* Get the current system clock source */
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switch (LL_RCC_GetSysClkSource()) {
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case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:
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sysclk = HSI_VALUE/hsidiv;
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sysclk = STM32_HSI_FREQ/hsidiv;
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break;
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case LL_RCC_SYS_CLKSOURCE_STATUS_CSI:
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sysclk = CSI_VALUE;
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sysclk = STM32_CSI_FREQ;
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break;
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case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:
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sysclk = HSE_VALUE;
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sysclk = STM32_HSE_FREQ;
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break;
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case LL_RCC_SYS_CLKSOURCE_STATUS_PLL1:
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sysclk = PLLP_FREQ(get_pllsrc_frequency(),
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@ -516,7 +504,7 @@ static struct clock_control_driver_api stm32_clock_control_api = {
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__unused
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static int set_up_pll3(void)
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{
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#if defined(STM32_PLL3_ENABLE)
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#if defined(STM32_PLL3_ENABLED)
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int r;
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uint32_t vco_input_range;
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uint32_t vco_output_range;
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@ -537,17 +525,17 @@ static int set_up_pll3(void)
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LL_RCC_PLL3_SetVCOInputRange(vco_input_range);
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LL_RCC_PLL3_SetVCOOutputRange(vco_output_range);
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if (IS_ENABLED(STM32_PLL3_P_ENABLE)) {
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if (IS_ENABLED(STM32_PLL3_P_ENABLED)) {
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LL_RCC_PLL3P_Enable();
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LL_RCC_PLL3_SetP(STM32_PLL3_P_DIVISOR);
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}
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if (IS_ENABLED(STM32_PLL3_Q_ENABLE)) {
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if (IS_ENABLED(STM32_PLL3_Q_ENABLED)) {
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LL_RCC_PLL3Q_Enable();
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LL_RCC_PLL3_SetQ(STM32_PLL3_Q_DIVISOR);
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}
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if (IS_ENABLED(STM32_PLL3_R_ENABLE)) {
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if (IS_ENABLED(STM32_PLL3_R_ENABLED)) {
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LL_RCC_PLL3R_Enable();
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LL_RCC_PLL3_SetR(STM32_PLL3_R_DIVISOR);
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}
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@ -555,7 +543,7 @@ static int set_up_pll3(void)
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LL_RCC_PLL3_Enable();
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while (LL_RCC_PLL3_IsReady() != 1U) {
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}
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#endif /* STM32_PLL3_ENABLE */
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#endif /* STM32_PLL3_ENABLED */
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return 0;
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}
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@ -765,7 +753,7 @@ static int stm32_clock_control_init(const struct device *dev)
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optimize_regulator_voltage_scale(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
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if (IS_ENABLED(STM32_PLL3_ENABLE)) {
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if (IS_ENABLED(STM32_PLL3_ENABLED)) {
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int r = set_up_pll3();
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if (r < 0) {
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@ -51,7 +51,7 @@ void config_enable_default_clocks(void)
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/* Enable the power interface clock */
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);
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if (IS_ENABLED(STM32_LSE_CLOCK)) {
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if (IS_ENABLED(STM32_LSE_ENABLED)) {
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if (!LL_PWR_IsEnabledBkUpAccess()) {
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/* Enable write access to Backup domain */
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LL_PWR_EnableBkUpAccess();
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@ -257,7 +257,7 @@ static void set_up_clk_msis(void)
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LL_RCC_MSIS_SetRange(STM32_MSIS_RANGE << RCC_ICSCR1_MSISRANGE_Pos);
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if (IS_ENABLED(STM32_MSIS_PLL_MODE)) {
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BUILD_ASSERT(STM32_LSE_CLOCK,
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BUILD_ASSERT(STM32_LSE_ENABLED,
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"MSI Hardware auto calibration needs LSE clock activation");
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/* Enable MSI hardware auto calibration */
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LL_RCC_MSI_EnablePLLMode();
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@ -49,7 +49,7 @@ void config_enable_default_clocks(void)
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/* Enable the power interface clock */
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
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#if STM32_LSE_CLOCK
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#if STM32_LSE_ENABLED
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/* LSE belongs to the back-up domain, enable access.*/
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/* Set the DBP bit in the Power control register 1 (PWR_CR1) */
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@ -53,7 +53,7 @@ void config_enable_default_clocks(void)
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
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#endif
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#if STM32_LSE_CLOCK
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#if STM32_LSE_ENABLED
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/* LSE belongs to the back-up domain, enable access.*/
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#if defined(CONFIG_SOC_SERIES_STM32WBX)
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@ -69,22 +69,26 @@
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay)
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#define STM32_PLL_ENABLED 1
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#define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m)
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#define STM32_PLL_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul_n)
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#define STM32_PLL_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_p)
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#define STM32_PLL_P_DIVISOR DT_PROP(DT_NODELABEL(pll), div_p)
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#define STM32_PLL_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_q)
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#define STM32_PLL_Q_DIVISOR DT_PROP(DT_NODELABEL(pll), div_q)
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#define STM32_PLL_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_r)
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#define STM32_PLL_R_DIVISOR DT_PROP(DT_NODELABEL(pll), div_r)
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#endif
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7_pll_clock, okay)
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#define STM32_PLL3_ENABLE 1
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#define STM32_PLL3_ENABLED 1
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#define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m)
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#define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n)
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#define STM32_PLL3_P_ENABLE DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_p)
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#define STM32_PLL3_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_p)
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#define STM32_PLL3_P_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_p)
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#define STM32_PLL3_Q_ENABLE DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_q)
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#define STM32_PLL3_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_q)
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#define STM32_PLL3_Q_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_q)
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#define STM32_PLL3_R_ENABLE DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_r)
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#define STM32_PLL3_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_r)
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#define STM32_PLL3_R_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_r)
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#endif
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@ -129,34 +133,64 @@
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/** Fixed clocks related symbols */
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), fixed_clock, okay)
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#define STM32_LSE_CLOCK DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
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#define STM32_LSE_ENABLED 1
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#define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
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#else
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#define STM32_LSE_ENABLED 0
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#define STM32_LSE_FREQ 0
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#endif
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32l0_msi_clock, okay)
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#define STM32_MSI_ENABLED 1
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#define STM32_MSI_RANGE DT_PROP(DT_NODELABEL(clk_msi), msi_range)
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#endif
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay)
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#define STM32_MSI_ENABLED 1
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#define STM32_MSI_PLL_MODE DT_PROP(DT_NODELABEL(clk_msi), msi_pll_mode)
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#endif
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay)
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#define STM32_MSIS_ENABLED 1
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#define STM32_MSIS_RANGE DT_PROP(DT_NODELABEL(clk_msis), msi_range)
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#define STM32_MSIS_PLL_MODE DT_PROP(DT_NODELABEL(clk_msis), msi_pll_mode)
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#endif
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_csi), fixed_clock, okay)
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#define STM32_CSI_ENABLED 1
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#define STM32_CSI_FREQ DT_PROP(DT_NODELABEL(clk_csi), clock_frequency)
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#else
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#define STM32_CSI_FREQ 0
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#endif
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi), fixed_clock, okay)
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#define STM32_LSI_ENABLED 1
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#define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi), clock_frequency)
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#else
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#define STM32_LSI_FREQ 0
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#endif
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32h7_hsi_clock, okay)
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#define STM32_HSI_ENABLED 1
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#define STM32_HSI_DIVISOR DT_PROP(DT_NODELABEL(clk_hsi), hsi_div)
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#define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency)
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#else
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#define STM32_HSI_DIVISOR 1
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#define STM32_HSI_FREQ 0
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#endif
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32_hse_clock, okay)
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#define STM32_HSE_ENABLED 1
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#define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass)
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#endif
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wl_hse_clock, okay)
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#define STM32_HSE_TCXO DT_PROP(DT_NODELABEL(clk_hse), hse_tcxo)
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#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
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#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
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#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wl_hse_clock, okay)
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#define STM32_HSE_ENABLED 1
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#define STM32_HSE_TCXO DT_PROP(DT_NODELABEL(clk_hse), hse_tcxo)
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#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
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#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
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#else
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#define STM32_HSE_FREQ 0
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#endif
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/** Driver structure definition */
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