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include/drivers/clock_control: stm32: Add XXX_ENABLED and XXX_FREQ

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Add STM32_FOO_ENABLED and STM32_FOO_FREQ to STM32 fixed clocks:
HSI, HSE, MSI(S), CSI, LSI, LSE..

Replace STM32_LSE_CLOCK by STM32_LSE_FREQ and when possible
replace by new STM32_LSE_ENABLED when making sense.

Fix STM32_PLL3_FOO_ENABLE to STM32_PLL3_FOO_ENABLED

Additionally, add STM32_PLL_FOO_ENABLED definitions.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2022-01-18 11:44:01 +01:00 • committed by Carles Cufí
commit ceb8579854
7 changed files with 68 additions and 46 deletions
Download patch file Download diff file Expand all files Collapse all files

2
drivers/bluetooth/hci/ipm_stm32wb.c
View file

@ -393,7 +393,7 @@ static void start_ble_rf(void)
LL_RCC_ReleaseBackupDomainReset();
}
#if STM32_LSE_CLOCK
#if STM32_LSE_ENABLED
/* Select LSE clock */
LL_RCC_LSE_Enable();
while (!LL_RCC_LSE_IsReady()) {

2
drivers/clock_control/clock_stm32_ll_common.c
View file

@ -452,7 +452,7 @@ int stm32_clock_control_init(const struct device *dev)
#if STM32_MSI_PLL_MODE
#ifndef STM32_LSE_CLOCK
#ifndef STM32_LSE_ENABLED
#error "MSI Hardware auto calibration requires LSE clock activation"
#endif
/* Enable MSI hardware auto calibration */

48
drivers/clock_control/clock_stm32_ll_h7.c
View file

@ -44,25 +44,13 @@
/* This check should only be performed for the M7 core code */
#ifdef CONFIG_CPU_CORTEX_M7
/* Define primary oscillator frequencies */
/* Suppress the cast to uint32_t which */
/* prevents from compare with #if > operator*/
/* original defines in stm32h7xx_hal_conf.h*/
#define HSI_FREQ 64000000UL /* HSI_VALUE ((uint32_t)64000000) */
/* HSE_VALUE overridden by the build system without C cast to uint*/
/* Build system doesn't provide the UL type suffix for HSE_VALUE */
/* Force HSE_FREQ to be cast to preprocessor UL to prevent overflow*/
/* Only use these constants in preprocessor expressions */
#define HSE_FREQ HSE_VALUE
#define CSI_FREQ 4000000UL /* CSI_VALUE ((uint32_t)4000000) */
/* Choose PLL SRC */
#if defined(STM32_PLL_SRC_HSI)
#define PLLSRC_FREQ ((HSI_FREQ)/(STM32_HSI_DIVISOR))
#define PLLSRC_FREQ ((STM32_HSI_FREQ)/(STM32_HSI_DIVISOR))
#elif defined(STM32_PLL_SRC_CSI)
#define PLLSRC_FREQ CSI_FREQ
#define PLLSRC_FREQ STM32_CSI_FREQ
#elif defined(STM32_PLL_SRC_HSE)
#define PLLSRC_FREQ HSE_FREQ
#define PLLSRC_FREQ STM32_HSE_FREQ
#else
#define PLLSRC_FREQ 0
#endif
@ -82,11 +70,11 @@
#if defined(STM32_SYSCLK_SRC_PLL)
#define SYSCLKSRC_FREQ PLLP_VALUE
#elif defined(STM32_SYSCLK_SRC_HSI)
#define SYSCLKSRC_FREQ ((HSI_FREQ)/(STM32_HSI_DIVISOR))
#define SYSCLKSRC_FREQ ((STM32_HSI_FREQ)/(STM32_HSI_DIVISOR))
#elif defined(STM32_SYSCLK_SRC_CSI)
#define SYSCLKSRC_FREQ CSI_FREQ
#define SYSCLKSRC_FREQ STM32_CSI_FREQ
#elif defined(STM32_SYSCLK_SRC_HSE)
#define SYSCLKSRC_FREQ HSE_FREQ
#define SYSCLKSRC_FREQ STM32_HSE_FREQ
#endif
/* ARM Sys CPU Clock before HPRE prescaler */
@ -176,11 +164,11 @@ static inline uint32_t get_pllsrc_frequency(void)
{
switch (LL_RCC_PLL_GetSource()) {
case LL_RCC_PLLSOURCE_HSI:
return HSI_VALUE;
return STM32_HSI_FREQ;
case LL_RCC_PLLSOURCE_CSI:
return CSI_VALUE;
return STM32_CSI_FREQ;
case LL_RCC_PLLSOURCE_HSE:
return HSE_VALUE;
return STM32_HSE_FREQ;
case LL_RCC_PLLSOURCE_NONE:
default:
return 0;
@ -213,13 +201,13 @@ static uint32_t get_hclk_frequency(void)
/* Get the current system clock source */
switch (LL_RCC_GetSysClkSource()) {
case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:
sysclk = HSI_VALUE/hsidiv;
sysclk = STM32_HSI_FREQ/hsidiv;
break;
case LL_RCC_SYS_CLKSOURCE_STATUS_CSI:
sysclk = CSI_VALUE;
sysclk = STM32_CSI_FREQ;
break;
case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:
sysclk = HSE_VALUE;
sysclk = STM32_HSE_FREQ;
break;
case LL_RCC_SYS_CLKSOURCE_STATUS_PLL1:
sysclk = PLLP_FREQ(get_pllsrc_frequency(),
@ -516,7 +504,7 @@ static struct clock_control_driver_api stm32_clock_control_api = {
__unused
static int set_up_pll3(void)
{
#if defined(STM32_PLL3_ENABLE)
#if defined(STM32_PLL3_ENABLED)
int r;
uint32_t vco_input_range;
uint32_t vco_output_range;
@ -537,17 +525,17 @@ static int set_up_pll3(void)
LL_RCC_PLL3_SetVCOInputRange(vco_input_range);
LL_RCC_PLL3_SetVCOOutputRange(vco_output_range);
if (IS_ENABLED(STM32_PLL3_P_ENABLE)) {
if (IS_ENABLED(STM32_PLL3_P_ENABLED)) {
LL_RCC_PLL3P_Enable();
LL_RCC_PLL3_SetP(STM32_PLL3_P_DIVISOR);
}
if (IS_ENABLED(STM32_PLL3_Q_ENABLE)) {
if (IS_ENABLED(STM32_PLL3_Q_ENABLED)) {
LL_RCC_PLL3Q_Enable();
LL_RCC_PLL3_SetQ(STM32_PLL3_Q_DIVISOR);
}
if (IS_ENABLED(STM32_PLL3_R_ENABLE)) {
if (IS_ENABLED(STM32_PLL3_R_ENABLED)) {
LL_RCC_PLL3R_Enable();
LL_RCC_PLL3_SetR(STM32_PLL3_R_DIVISOR);
}
@ -555,7 +543,7 @@ static int set_up_pll3(void)
LL_RCC_PLL3_Enable();
while (LL_RCC_PLL3_IsReady() != 1U) {
}
#endif /* STM32_PLL3_ENABLE */
#endif /* STM32_PLL3_ENABLED */
return 0;
}
@ -765,7 +753,7 @@ static int stm32_clock_control_init(const struct device *dev)
optimize_regulator_voltage_scale(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
if (IS_ENABLED(STM32_PLL3_ENABLE)) {
if (IS_ENABLED(STM32_PLL3_ENABLED)) {
int r = set_up_pll3();
if (r < 0) {

4
drivers/clock_control/clock_stm32_ll_u5.c
View file

@ -51,7 +51,7 @@ void config_enable_default_clocks(void)
/* Enable the power interface clock */
LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);
if (IS_ENABLED(STM32_LSE_CLOCK)) {
if (IS_ENABLED(STM32_LSE_ENABLED)) {
if (!LL_PWR_IsEnabledBkUpAccess()) {
/* Enable write access to Backup domain */
LL_PWR_EnableBkUpAccess();
@ -257,7 +257,7 @@ static void set_up_clk_msis(void)
LL_RCC_MSIS_SetRange(STM32_MSIS_RANGE << RCC_ICSCR1_MSISRANGE_Pos);
if (IS_ENABLED(STM32_MSIS_PLL_MODE)) {
BUILD_ASSERT(STM32_LSE_CLOCK,
BUILD_ASSERT(STM32_LSE_ENABLED,
"MSI Hardware auto calibration needs LSE clock activation");
/* Enable MSI hardware auto calibration */
LL_RCC_MSI_EnablePLLMode();

2
drivers/clock_control/clock_stm32g4.c
View file

@ -49,7 +49,7 @@ void config_enable_default_clocks(void)
/* Enable the power interface clock */
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
#if STM32_LSE_CLOCK
#if STM32_LSE_ENABLED
/* LSE belongs to the back-up domain, enable access.*/
/* Set the DBP bit in the Power control register 1 (PWR_CR1) */

2
drivers/clock_control/clock_stm32l4_l5_wb_wl.c
View file

@ -53,7 +53,7 @@ void config_enable_default_clocks(void)
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
#endif
#if STM32_LSE_CLOCK
#if STM32_LSE_ENABLED
/* LSE belongs to the back-up domain, enable access.*/
#if defined(CONFIG_SOC_SERIES_STM32WBX)

54
include/drivers/clock_control/stm32_clock_control.h
View file

@ -69,22 +69,26 @@
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay)
#define STM32_PLL_ENABLED 1
#define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m)
#define STM32_PLL_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul_n)
#define STM32_PLL_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_p)
#define STM32_PLL_P_DIVISOR DT_PROP(DT_NODELABEL(pll), div_p)
#define STM32_PLL_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_q)
#define STM32_PLL_Q_DIVISOR DT_PROP(DT_NODELABEL(pll), div_q)
#define STM32_PLL_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_r)
#define STM32_PLL_R_DIVISOR DT_PROP(DT_NODELABEL(pll), div_r)
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7_pll_clock, okay)
#define STM32_PLL3_ENABLE 1
#define STM32_PLL3_ENABLED 1
#define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m)
#define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n)
#define STM32_PLL3_P_ENABLE DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_p)
#define STM32_PLL3_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_p)
#define STM32_PLL3_P_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_p)
#define STM32_PLL3_Q_ENABLE DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_q)
#define STM32_PLL3_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_q)
#define STM32_PLL3_Q_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_q)
#define STM32_PLL3_R_ENABLE DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_r)
#define STM32_PLL3_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_r)
#define STM32_PLL3_R_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_r)
#endif
@ -129,34 +133,64 @@
/** Fixed clocks related symbols */
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), fixed_clock, okay)
#define STM32_LSE_CLOCK DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
#define STM32_LSE_ENABLED 1
#define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
#else
#define STM32_LSE_ENABLED 0
#define STM32_LSE_FREQ 0
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32l0_msi_clock, okay)
#define STM32_MSI_ENABLED 1
#define STM32_MSI_RANGE DT_PROP(DT_NODELABEL(clk_msi), msi_range)
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay)
#define STM32_MSI_ENABLED 1
#define STM32_MSI_PLL_MODE DT_PROP(DT_NODELABEL(clk_msi), msi_pll_mode)
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay)
#define STM32_MSIS_ENABLED 1
#define STM32_MSIS_RANGE DT_PROP(DT_NODELABEL(clk_msis), msi_range)
#define STM32_MSIS_PLL_MODE DT_PROP(DT_NODELABEL(clk_msis), msi_pll_mode)
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_csi), fixed_clock, okay)
#define STM32_CSI_ENABLED 1
#define STM32_CSI_FREQ DT_PROP(DT_NODELABEL(clk_csi), clock_frequency)
#else
#define STM32_CSI_FREQ 0
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi), fixed_clock, okay)
#define STM32_LSI_ENABLED 1
#define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi), clock_frequency)
#else
#define STM32_LSI_FREQ 0
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32h7_hsi_clock, okay)
#define STM32_HSI_ENABLED 1
#define STM32_HSI_DIVISOR DT_PROP(DT_NODELABEL(clk_hsi), hsi_div)
#define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency)
#else
#define STM32_HSI_DIVISOR 1
#define STM32_HSI_FREQ 0
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32_hse_clock, okay)
#define STM32_HSE_ENABLED 1
#define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass)
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wl_hse_clock, okay)
#define STM32_HSE_TCXO DT_PROP(DT_NODELABEL(clk_hse), hse_tcxo)
#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wl_hse_clock, okay)
#define STM32_HSE_ENABLED 1
#define STM32_HSE_TCXO DT_PROP(DT_NODELABEL(clk_hse), hse_tcxo)
#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
#else
#define STM32_HSE_FREQ 0
#endif
/** Driver structure definition */