Simply to provide some consistencies on file naming under
arch/xtensa.
These are all internally used files and are not public.
So there is no need to provide a deprecation path for
them.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch enables DSP clock gating for ACE platforms. By default, clock
gating is blocked by the firmware in the hardware configuration. If
CONFIG_ADSP_IDLE_CLOCK_GATING is enabled, this prevent is not active and
clock can be gated when core is in idle state. WIth this option disabled
clock gating will only be enabled in hardware during power gating.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Reset cause reason was not initalized properly, making
hwinfo feature not to work as expected.
Fixes#65634
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Secondary dsp is idle and waiting for interrupt before it is totally
halted. The other active cores can trigger idc interrupt to this core,
this can wake it up and result to fw panic. Mask idc interrupt as timer
interrupt to prevent this case.
Signed-off-by: Rander Wang <rander.wang@intel.com>
Andy Ross re-implementation of MMU layer with some subtle changes,
like re-using existent macros, fix page table cache property when
direct mapping it in TLB.
From Andy's original commit message:
This is a reworked MMU layer, sitting cleanly below the page table
handling in the OS. Notable differences from the original work:
+ Significantly smaller code and simpler API (just three functions to
be called from the OS/userspace/ptable layer).
+ Big README-MMU document containing my learnings over the process, so
hopefully fewer people need to go through this in the future.
+ No TLB flushing needed. Clean separation of ASIDs, just requires
that the upper levels match the ASID to the L1 page table page
consistently.
+ Vector mapping is done with a 4k page and not a 4M page, leading to
much more flexibility with hardware memory layout. The original
scheme required that the 4M region containing vecbase be mapped
virtually to a location other than the hardware address, which makes
confusing linkage with call0 and difficult initialization
constraints where the exception vectors run at different addresses
before and after MMU setup (effectively forcing them to be PIC
code).
+ More provably correct initialization, all MMU changes happen in a
single asm block with no memory accesses which would generate a
refill.
Signed-off-by: Andy Ross <andyross@google.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Some workarounds were introduced for intel cavs2.5 platform bring up.
It is not general so move them to platform code.
Signed-off-by: Rander Wang <rander.wang@intel.com>
Cavs platforms starts from Apllolake to Raptorlake. Some of them need some
workaround for arch_cpu_idle so create a bespoken one. Each workaround is
configured by kconfig setting.
Signed-off-by: Rander Wang <rander.wang@intel.com>
The xtensa/nxp_adsp_imx8m linker script is missing
the necessary include statements for linker snippets.
So we need to add them.
This fixes compile warnings like: orphan section `.unstable_id'
from `modules/chre/lib..__modules__lib__chre__platform__zephyr.a
(version.cc.obj)' being placed in section `.unstable_id'.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Add _heap_sentry value to fix build errors for
newlib, like: "undefined reference to `_heap_sentry'"
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
When linking, in crtbegin.o for C++ exception support, we pull in
the .tm_clone_table section.
Update the linker scripts to handle this, otherwise we get a
"warning: orphan section `.tm_clone_table'".
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Remove platform.h since is no longer used for SOF.
Move memory.h to include folder and modify the linker
to reflect this.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
As the name suggests, this commit attempts to cleanup some
of the configurations for the i.MX8 series. This cleanup
consists of either relocating the configuration or removing
unnecessary configurations.
As a rule of thumb, SoC-specific configurations have been moved
to Kconfig.series. If the configuration is by default 'y' and
needs to be set to 'n' or it has a numeric value then it has
been moved to Kconfig.defconfig.series. Configurations that
are default 'n' and were also explicitly set to 'n' have been
removed. Also, enabling logging has been moved to the board
level to avoid having to force all boards based on the same
SoC to enable logging.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit attempts to clean the memory.h header by doing
the following changes:
1) Change the include guard to the standard
ZEPHYR_....
2) Remove unused macro definitions.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Since platform.h is a SOF-specific header that's no
longer used there's no point in keeping the include/soc directory.
As such, move memory.h to include/ and modify the linker script
to reflect this location change.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit attempts to split the generic i.MX8 SoC into its
QXP and QM variants. As things are now, the i.MX8 SoC doesn't
have any NXP HAL files to back it up. As a consequence, the
native Zephyr drivers cannot be used.
To solve this issue, the generic i.MX8 has been split into
i.MX8QXP and i.MX8QM, each of them having different NXP HAL
files.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Several paths are checked for existence before added as global Zephyr
include path.
The existence check was needed because some tooling emit warnings on
non-existing paths.
Only few SoCs are using those pre-defined paths, yet this code runs
for all SoCs. The principle originates back from Kbuild days, and with
CMake it's more common and generally more visible to let the CMake code
defining libraries to specify include paths.
Furthermore it appears that several SoC implementation following the
<soc-path>/include was unaware that the path would be automatically
added as include path, cause they contain lines like:
zephyr_library_include_directories(include)
Remove pre-defineds path except the `<SOC_PATH>` path, which is
guaranteed to exists.
This simplifies the CMake logic in the top-level Zephyr CMakeLists.txt
file.
This cleanup further prepares for future work where SoCs need not to
be organised under architectures which is important for multi-arch SoCs.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit updates all xtensa SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Save secondary dsp context when it is powered off in idle thread
and restore it when the secondary dsp is powered up. The algorithm
is aligned with ace platform.
Tested on a tgl platform.
Signed-off-by: Rander Wang <rander.wang@intel.com>
Fix a bug on cavs platform that secondary core is not powered off
by SET_DX ipc message sometimes. Secondary core is set into idle
state when switching to SOF_OFF state and then halted by primary
core. The interrupt is enabled before entring idle state, so the
secondary core may be woken up by interrupt and soc_cpus_active
is set to true before it is halted by hardware power gating. This
result to error when SOF check soc_cpus_active after the secondary
is halted.
This patch doesn't enable interrupt before idle entry to avoid above issue.
Signed-off-by: Rander Wang <rander.wang@intel.com>
Mark .noinit section as NOLOAD and move it
next to the other NOLOAD sections. This way
it is removed from a generated image that is
embedded in the rt595 app image.
Signed-off-by: Mike J. Chen <mjchen@google.com>
This adds a if CONFIG_SOC_FAMILY_NXP_ADSP guard in
Kconfig.defconfig for nxp_adsp. Or else all of its default
get applied everywhere. For example, qemu_xtensa fails
kernel.logging.message_capture tests because
CONFIG_TEST_LOGGING_DEFAULTS is disabled in
nxp_adsp/Kconfig.defconfig which should not have applied
to qemu_xtensa at all. So put a guard in there.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
In preparation for RT500 ADSP enablement, consolidate common Xtensa
configuration parameters in top level Kconfig.defconfig.
Signed-off-by: Dmitry Lukyantsev <dmitrylu@google.com>
ESP32 flash_mmap() function requires `_rodata_reserved_start` address
to be at the beginning of RODATA. This allows adding memory-mapped flash
areas.
Fixes#52764
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This patch contains small refactor of lpsram init function (defines
registers and adds new macro).
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This changes qemu_xtensa to use dc233c core instead of
sample_controller. The sample_controller uses a very
basic configuration which lacks features usually needed
in real world applications. Instead, use the dc233c core
as the base for qemu_xtensa so we can use QEMU to cover
more of our code path.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
If the channel was used for 16bit in the once, subsequent 32bit sample size
audio will be broken since the SCS bit remains set.
Example sequence with SOF:
normal audio playback with 16bit
ChainDMA audio playback with 16bit
normal audio playback with 16bit
The last playback results garbled audio.
Introduce intel_adsp_hda_set_sample_container_size() helper function
to handle the SCS bit and use it in the driver.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Commit 759e07bebe ("intel_adsp: move memory window setup to
PRE_KERNEL_1") moved memory window setup from EARLY to
PRE_KERNEL_1. Similar change must be done to boot_complete, or
otherwise boot-up sequence will not be completed correctly
on all platforms.
Suggested-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
This renames the board from qemu_xtensa_dc233c to
qemu_xtensa_mmu to better signal that it is for testing with
MMU on QEMU Xtensa. Also turn on testing by default to make
sure future changes will not break Xtensa MMU support.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The symbol _end is used to indicate the start of heap in
the common libc malloc code. On ACE, heap is in uncached
area. However, _end was in the cached area while end of
heap is in uncached area. This resulted in incorrect
calculation of heap size. So move _end into uncached
area so correct heap size can be calculated.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
PRE_KERNEL_1 is more suited for dealing with devices, so move out of
EARLY.
Verified on hardware and things seem to behave the same. Something was
changed since this was first introduced as this was not possible for
some reason.
Fixes#62627
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Flash segments require VMA to proper work. Executing from LMA
is not possible. Current implementation did not take into account
runtime iterable rom sections that any application could implement.
In the above cenario and as reported in the issue below, ESP32 won't run
when those ROM sections are created in application level.
This change make sure all flash segments are properly mapped
accordingly.
Fixes#61834
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Selecting Low Power clock has the same result as selecting High
Performance clock (now IPLL). Therefore, the LP clock will be removed
from the list of available clocks on ACE family platforms.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
