zephyr/soc/xtensa
Rander Wang efc3208189 soc: intel_adsp: cavs: mask idc interrupt before halting cpu
Secondary dsp is idle and waiting for interrupt before it is totally
halted. The other active cores can trigger idc interrupt to this core,
this can wake it up and result to fw panic. Mask idc interrupt as timer
interrupt to prevent this case.

Signed-off-by: Rander Wang <rander.wang@intel.com>
2023-11-22 14:57:07 +00:00
..
dc233c arch/xtensa: Add new MMU layer 2023-11-21 15:49:48 +01:00
espressif_esp32 cmake: xtensa: update xtensa SoC to use SOC_LINKER_SCRIPT variable 2023-11-03 11:01:23 +01:00
intel_adsp soc: intel_adsp: cavs: mask idc interrupt before halting cpu 2023-11-22 14:57:07 +00:00
nxp_adsp nxp_adsp: linker: Add snippets to linker script 2023-11-20 11:13:44 +01:00
sample_controller cmake: cleanup and simplify the standard include logic in Zephyr 2023-11-06 18:57:30 -05:00
CMakeLists.txt soc/xtensa/intel_adsp: Upstream updates 2020-10-21 06:38:53 -04:00