intel_s1000: various fixes for build errors
Lot of misdefined variables that went in undetected due to lack of CI on this board. Fix them and test build with new SDK. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
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0358d707b0
commit
aa14022c8a
5 changed files with 7 additions and 6 deletions
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@ -46,7 +46,7 @@ static int dw_ictl_initialize(struct device *dev)
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static void dw_ictl_isr(void *arg)
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{
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struct device *devt = (struct device *)arg;
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struct device *dev = (struct device *)arg;
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const struct dw_ictl_config *config = dev->config->config_info;
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volatile struct dw_ictl_registers * const regs =
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(struct dw_ictl_registers *)config->base_addr;
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@ -62,7 +62,7 @@ static void dw_ictl_isr(void *arg)
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static inline void dw_ictl_intr_enable(struct device *dev, unsigned int irq)
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{
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const struct dw_ictl_config *config = dev->config->config_info
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const struct dw_ictl_config *config = dev->config->config_info;
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volatile struct dw_ictl_registers * const regs =
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(struct dw_ictl_registers *)config->base_addr;
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@ -75,7 +75,7 @@ static inline void dw_ictl_intr_enable(struct device *dev, unsigned int irq)
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static inline void dw_ictl_intr_disable(struct device *dev, unsigned int irq)
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{
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const struct dw_ictl_config *config = dev->config->config_info
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const struct dw_ictl_config *config = dev->config->config_info;
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volatile struct dw_ictl_registers * const regs =
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(struct dw_ictl_registers *)config->base_addr;
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@ -126,7 +126,6 @@ static int dw_ictl_intr_get_line_state(struct device *dev, unsigned int irq)
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static void dw_ictl_config_irq(struct device *dev);
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static const struct dw_ictl_config dw_config = {
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.irq_num = DT_INTC_DW_0_BASE_ADDR,
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.numirqs = DT_INTC_DW_0_NUM_IRQS,
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.isr_table_offset = CONFIG_DW_ISR_TBL_OFFSET,
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.config_func = dw_ictl_config_irq,
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@ -16,6 +16,7 @@ extern "C" {
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typedef void (*dw_ictl_config_irq_t)(struct device *dev);
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struct dw_ictl_config {
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u32_t base_addr;
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u32_t numirqs;
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u32_t isr_table_offset;
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dw_ictl_config_irq_t config_func;
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@ -95,6 +95,7 @@
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interrupts = <6 0 0>;
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num-irqs = <9>;
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interrupt-parent = <&cavs0>;
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label = "DW_INTC";
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};
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gpio0: gpio@80c00 {
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@ -38,7 +38,7 @@
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#define DT_INTC_DW_0_BASE_ADDR \
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DT_SNPS_DESIGNWARE_INTC_81800_BASE_ADDRESS
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#define DT_INTC_DW_0_NAME DT_SNPS_DESIGNWARE_INTC_81800_LABEL
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#define DT_INTC_DW_0_IRQ DDT_SNPS_DESIGNWARE_INTC_81800_IRQ_0
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#define DT_INTC_DW_0_IRQ DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0
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#define DT_INTC_DW_0_IRQ_PRI \
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DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0_PRIORITY
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#define DT_INTC_DW_0_IRQ_FLAGS \
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@ -43,7 +43,7 @@
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#define IOAPIC_HIGH 0
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/* DW interrupt controller */
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#define DW_ICTL_IRQ_CAVS_OFFSET CAVS_IRQ_NUMBER(DT_DW_ICTL_IRQ)
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#define DW_ICTL_IRQ_CAVS_OFFSET CAVS_IRQ_NUMBER(DT_INTC_DW_0_IRQ)
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#define DW_ICTL_NUM_IRQS 9
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/* GPIO */
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