x86: apollo_lake: changes GPIO definition in DTS

This breaks down the GPIO controller definition in DTS into
multiple entries. This allows these controllers to be
referenced by other DTS, and test board overlay files.
And also we can remove the entries in the dts fixup file.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2019-12-11 20:37:04 -08:00 committed by Carles Cufí
commit 07cb01b079
5 changed files with 207 additions and 61 deletions

View file

@ -36,7 +36,7 @@
* as well, but my (admitted cursory) testing disagrees.
*/
BUILD_ASSERT(DT_APL_GPIO_IRQ == 14);
BUILD_ASSERT(DT_INST_0_INTEL_APL_GPIO_IRQ_0 == 14);
#define REG_PAD_BASE_ADDR 0x000C
@ -627,12 +627,15 @@ int gpio_intel_apl_init(struct device *dev)
__ASSERT(nr_isr_devs < GPIO_INTEL_APL_NR_SUBDEVS, "too many subdevs");
if (nr_isr_devs == 0) {
IRQ_CONNECT(DT_APL_GPIO_IRQ,
DT_APL_GPIO_IRQ_PRIORITY,
/* Note that all controllers are using the same IRQ line.
* So we can just use the values from the first instance.
*/
IRQ_CONNECT(DT_INST_0_INTEL_APL_GPIO_IRQ_0,
DT_INST_0_INTEL_APL_GPIO_IRQ_0_PRIORITY,
gpio_intel_apl_isr, NULL,
DT_APL_GPIO_IRQ_SENSE);
DT_INST_0_INTEL_APL_GPIO_IRQ_0_SENSE);
irq_enable(DT_APL_GPIO_IRQ);
irq_enable(DT_INST_0_INTEL_APL_GPIO_IRQ_0);
}
isr_devs[nr_isr_devs++] = dev;
@ -647,18 +650,19 @@ int gpio_intel_apl_init(struct device *dev)
return 0;
}
#define GPIO_INTEL_APL_DEV_CFG_DATA(dir_l, dir_u, pos, offset, pins) \
#define GPIO_INTEL_APL_DEV_CFG_DATA(dir_l, dir_u, pos) \
static const struct gpio_intel_apl_config \
gpio_intel_apl_cfg_##dir_l##_##pos = { \
.reg_base = DT_APL_GPIO_BASE_ADDRESS_##dir_u, \
.pin_offset = offset, \
.num_pins = pins, \
.reg_base = (DT_ALIAS_GPIO_##dir_u##_##pos##_BASE_ADDRESS \
& 0xFFFFFF00), \
.pin_offset = DT_ALIAS_GPIO_##dir_u##_##pos##_PIN_OFFSET, \
.num_pins = DT_ALIAS_GPIO_##dir_u##_##pos##_NGPIOS, \
}; \
\
static struct gpio_intel_apl_data gpio_intel_apl_data_##dir_l##_##pos; \
\
DEVICE_AND_API_INIT(gpio_intel_apl_##dir_l##_##pos, \
DT_APL_GPIO_LABEL_##dir_u##_##pos, \
DT_ALIAS_GPIO_##dir_u##_##pos##_LABEL, \
gpio_intel_apl_init, \
&gpio_intel_apl_data_##dir_l##_##pos, \
&gpio_intel_apl_cfg_##dir_l##_##pos, \
@ -667,16 +671,16 @@ DEVICE_AND_API_INIT(gpio_intel_apl_##dir_l##_##pos, \
/* "sub" devices. no more than GPIO_INTEL_APL_NR_SUBDEVS of these! */
GPIO_INTEL_APL_DEV_CFG_DATA(n, N, 0, 0, 32);
GPIO_INTEL_APL_DEV_CFG_DATA(n, N, 1, 32, 32);
GPIO_INTEL_APL_DEV_CFG_DATA(n, N, 2, 32, 14);
GPIO_INTEL_APL_DEV_CFG_DATA(n, N, 000);
GPIO_INTEL_APL_DEV_CFG_DATA(n, N, 032);
GPIO_INTEL_APL_DEV_CFG_DATA(n, N, 064);
GPIO_INTEL_APL_DEV_CFG_DATA(nw, NW, 0, 0, 32);
GPIO_INTEL_APL_DEV_CFG_DATA(nw, NW, 1, 32, 32);
GPIO_INTEL_APL_DEV_CFG_DATA(nw, NW, 2, 32, 13);
GPIO_INTEL_APL_DEV_CFG_DATA(nw, NW, 000);
GPIO_INTEL_APL_DEV_CFG_DATA(nw, NW, 032);
GPIO_INTEL_APL_DEV_CFG_DATA(nw, NW, 064);
GPIO_INTEL_APL_DEV_CFG_DATA(w, W, 0, 0, 32);
GPIO_INTEL_APL_DEV_CFG_DATA(w, W, 1, 32, 15);
GPIO_INTEL_APL_DEV_CFG_DATA(w, W, 000);
GPIO_INTEL_APL_DEV_CFG_DATA(w, W, 032);
GPIO_INTEL_APL_DEV_CFG_DATA(sw, SW, 0, 0, 32);
GPIO_INTEL_APL_DEV_CFG_DATA(sw, SW, 1, 32, 11);
GPIO_INTEL_APL_DEV_CFG_DATA(sw, SW, 000);
GPIO_INTEL_APL_DEV_CFG_DATA(sw, SW, 032);

View file

@ -17,6 +17,14 @@ properties:
interrupts:
required: true
ngpios:
required: true
pin-offset:
type: int
required: true
description: Pin offset of this GPIO entry
"#gpio-cells":
const: 2

View file

@ -35,6 +35,19 @@
#interrupt-cells = <3>;
};
aliases {
gpio-n-000 = &gpio_n_000_031;
gpio-n-032 = &gpio_n_032_063;
gpio-n-064 = &gpio_n_064_077;
gpio-nw-000 = &gpio_nw_000_031;
gpio-nw-032 = &gpio_nw_032_063;
gpio-nw-064 = &gpio_nw_064_076;
gpio-w-000 = &gpio_w_000_031;
gpio-w-032 = &gpio_w_032_046;
gpio-sw-000 = &gpio_sw_000_031;
gpio-sw-032 = &gpio_sw_032_042;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
@ -212,19 +225,164 @@
status = "okay";
};
gpio: gpio@d0c50000 {
gpio_n_000_031: gpio@d0c50000 {
compatible = "intel,apl-gpio";
reg = <0xd0c50000 0x1000>,
<0xd0c40000 0x1000>,
<0xd0c70000 0x1000>,
<0xd0c00000 0x1000>;
reg = <0xd0c50000 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "APL_GPIO";
gpio-controller ;
label = "GPIO_N_000";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
pin-offset = <0>;
status = "okay";
};
gpio_n_032_063: gpio@d0c50001 {
compatible = "intel,apl-gpio";
reg = <0xd0c50001 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "GPIO_N_032";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
pin-offset = <32>;
status = "okay";
};
gpio_n_064_077: gpio@d0c50002 {
compatible = "intel,apl-gpio";
reg = <0xd0c50002 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "GPIO_N_064";
gpio-controller;
#gpio-cells = <2>;
ngpios = <14>;
pin-offset = <64>;
status = "okay";
};
gpio_nw_000_031: gpio@d0c40000 {
compatible = "intel,apl-gpio";
reg = <0xd0c40000 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "GPIO_NW_000";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
pin-offset = <0>;
status = "okay";
};
gpio_nw_032_063: gpio@d0c40001 {
compatible = "intel,apl-gpio";
reg = <0xd0c40001 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "GPIO_NW_032";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
pin-offset = <32>;
status = "okay";
};
gpio_nw_064_076: gpio@d0c40002 {
compatible = "intel,apl-gpio";
reg = <0xd0c40002 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "GPIO_NW_064";
gpio-controller;
#gpio-cells = <2>;
ngpios = <64>;
pin-offset = <13>;
status = "okay";
};
gpio_w_000_031: gpio@d0c70000 {
compatible = "intel,apl-gpio";
reg = <0xd0c70000 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "GPIO_W_000";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
pin-offset = <0>;
status = "okay";
};
gpio_w_032_046: gpio@d0c70001 {
compatible = "intel,apl-gpio";
reg = <0xd0c70001 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "GPIO_W_032";
gpio-controller;
#gpio-cells = <2>;
ngpios = <15>;
pin-offset = <32>;
status = "okay";
};
gpio_sw_000_031: gpio@d0c00000 {
compatible = "intel,apl-gpio";
reg = <0xd0c00000 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "GPIO_SW_000";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
pin-offset = <0>;
status = "okay";
};
gpio_sw_032_042: gpio@d0c00001 {
compatible = "intel,apl-gpio";
reg = <0xd0c00001 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "GPIO_SW_032";
gpio-controller;
#gpio-cells = <2>;
ngpios = <11>;
pin-offset = <32>;
status = "okay";
};

View file

@ -12,30 +12,6 @@
#define DT_ROM_SIZE CONFIG_FLASH_SIZE
#define DT_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS
#define DT_APL_GPIO_BASE_ADDRESS_N DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_0
#define DT_APL_GPIO_BASE_ADDRESS_NW DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_1
#define DT_APL_GPIO_BASE_ADDRESS_W DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_2
#define DT_APL_GPIO_BASE_ADDRESS_SW DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_3
#define DT_APL_GPIO_IRQ DT_INTEL_APL_GPIO_D0C50000_IRQ_0
#define DT_APL_GPIO_IRQ_PRIORITY DT_INTEL_APL_GPIO_D0C50000_IRQ_0_PRIORITY
#define DT_APL_GPIO_IRQ_SENSE DT_INTEL_APL_GPIO_D0C50000_IRQ_0_SENSE
#define DT_APL_GPIO_MEM_SIZE_N DT_INTEL_APL_GPIO_D0C50000_SIZE_0
#define DT_APL_GPIO_MEM_SIZE_NW DT_INTEL_APL_GPIO_D0C50000_SIZE_1
#define DT_APL_GPIO_MEM_SIZE_W DT_INTEL_APL_GPIO_D0C50000_SIZE_2
#define DT_APL_GPIO_MEM_SIZE_SW DT_INTEL_APL_GPIO_D0C50000_SIZE_3
#define DT_APL_GPIO_LABEL_N_0 DT_INTEL_APL_GPIO_D0C50000_LABEL "_N_0"
#define DT_APL_GPIO_LABEL_N_1 DT_INTEL_APL_GPIO_D0C50000_LABEL "_N_1"
#define DT_APL_GPIO_LABEL_N_2 DT_INTEL_APL_GPIO_D0C50000_LABEL "_N_2"
#define DT_APL_GPIO_LABEL_NW_0 DT_INTEL_APL_GPIO_D0C50000_LABEL "_NW_0"
#define DT_APL_GPIO_LABEL_NW_1 DT_INTEL_APL_GPIO_D0C50000_LABEL "_NW_1"
#define DT_APL_GPIO_LABEL_NW_2 DT_INTEL_APL_GPIO_D0C50000_LABEL "_NW_2"
#define DT_APL_GPIO_LABEL_W_0 DT_INTEL_APL_GPIO_D0C50000_LABEL "_W_0"
#define DT_APL_GPIO_LABEL_W_1 DT_INTEL_APL_GPIO_D0C50000_LABEL "_W_1"
#define DT_APL_GPIO_LABEL_SW_0 DT_INTEL_APL_GPIO_D0C50000_LABEL "_SW_0"
#define DT_APL_GPIO_LABEL_SW_1 DT_INTEL_APL_GPIO_D0C50000_LABEL "_SW_1"
#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_INST_0_NS16550_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_SIZE DT_INST_0_NS16550_SIZE

View file

@ -15,7 +15,7 @@
#ifndef __SOC_GPIO_H_
#define __SOC_GPIO_H_
#define APL_GPIO_DEV_N_0 DT_APL_GPIO_LABEL_N_0
#define APL_GPIO_DEV_N_0 DT_ALIAS_GPIO_N_000_LABEL
#define APL_GPIO_0 0
#define APL_GPIO_1 1
#define APL_GPIO_2 2
@ -49,7 +49,7 @@
#define APL_GPIO_30 30
#define APL_GPIO_31 31
#define APL_GPIO_DEV_N_1 DT_APL_GPIO_LABEL_N_1
#define APL_GPIO_DEV_N_1 DT_ALIAS_GPIO_N_032_LABEL
#define APL_GPIO_32 0
#define APL_GPIO_33 1
#define APL_GPIO_34 2
@ -83,7 +83,7 @@
#define APL_GPIO_TCK 30
#define APL_GPIO_TRST_B 31
#define APL_GPIO_DEV_N_2 DT_APL_GPIO_LABEL_N_2
#define APL_GPIO_DEV_N_2 DT_ALIAS_GPIO_N_064_LABEL
#define APL_GPIO_TMS 0
#define APL_GPIO_TDI 1
#define APL_GPIO_CX_PMODE 2
@ -99,7 +99,7 @@
#define APL_GPIO_SVOD0_DATA 12
#define APL_GPIO_SVOD0_CLK 13
#define APL_GPIO_DEV_NW_0 DT_APL_GPIO_LABEL_NW_0
#define APL_GPIO_DEV_NW_0 DT_ALIAS_GPIO_NW_000_LABEL
#define APL_GPIO_187 0
#define APL_GPIO_188 1
#define APL_GPIO_189 2
@ -133,7 +133,7 @@
#define APL_GPIO_PMIC_STDBY 30
#define APL_GPIO_PROCHOT_B 31
#define APL_GPIO_DEV_NW_1 DT_APL_GPIO_LABEL_NW_1
#define APL_GPIO_DEV_NW_1 DT_ALIAS_GPIO_NW_032_LABEL
#define APL_GPIO_PMIC_I2C_SCL 0
#define APL_GPIO_PMIC_I2C_SDA 1
#define APL_GPIO_74 2
@ -167,7 +167,7 @@
#define APL_GPIO_105 30
#define APL_GPIO_106 31
#define APL_GPIO_DEV_NW_2 DT_APL_GPIO_LABEL_NW_2
#define APL_GPIO_DEV_NW_2 DT_ALIAS_GPIO_NW_064_LABEL
#define APL_GPIO_109 0
#define APL_GPIO_110 1
#define APL_GPIO_111 2
@ -182,7 +182,7 @@
#define APL_GPIO_122 11
#define APL_GPIO_123 12
#define APL_GPIO_DEV_W_0 DT_APL_GPIO_LABEL_W_0
#define APL_GPIO_DEV_W_0 DT_ALIAS_GPIO_W_000_LABEL
#define APL_GPIO_124 0
#define APL_GPIO_125 1
#define APL_GPIO_126 2
@ -216,7 +216,7 @@
#define APL_GPIO_OSC_CLK_OUT_0 30
#define APL_GPIO_OSC_CLK_OUT_1 31
#define APL_GPIO_DEV_W_1 DT_APL_GPIO_LABEL_W_1
#define APL_GPIO_DEV_W_1 DT_ALIAS_GPIO_W_032_LABEL
#define APL_GPIO_OSC_CLK_OUT_2 0
#define APL_GPIO_OSC_CLK_OUT_3 1
#define APL_GPIO_OSC_CLK_OUT_4 2
@ -233,7 +233,7 @@
#define APL_GPIO_SUS_STAT_B 13
#define APL_GPIO_SUSPWRDNACK 14
#define APL_GPIO_DEV_SW_0 DT_APL_GPIO_LABEL_SW_0
#define APL_GPIO_DEV_SW_0 DT_ALIAS_GPIO_SW_000_LABEL
#define APL_GPIO_205 0
#define APL_GPIO_206 1
#define APL_GPIO_207 2
@ -267,7 +267,7 @@
#define APL_GPIO_183 30
#define APL_GPIO_SMB_ALERTB 31
#define APL_GPIO_DEV_SW_1 DT_APL_GPIO_LABEL_SW_1
#define APL_GPIO_DEV_SW_1 DT_ALIAS_GPIO_SW_032_LABEL
#define APL_GPIO_SMB_CLK 0
#define APL_GPIO_SMB_DATA 1
#define APL_GPIO_LPC_ILB_SERIRQ 2