This commit adds CAN support for nucleo F746zg.
Furtermore CAN was added in stm32f7.dtsi and pinmuc_stm32f7.h
CAN_RX: PD0, CAN_TX: PD1
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
2 identical packages were defined for stm32f412 SoC, invariant "g".
Merge them in new sinclge stm32f412Xg.dtsi.
Update matching boards accordinlgy.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
SAMD20 does not have the DMA or USB peripherals and as a result
the IRQs for all subsequent lines are shifted down from SAMD21.
This splits the interrupt assignment for the SERCOMs into the
SoC specific DTS file and moves the USB definition to SAMD21 only.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
Update the files which contain no license information with the
'Apache-2.0' SPDX license identifier. Many source files in the tree are
missing licensing information, which makes it harder for compliance
tools to determine the correct license.
By default all files without license information are under the default
license of Zephyr, which is Apache version 2.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Ports B and C share a common interrupt vector on kw40 and kw41z socs,
but we don't currently have a way to express this in device tree. A
check was added in commit 77cb942a97 that
correctly causes build errors on kw40/41 boards when both ports are
enabled.
Disable the port b interrupt for now until we have a better way to
handle this.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
According to nrf51 and nrf52 specifaction every peripheral is
assigned a fixed block of 0x1000 bytes. Due to that dts for
nrf51 and nrf52 chips have been updated.
The only exception is gpio for nrf52840 where gpio0 and gpio1
share the same memory regions. For this reason, the definition
of gpio for nrf52840 is different from the others.
Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
On various stm32 soc packages CCM is available and SRAM size
mentionned in datasheet include CCM.
Though, actual SRAM size defined in dtsi files should not
include CCM sizes.
Fix this on impacted dtsi files.
Fixes#14779
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The iMX RT1060 and RT1064 have additional dedicated 512KB on-chip ram.
This OCRAM2 is mapped at 0x20200000, formerly OCRAM1 (flexram) mapping
which is moved to 0x20280000 in order to guarentee global OCRAM memory
continuity regardless OCRAM1 size configuration (256KB by default).
In default configuration, this gives 768KB (512+256) on-chip ram:
0x20200000 to 0x202BFFFF.
OCRAM2: 0x20200000 - 0x2027FFFF
OCRAM1(FlexRam): 0x2028FFFF - 0x202BFFFF
Add this memory region as a single node in the rt1060 device tree.
Note: MPU expects power of two memory region, in case of 768KB, let
the MPU configure 1MB instead.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
uart4 is not available on whole stm32f4 series (not on stm32f401
for instance), remove from stm32f4.dtsi
It is actually correctly defined in f405, f413 but missing in f446,
so add it in there.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
1. SW PWM device node added to common nrf5_common.dtsi
2. SW PWM node set in all nRF5x DTSI files.
Different initial settings for nRF51 and nRF52 devices.
Status is ok by default for nRF51.
3. Added yaml binding for Nordic SW PWM node.
4. Set codeowner of nordic dts bindings to @anangl
Signed-off-by: Gaute Gamnes <gaute.gamnes@nordicsemi.no>
In the recent MDK brought by nrfx 1.6.2, these legacy peripherals have
been revealed as available also in nRF52810. This patch allows their
use in Zephyr drivers.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
On currently supported stm32f3 chips,
erase-block-size = 2048
write-block-size = 2
Set these property in stm32f3 series root dtsi file.
Fixes#9686
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add nvs support to nucleo_f091rc board. This requires to
add erase-block-size property to stm32f0.dtsi.
Storage partition is set to 4kb at the end of the flash.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Initial support for Microchip MEC1701 series is incorporated to the
tree. Additional support for UART is also included. This SOC supports
two operation modes for interrupts (Direct and Aggregated). For this
commit, the interrupts are configured in direct mode.
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
This patch adds basic support for the PWM devices available on the Atmel
SAM family. Beside enabling the driver, everything is selected through
the device tree, including enabling the PWM0 and PWM1 devices. Thus
CONFIG_PWM_0 and CONFIG_PWM_1 are ignored.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Add EPIT (Enhanced Periodic Interrupt Timer) peripheral support
for i.MX6SoloX soc.
Origin: Original
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Adds device tree bindings for the imx enhanced LCD interface (eLCDIF)
controller. The compatible is reused from linux.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Actually, add the "status" property that enables the nodes explicitly.
They were apparently enabled by default without this property.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use the new DT_<COMPAT>_<INSTANCE>_<PROP> defines to instantiate
devices. This commit adds also ability to define individual pin
locations on SoC series that support the feature. Definitions of GPIO
pins assigned to a given location have been moved from soc_pinmap.h file
to board DTS file.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Use the new DT_<COMPAT>_<INSTANCE>_<PROP> defines to instantiate
devices. This commit adds also ability to define individual pin
locations on SoC series that support the feature. Definitions of GPIO
pins assigned to a given location have been moved from soc_pinmap.h file
to board DTS file.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Use the new DT_<COMPAT>_<INSTANCE>_<PROP> defines to instantiate
devices. This commit adds also ability to define individual pin
locations on SoC series that support the feature. Definitions of GPIO
pins assigned to a given location have been moved from soc_pinmap.h file
to board DTS file.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Add sam0_rtc_driver that implements system timer API on top of the RTC
and can be used as a replacement for the default systick timer.
Signed-off-by: Martin Benda <martin.benda@omsquare.com>
This commit introduces the possibility to have multiple
device nodes attached to the same I2S controller. For this
purpose a new i2s-device.yaml description has been introduced
with the a 'reg' property to define the logic number of the
device. For example, if two microphones are attached to the
same I2S port (say 1) to achieve stereo audio, the two microphones
might be described in dts as:
&i2s1 {
status = "ok";
mic@0 {
compatible = "...";
reg = <0>;
label = "...";
};
mic@1 {
compatible = "...";
reg = <1>;
label = "...";
};
};
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Added UART4 alternate pin function for L4 µC for PC10 and PC11.
Corrected naming of previously defined UART4 TX and RX defines.
Signed-off-by: Georgij Cernysiov <g.cernysiov@elco-automation.de>
The SPI1 controller that is connected to the mcr20a block utilizes the
hardware chipselect and not a GPIO CS. So remove the cs-gpios property.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The SPI0 node had a property called 'cs' which wasn't used or defined as
part of the binding yaml. So let's remove it.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We get warnings from dtc when building any of the NXP i.MX-RT boards of
the form:
mimxrt1020_evk.dts_compiled: Warning (simple_bus_reg):
/soc/random@400CC000: simple-bus unit address format
error, expected "400cc000"
Simple fix to make everything lowercase to have the unit-address and reg
match.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Adds STM32 L452 soc with L452xC variant. L452 has 160 KB SRAM;
therefore, mpu mem config has been extended; IRQ number is based on
'stm32l452xx.h'.
Signed-off-by: Georgij Cernysiov <g.cernysiov@elco-automation.de>
Use the symbol generated from DT so that it is common for nRF9160
and nRF5 family SoCs. To avoid artificial renaming of CLOCK_POWER_IRQn
to POWER_CLOCK_IRQn.
For nRF5 family SoCs clock nodes were not defined so far, thus they are
added so that the proper DT symbol is generated for them as well.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add missing node for instance 0 of the RTC peripheral and use an alias
to the flash-controller node instead of the nvmc node definition (there
is no need to have a separate node just to get the NVMC base address).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
