All pinmux supporting CAN, SPI and I2C of F7 series are added.
Since the F7 series supports up to two CANs,
the pin names of CANs have been changed.
Several minor pinmux errors have also been fixed.
Sorted by Alternate function.
Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr>
PA selection mainly depends on board design. So it looks like
device-tree is a better mechanism than Kconfig in this case. Use string
property with two possible values: "rfo" and "pa-boost".
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Changes to the PLL configuration were required
for proper device enumeration. Now there is a 48MHz USB clock
(was 25MHz), and a 96MHz system clock (was 100 MHz).
Addresses #25293
Signed-off-by: Brian Bradley <brian.bradley.p@gmail.com>
With addition of flash_get_parameters API call, it is needed to provide
support for the API to flash drivers.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Now that the SAM0 SOC selects the appropriate SAM0 driver for a class,
reduce the drivers that are compiled in by default on the Arduino
Zero. This reduces the size of `blink` from ~14 KiB to ~10 KiB.
Also add the supported features to arduino_zero.yaml to get more
coverage in the sanity tests.
Signed-off-by: Michael Hope <mlhx@google.com>
The DTS for nRF53 and nRF91 boards has been modified to cut the size
of boot partition from 64KiB to 48KiB, making it the same size as for
nRF52.
Resolves#25664
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Only boards with at least 64K Flash will activate MPU because:
MPU + UERSPACE + All switches implicity activated
(CONFIG_MPU_STACK_GUARD, CONFIG_ARM_STACK_PROTECTION ...)
will consume about 40K Flash
(value computed on nucleo_f767_zi on tests/arch/arm/arm_ramfunc/).
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Add support for the polarity flag in the STM32 PWM driver.
STM32 boards using PWM have been updated accordingly.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add devicetree nodes for the Arduino GPIO and MikroElektronika
mikroBUS headers present on the NXP LPCXpresso55S16 development board.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Bluetooth interacts with real-world hardware and thus requires the QEMU
target to follow wall time, and not have a free running timer that is
much faster than actual wall time.
Diable the QEMU icount mechanism when Bluetooth is enabled.
Fixes#26242
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
With latest SDK release v0.11.3 basic SMP support for HSDK
board was introduced in OpenOCD. Lets enable smp in openocd.cfg,
so using west we would be able to run Zephyr on all 4 cores.
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Implement stubs for ARM CMSIS intrinsics,
to be used locally for nrf52_bsim builds.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Provide a very simple model of the DSB ARM
instruction as no-operation. The implementation
is provided in a cmsis.h header file added
in the nrf52_bsim board directory.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Appropriate WS can be loaded automatically if
the display controller has integrated temperature
sensor or an external sensor is connected.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
Enable GPIO as a workaround to enable some SPI slaves are not correctly
controlled using the Flexcomm SPI device.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
This patch introduces the new b_l4s5i_iot01a discovery kit
from STMicroelectronics.
This is a IOT node based on the stm32l4s5vi
including MEMS, Bluetooth BLE, WiFi and NFC modules
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Replace usage of deprecated GPIO_INT_ACTIVE_LOW, GPIO_INT_ACTIVE_HIGH,
GPIO_PUD_PULL_UP flags with a new equivalent in a few boards that were
added after 2.2 release.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Added / Tested support for RNG on the STM32F767ZI nucleo board.
Updated the SoC defconfig to auto-enable the driver when
ENTROPY_GENERATOR is enabled, and updated the board README.
Signed-off-by: Bilal Wasim <bilalwasim676@gmail.com>
- Change default CPU Clock to 240MHz
(PLL is activated)
- I2C, UART will use sysclk from clock driver
- esp32_enable_peripheral replaced by
clock_control_on
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
- Support PLL for Higher Frequencies 80,160,240 MHz
- Support XTAL Frequencies 26MHz, 40MHz
- Clock Driver can't be disabled, because all of the other drivers
will depend on it to get their operating Frequency based on chosen
clock source (XTAL/PLL).
- Add needed references to BBPLL i2c bus ROM functions.
- Add `rtc` node to Device Tree.
- Since All Peripherals Frequency is depending on CPU_CLK Source,
`clock-source` property added to CPU node
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
tested on mimxrt1060_evt
MEMORY_NOCACHE is needed
test on frdmk64f
special test slot need configure with
CONFIG_DMA_TEST_SLOT_START
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Add support for Bluetooth Controller GPIO Debug Pins for
nRF5340 PDK board. GPIO Pin toggling can be captured on the
P3 pinhead of the PDK.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
The `netif` capability is needed for certain samples to be built by the
CI for a target platform. As it was missing for nrf52840dk_nrf52840,
echo samples with OpenThread support were not being built and thus not
tested by the CI.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
The STM32L072CZ MCU has a built-in USB device controller which is
supported by Zephyr's USB STM32 driver. The b_l072z_lrwan1 board has a
micro-USB connector that is wired to the MCU via two solder bridges
(SB15 and SB16) that need to be closed to connect the data lines.
Update the board documentation to describe the solder bridges and
enable the USB controller in the device tree.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
* current supported boards:
* emsk, iotdk, nsim, emsdp, hsdk.
* for the unsupported future boards, pls take a
reference of supported boards' board.cmake.
* mdb runner is required and the default runner for SMP
case, e.g., HSDK and nsim_hs_smp.
* other ARC boards can also choose to use mdb by
setting runner as mdb, e.g. west flash --runner mdb.
* with mdb runner, user can make a debug through mdb gui
* with arc_nsim or opencod runner (default runner), user
can make a debug through gdb cmdline.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Provide devicetree configuration for UART2 on the mesh feather header.
The peripheral must be enabled in an overlay, optionally including a
provided overlay with the hardware flow control signals.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Default alternate function for the MEC15xx VCI pins makes them
HW-controlled.
Most common scenario is that pins are used as GPIOs, however
there are still some board designs where HW-controlled is desired.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
The ip_k66f board can run with clock frequency of 180 MHz. This requires
switching it to high speed mode (HSRUN).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This patch adds information regarding usage of serial console on
the ip_k66f board, as it only can use Segger's RTT console for
communication.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This change allows usage of larger RTT "UP" buffers from target to host.
It is necessary to allow correct execution of ping command:
net ping 192.168.0.1
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The ip_k66f board (embOS/IP switch) from Segger doesn't have the serial
console pins connected to J-Link OB. As a result one needs to use RTT
to get the serial console.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The documentation page in Zephyr states that the STM32L072CZ has 20KiB
of EEPROM. This is incorrect, the datasheet (and DTS) indicates that
it has 6KiB of EEPROM.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
The STM32L072CZ has an EEPROM for user configuration. Enable this for
the B-L072Z-LRWAN1 Discovery kit.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
This patch enables the rtc so that the testcase
tests/drivers/counter/counter_basic_api
can run on this nucleo_stm32f207 board
also when running sanity check
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The "gccarmemb" toolchain type has been renamed to "gnuarmemb" to
better reflect the official naming.
This commit replaces all references to the "gccarmemb" toolchain type
to "gnuarmemb".
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Removed flow control configuration from Kconfig and updated samples
to use device tree for that.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
The Adafruit ItsyBitsy M4 express is a small (36 mm x 18 mm) ARM
development board with an onboard RGB LED, USB port, 2 MiB of SPI
flash, and range of I/O broken out onto 23 GPIO pins.
Signed-off-by: Michael Hope <mlhx@google.com>
emsdp_em7d_esp is a board with secure just like em_starterkit_em7d,
but the secure feature not configed in defconfig file. we need to add
below configs in emsdp_em7d_esp_defconfig files:
CONFIG_ARC_HAS_SECURE=y
CONFIG_TRUSTED_EXECUTION_SECURE=y
when secure feature enabled, we use secure timer for system tick, so
we need to add below macro for secure timer:
#define IRQ_SEC_TIMER0 20
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
In order for the application to be flashed beginning at address 0,
which is desired when flashing with an external probe,
BOARD_HAS_NRF5_BOOTLOADER must be set to n.
Signed-off-by: Jacob Siverskog <jacob@teenage.engineering>
This follows the board porting guide. Only the the board
efm32hg_slstk3400a does not include a SoC containting an MPU.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
Now when we're finally ready to open QEMU port for ARC
we introduce the first ever platform it supports and in fact does
that quite well - Zephyr RTOS.
For now we only offer support of basic EM & HS code execution,
built-in timers, interrupt controller and set of very simple
peripherals: DW UART & optionally MMIO Virtio devices.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
We only need a 'compatible' entry for the DK,
not the SoC and part-number. This commit fixes
this and aligns the nRF5340 PDK DTS with the
remainder of nRF-based boards.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Conditionalizes csi pinmuxes on CONFIG_VIDEO for all nxp boards
(kinetis, lpc, and imx families) to avoid possible conflicts between
peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Conditionalizes display pinmuxes on CONFIG_DISPLAY for all nxp boards
(kinetis, lpc, and imx families) to avoid possible conflicts between
peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Conditionalizes dac pinmuxes on CONFIG_DAC for all nxp boards (kinetis,
lpc, and imx families) to avoid possible conflicts between peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Conditionalizes can pinmuxes on CONFIG_CAN for all nxp boards (kinetis,
lpc, and imx families) to avoid possible conflicts between peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Conditionalizes ethernet pinmuxes on CONFIG_NET_L2_ETHERNET for all nxp
boards (kinetis, lpc, and imx families) to avoid possible conflicts
between peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Conditionalizes pwm pinmuxes on CONFIG_PWM for all nxp boards (kinetis,
lpc, and imx families) to avoid possible conflicts between peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Conditionalizes adc pinmuxes on CONFIG_ADC for all nxp boards (kinetis,
lpc, and imx families) to avoid possible conflicts between peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Conditionalizes i2c pinmuxes on CONFIG_I2C for all nxp boards (kinetis,
lpc, and imx families) to avoid possible conflicts between peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Conditionalizes spi pinmuxes on CONFIG_SPI for all nxp boards (kinetis,
lpc, and imx families) to avoid possible conflicts between peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Conditionalizes serial pinmuxes on CONFIG_SERIAL for all nxp boards
(kinetis, lpc, and imx families) to avoid possible conflicts between
peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Pins p0.02/p0.03 that were assigned to the i2c1 node are NFC pins.
Use p1.02/p1.03 instead, which are routed to the standard I2C location
in the Arduino header.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Conditionalizes pinmuxes on associated driver configs (CONFIG_SERIAL,
CONFIG_I2C, etc.) for the rv32m1_vega board to avoid possible conflicts
between peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
I2C1 used LED pins rather than the ones in the Arduino header
position. SPI2 used Arduino D0 for both SCK and MOSI; replace all
pins with D11-D13 which are the standard location for SPI on the
Arduino header.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Enables the adc instance and pinmux associated with arduino header pin
A2 on the frdm_k82 board. Adds adc to the board yaml to ensure we build
adc samples/tests for this board in CI.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
As a slow FPGA platform with max. freq < 25 Mhz,
the default CON_SYS_CLOCK_TICKS_PER_SEC=10000 is
not suitable. CON_SYS_CLOCK_TICKS_PER_SEC=100 is
a better value.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Map Arduino interface to LPCXpresso55S69 pins.
Also tell which SPI interface is used by Arduino.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Map mikroBUS interface to LPCXpresso55S69 pins.
Also tell which SPI interface is used by mikroBUS.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Adds support for a new SHIELD, Eth Click.
Mikro-BUS type shield supported in Zephyr.
Adds Kconfig for mikroe_eth_click shield.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_DISK_ACCESS_STM32_SDMMC flag to for each SDMMC pinmux
configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_I2S flag to for each i2s pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_CAN flag to for each can pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_DAC flag to for each dac pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_ADC flag to for each adc pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_PWM flag to for each pwm pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_I2C flag to for each i2c pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_SPI flag to for each spi pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_SERIAL flag to for each serial pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add an additional check for CONFIG_PWM to decide if pins associated with
LED are configured for GPIO or PWM.
Fixes#25337
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This makes the up_squared board default to x86_64.
This also adds a new board, up_squared_32, for when 32-bit
is desired.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Given that the UP Squared has relatively large memory, the default
number of pages allocated for page tables are not enough, and
resulting in asserting in the page table initialization code.
So change the number of pages to a large number to accomodate
various applications.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The APIC timer is not supported e.g. with SMP (which will be enabled
by default soon as well) so the sensible choice is to default to HPET.
Also, the default makes more sense to be on the SoC side, so move it
there from the board defaults.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Let the default value for SYS_CLOCK_HW_CYCLES_PER_SEC come from the
SoC instead. Furthermore, a default for HPET_TIMER didn't even make
sense since this timer doesn't do anything with the Kconfig value.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
OpenOCD currently uses a single-bank STM32 configuration for the
B_L072Z_LRWAN1 board. This causes flashing to fail when the firmware
image is larger than the first bank. Switch to the dual bank
configuration to make this work.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Enable icount mode for qemu_xtensa platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for hifive1 platform, The icount shift value is
selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_riscv64 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_riscv32 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_cortex_a53 platform, The icount shift
value is selectd based on cpu clock frequency of this platform.
The virtual cpu will execute one instruction every 2^shift ns of
virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_cortex_m3 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_cortex_m0 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_x86 platform, The icount shift value is
selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Remove the existing qemu icount configuration because icount mode
will be controlled by Kconfig QEMU_ICOUNT so that none suitable
cases(especially networking cases) can exclude icount configuration
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
The length field for the MCUBOOT slot partitions in Nordic platforms
has always had an extra leading zero suggesting it's a 40-bit value,
being stored in a 32-bit field. Remove the incorrect leading zero to
reduce misunderstanding of the field.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Several reviewers agreed that DT_HAS_NODE_STATUS_OKAY(...) was an
undesirable API for the following reasons:
- it's inconsistent with the rest of the DT_NODE_HAS_FOO names
- DT_NODE_HAS_FOO_BAR_BAZ(node) was agreed upon as a shorthand
for macros which are equivalent to
DT_NODE_HAS_FOO(node) && DT_NODE_HAS_BAR(node) &&
- DT_NODE_HAS_BAZ(node), and DT_HAS_NODE_STATUS_OKAY is an odd duck
- DT_NODE_HAS_STATUS(..., okay) was viewed as more readable anyway
- it is seen as a somewhat aesthetically challenged name
Replace all users with DT_NODE_HAS_STATUS(..., okay), which is
semantically equivalent.
This is mostly done with sed, but a few remaining cases were done by
hand, along with whitespace, docs, and comment changes. These special
cases include the Nordic SOC static assert files.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
When we build Zephyr as Secure image on nRF340 Application
MCU and nRF9160 SoC we would like to pass the information
about the reserved memory area allocated to the Non-Secure
images. The information may be needed to apply proper
security configuration. We add a "chosen" node in board .dts
file for this purpose.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We do not want sram0_ns and sram0_bsd to represent physical
ram; these are just portions of sram reserved for the non-secure
image and the bsd library, respectively. Thus we can remove the
compatible property from these nodes. We also make use of
'reserved-memory' to represent the different memory partitions
to be used by the nrf9160 builds.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
sram0 node is needed to hold the size of the
total, physical SRAM available on nRF9160 SoC.
We use sram0_s to represent the Secure image
SRAM for nRF9160_dk builds.
Signed-off-by: Håkon Øye Amundsen <haakon.amundsen@nordicsemi.no>
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We do not want sram0_shared to represent physical ram;
this is just a portion of sram reserved for shared memory
between Application and Network MCU. Therfore, we remove
the 'mmio' compatible property and transform this node to
a reserved-memory node definition, inside which we define
the sram0_shared node along with its reg property.
In addition we correct the documentation about the shared
memory, stressing that it is placed after the image RAM of
nrf5340 Application MCU (not after the secure SRAM).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We should not be using sram0 for image SRAM in nrf5340pdk.
sram0 represents the physical SRAM and that one includes the
shared memory between the two M33 CPUs on the SoC. We should
not be re-sizing sram0 to account for the shared RAM; instead
we would like to have sram0 representing the whole available
SRAM.
For that, we define a new memory node, sram0_image to
represent the 'image' SRAM that is available for Zephyr
on the board. sram0_image is the chosen image SRAM for
default builds, i.e. when TrustZone is ignored
(TRUSTED_EXECUTION_SECURE is not defined).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Move from a Kconfig to select/initialize the MAC address to using the
"local-mac-address" property in devicetree. If the property is set the
drivers will initialize the mac-address from the devicetree (unless the
mac address is all 0's). The MAC address might get overwritten by
either a driver specific means or by the setting of
"zephyr,random-mac-address" in the devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Utilize the devicetree property "zephyr,random-mac-address" to determine
if a driver should use a random mac address and remove the associated
Kconfig options that enabled this feature.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds support for TF-M to the MUSCA B1.
When the CONFIG_BUILD_WITH_TFM flag is set, a secure and
non-secure processing environment image pair will be
generated, with the Zephy application image running on
the non-secure side.
The secure and non-secure binary images will be signed
for use with the BL2 secure bootloader.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
This commit adds support for TF-M to the MPS2 AN521.
When the CONFIG_BUILD_WITH_TFM flag is set, a secure and
non-secure processing environment image pair will be
generated, with the Zephyr application image running on
the non-secure side.
The secure and non-secure binary images will be signed
for use with the BL2 secure bootloader.
An additional .hex file is also generated to enable
running QEMU with the AN521 binaries, `tfm_qemu.hex`,
which can be executed with the `-t run` option with
west, or `run` with ninja or make.
When configured for use with TF-M, the
`mps2_an521_nonsecure` board definition should be used.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
PSA level 1 requires secure boot. TF-M BL2 is the official
secure boot loader. It needs a BL2_HEADER_SIZE offset.
Align nonsecure address with TF-M's NS slot while TF-M BL2 enabled.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
Use DT_INST_SPI_DEV_HAS_CS_GPIOS() in drivers to determine if we should
utilize CS_GPIO base SPI chipselect handling. This allows us to remove
Kconfig option for this feature.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
For HPET devices, configure it with fixed delivery mode because HPET
timer interrupt is needed to fuel the scheduler for all CPUS.
For all other type of devices, like UART, I2C, GPIO, Ethernet, etc.
configure them as lowest priority delivery mode, in which IO APIC
delivers the interrupt to the processor core that is executing at the
lowest priority among all the processors listed in the specified
destination. In this case, the device drivers can avoid the trouble of
handling repeated interrupts delivered to all CPUS.
Signed-off-by: Zide Chen <zide.chen@intel.com>
Swap this out and make the status a parameter.
Leave a couple of cases of DT_NODE_HAS_COMPAT().
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
These are redundantly checking a node's status twice.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Usually, we want to operate only on "available" device
nodes ("available" means "status is okay and a matching binding is
found"), but that's not true in all cases.
Sometimes we want to operate on special nodes without matching
bindings, such as those describing memory.
To handle the distinction, change various additional devicetree APIs
making it clear that they operate only on available device nodes,
adjusting gen_defines and devicetree.h implementation details
accordingly:
- emit macros for all existing nodes in gen_defines.py, regardless
of status or matching binding
- rename DT_NUM_INST to DT_NUM_INST_STATUS_OKAY
- rename DT_NODE_HAS_COMPAT to DT_NODE_HAS_COMPAT_STATUS_OKAY
- rename DT_INST_FOREACH to DT_INST_FOREACH_STATUS_OKAY
- rename DT_ANY_INST_ON_BUS to DT_ANY_INST_ON_BUS_STATUS_OKAY
- rewrite DT_HAS_NODE_STATUS_OKAY in terms of a new DT_NODE_HAS_STATUS
- resurrect DT_HAS_NODE in the form of DT_NODE_EXISTS
- remove DT_COMPAT_ON_BUS as a public API
- use the new default_prop_types edtlib parameter
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
With the new RI-2018.0 XCC, xt-gdb complains about not being able
to find register f0. Turns out that xt-gdb needs to be told which
file to look at (the file command) before a load command can be
issued. So swap these two commands in the load_elf.txt file.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Michael Hope
