In order to avoid pin configuration conflicts between peripherals,
add CONFIG_SERIAL flag to for each serial pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add an additional check for CONFIG_PWM to decide if pins associated with
LED are configured for GPIO or PWM.
Fixes#25337
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This makes the up_squared board default to x86_64.
This also adds a new board, up_squared_32, for when 32-bit
is desired.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Given that the UP Squared has relatively large memory, the default
number of pages allocated for page tables are not enough, and
resulting in asserting in the page table initialization code.
So change the number of pages to a large number to accomodate
various applications.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The APIC timer is not supported e.g. with SMP (which will be enabled
by default soon as well) so the sensible choice is to default to HPET.
Also, the default makes more sense to be on the SoC side, so move it
there from the board defaults.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Let the default value for SYS_CLOCK_HW_CYCLES_PER_SEC come from the
SoC instead. Furthermore, a default for HPET_TIMER didn't even make
sense since this timer doesn't do anything with the Kconfig value.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
OpenOCD currently uses a single-bank STM32 configuration for the
B_L072Z_LRWAN1 board. This causes flashing to fail when the firmware
image is larger than the first bank. Switch to the dual bank
configuration to make this work.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Enable icount mode for qemu_xtensa platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for hifive1 platform, The icount shift value is
selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_riscv64 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_riscv32 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_cortex_a53 platform, The icount shift
value is selectd based on cpu clock frequency of this platform.
The virtual cpu will execute one instruction every 2^shift ns of
virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_cortex_m3 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_cortex_m0 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_x86 platform, The icount shift value is
selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Remove the existing qemu icount configuration because icount mode
will be controlled by Kconfig QEMU_ICOUNT so that none suitable
cases(especially networking cases) can exclude icount configuration
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
The length field for the MCUBOOT slot partitions in Nordic platforms
has always had an extra leading zero suggesting it's a 40-bit value,
being stored in a 32-bit field. Remove the incorrect leading zero to
reduce misunderstanding of the field.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Several reviewers agreed that DT_HAS_NODE_STATUS_OKAY(...) was an
undesirable API for the following reasons:
- it's inconsistent with the rest of the DT_NODE_HAS_FOO names
- DT_NODE_HAS_FOO_BAR_BAZ(node) was agreed upon as a shorthand
for macros which are equivalent to
DT_NODE_HAS_FOO(node) && DT_NODE_HAS_BAR(node) &&
- DT_NODE_HAS_BAZ(node), and DT_HAS_NODE_STATUS_OKAY is an odd duck
- DT_NODE_HAS_STATUS(..., okay) was viewed as more readable anyway
- it is seen as a somewhat aesthetically challenged name
Replace all users with DT_NODE_HAS_STATUS(..., okay), which is
semantically equivalent.
This is mostly done with sed, but a few remaining cases were done by
hand, along with whitespace, docs, and comment changes. These special
cases include the Nordic SOC static assert files.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
When we build Zephyr as Secure image on nRF340 Application
MCU and nRF9160 SoC we would like to pass the information
about the reserved memory area allocated to the Non-Secure
images. The information may be needed to apply proper
security configuration. We add a "chosen" node in board .dts
file for this purpose.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We do not want sram0_ns and sram0_bsd to represent physical
ram; these are just portions of sram reserved for the non-secure
image and the bsd library, respectively. Thus we can remove the
compatible property from these nodes. We also make use of
'reserved-memory' to represent the different memory partitions
to be used by the nrf9160 builds.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
sram0 node is needed to hold the size of the
total, physical SRAM available on nRF9160 SoC.
We use sram0_s to represent the Secure image
SRAM for nRF9160_dk builds.
Signed-off-by: Håkon Øye Amundsen <haakon.amundsen@nordicsemi.no>
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We do not want sram0_shared to represent physical ram;
this is just a portion of sram reserved for shared memory
between Application and Network MCU. Therfore, we remove
the 'mmio' compatible property and transform this node to
a reserved-memory node definition, inside which we define
the sram0_shared node along with its reg property.
In addition we correct the documentation about the shared
memory, stressing that it is placed after the image RAM of
nrf5340 Application MCU (not after the secure SRAM).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We should not be using sram0 for image SRAM in nrf5340pdk.
sram0 represents the physical SRAM and that one includes the
shared memory between the two M33 CPUs on the SoC. We should
not be re-sizing sram0 to account for the shared RAM; instead
we would like to have sram0 representing the whole available
SRAM.
For that, we define a new memory node, sram0_image to
represent the 'image' SRAM that is available for Zephyr
on the board. sram0_image is the chosen image SRAM for
default builds, i.e. when TrustZone is ignored
(TRUSTED_EXECUTION_SECURE is not defined).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Move from a Kconfig to select/initialize the MAC address to using the
"local-mac-address" property in devicetree. If the property is set the
drivers will initialize the mac-address from the devicetree (unless the
mac address is all 0's). The MAC address might get overwritten by
either a driver specific means or by the setting of
"zephyr,random-mac-address" in the devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Utilize the devicetree property "zephyr,random-mac-address" to determine
if a driver should use a random mac address and remove the associated
Kconfig options that enabled this feature.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds support for TF-M to the MUSCA B1.
When the CONFIG_BUILD_WITH_TFM flag is set, a secure and
non-secure processing environment image pair will be
generated, with the Zephy application image running on
the non-secure side.
The secure and non-secure binary images will be signed
for use with the BL2 secure bootloader.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
This commit adds support for TF-M to the MPS2 AN521.
When the CONFIG_BUILD_WITH_TFM flag is set, a secure and
non-secure processing environment image pair will be
generated, with the Zephyr application image running on
the non-secure side.
The secure and non-secure binary images will be signed
for use with the BL2 secure bootloader.
An additional .hex file is also generated to enable
running QEMU with the AN521 binaries, `tfm_qemu.hex`,
which can be executed with the `-t run` option with
west, or `run` with ninja or make.
When configured for use with TF-M, the
`mps2_an521_nonsecure` board definition should be used.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
PSA level 1 requires secure boot. TF-M BL2 is the official
secure boot loader. It needs a BL2_HEADER_SIZE offset.
Align nonsecure address with TF-M's NS slot while TF-M BL2 enabled.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
Use DT_INST_SPI_DEV_HAS_CS_GPIOS() in drivers to determine if we should
utilize CS_GPIO base SPI chipselect handling. This allows us to remove
Kconfig option for this feature.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
For HPET devices, configure it with fixed delivery mode because HPET
timer interrupt is needed to fuel the scheduler for all CPUS.
For all other type of devices, like UART, I2C, GPIO, Ethernet, etc.
configure them as lowest priority delivery mode, in which IO APIC
delivers the interrupt to the processor core that is executing at the
lowest priority among all the processors listed in the specified
destination. In this case, the device drivers can avoid the trouble of
handling repeated interrupts delivered to all CPUS.
Signed-off-by: Zide Chen <zide.chen@intel.com>
Swap this out and make the status a parameter.
Leave a couple of cases of DT_NODE_HAS_COMPAT().
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
These are redundantly checking a node's status twice.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Usually, we want to operate only on "available" device
nodes ("available" means "status is okay and a matching binding is
found"), but that's not true in all cases.
Sometimes we want to operate on special nodes without matching
bindings, such as those describing memory.
To handle the distinction, change various additional devicetree APIs
making it clear that they operate only on available device nodes,
adjusting gen_defines and devicetree.h implementation details
accordingly:
- emit macros for all existing nodes in gen_defines.py, regardless
of status or matching binding
- rename DT_NUM_INST to DT_NUM_INST_STATUS_OKAY
- rename DT_NODE_HAS_COMPAT to DT_NODE_HAS_COMPAT_STATUS_OKAY
- rename DT_INST_FOREACH to DT_INST_FOREACH_STATUS_OKAY
- rename DT_ANY_INST_ON_BUS to DT_ANY_INST_ON_BUS_STATUS_OKAY
- rewrite DT_HAS_NODE_STATUS_OKAY in terms of a new DT_NODE_HAS_STATUS
- resurrect DT_HAS_NODE in the form of DT_NODE_EXISTS
- remove DT_COMPAT_ON_BUS as a public API
- use the new default_prop_types edtlib parameter
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
With the new RI-2018.0 XCC, xt-gdb complains about not being able
to find register f0. Turns out that xt-gdb needs to be told which
file to look at (the file command) before a load command can be
issued. So swap these two commands in the load_elf.txt file.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit adds support for nRF52820 development on nRF52833DK.
Changes afffects:
- Introduce files related to board description.
- Add blank documentation file (for future update).
- configuration files for build process.
Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
Changes:
- Added all required board files in /boards/arm/96b_aerocore2
- Modified pinmux for stm32f4
Most of the changes in this PR is based on reverse-engineering of the
PCB layout and following commits in the PX4 firmware repository for
the same board. The manufacturer does not provide and or generate
schematics and pinout tables for this board.
This PR includes almost all of the interfaces connected to the STM32
MCU, the only thing not included is the J9 and J8 headers that connect
to a 96Boards baseboard.
These headers are not vital to the functionality of the Aerocore2.
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
The SAM V71 SoC configuration currently selects the `ARM_MPU` symbol
and this effectively forces MPU usage on the SoC.
This commit removes `ARM_MPU` selection from the SoC Kconfig since it
is intended to be selected by a board, and the `CPU_HAS_ARM_MPU` symbol
already indicates that the SoC supports ARM MPU.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The SAM E70 SoC configuration currently selects the `ARM_MPU` symbol
and this effectively forces MPU usage on the SoC.
This commit removes `ARM_MPU` selection from the SoC Kconfig since it
is intended to be selected by a board, and the `CPU_HAS_ARM_MPU` symbol
already indicates that the SoC supports ARM MPU.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Update dtsi and pinmux macros for stm32f7 family. Add sdmmc1 to dts file
for stm32f746g_disco. Also add board specific configuration file for
fat_fs sample.
Signed-off-by: Helge Juul <helge@fastmail.com>
Update the dtsi for stm32l471 (which the higher SoCs are based on) to
support the stm32-sdmmc disk access device. Enable the device for the
stm32l496g_disco board, and update the pinmuxing.
Note that the stm32l496g_disco board also has a card detect gpio
(MFX_GPIO8), but this is not supported yet. When not specified the
driver will assume a card is present.
Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com>
Use MSI as PLL source. This enables to run system clock at 110MHz.
To achieve this, voltage regulator should be set to scale 0.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Map lpcxpresso55xxx type boards entropy device to rng peripheral.
Apllies to all versions of lpcxpress55s69 and lpcxpresso55s16.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Given that the Minnowboard has relatively large memory, the default
number of pages allocated for page tables are not enough, and
resulting in asserting in the page table initialization code.
So change the number of pages to a large number to accomodate
various applications.
Fixes#24353
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Convert i2s_sam_ssc driver to utilize devicetree. We replace Kconfig
options for specifying the DMA configuration (channel, DMA device name)
with getting that from devicetree. We also get pincfg from devicetree,
however we still have Kconfig sybmols to specify if the RF or RK pin is
enabled.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The Gen3 (formerly "mesh") Particle product line has a header that is
structurally related to the Adafruit Feather, and is generally
compatible with Featherwing shields. Provide nexus maps for both the
native header layout, and for the subset feather header layout, and
add alias labels for the peripherals that would be referenced from
shield overlays.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The LoRa shell and samples need a way to find the default LoRa
radio. Add the DT alias 'lora0' for the default radio.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Refactors the fat_fs sample yaml to depend on a feature rather than
whitelisting specific boards. This implicitly extends the sample to
mimxrt10{60,64}_evk boards, since they already support the feature.
The only whitelist board remaining is the nrf52840_blip, which requires
a device tree overlay for this sample.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Enables sdhc on the mimxrt1064_evk board. Configures pinmuxes and device
tree, and updates board documentation accordingly.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Enables sdhc on the mimxrt1060_evk board. Configures pinmuxes and device
tree, and updates board documentation accordingly.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
As we phase out per instance Kconfig symbols convert to utilize
DT_DRV_INST to initialize CAN instances.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As we phase out per instance Kconfig symbols convert to utilize
DT_DRV_INST to initialize CAN instances.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Clean up as we wish to move away from using these Kconfig settings.
Also removing them from the boards' default config.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
ARC_MPU_VER 2 has a strong requirement in
* size, must be >= 2048 bytes and power of 2
* start address must be aligned to size
It may bring a big waste of memory.
On the other hand, GEN_PRIV_STACK is used for ARC_MPU_VER 2,
it conflicts with MPU_STACK_GUARD.
So considering the limmitations, remove MPU_STACK_GUARD for
ARC_MPU_VER 2
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Fix node status to "okay" instead of "ok" which doesn't
seem to be in used anymore across the tree.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Once the TPM driver and the required configs have been added,
now this patch enables the usage of the PWM framework on KW41Z
SoCs. As such, the DTS gets the proper nodes and the pinmuxing
is done according to the configuration requested.
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Allow to flash either Cortex M4 or M7 with OpenOCD
(depending on which Board/Core has been compiled)
Command: west flash
Warning: Dependency with recent OpenOCD patch:
Windows: https://gnutoolchains.com/arm-eabi/openocd/
version 20200408
Linux : http://openocd.zylin.com/
SHA1: 0a804222da63c5f849efa23b019a59e2dea76842
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
The Kconfig I2C_[0-9] sybmols don't have any meaning for the majority of
SoCs. The drivers doesn't utilize them and no sample or test code does
either so we can remove setting them in board Kconfig.defconfig files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
* Define USB driver for base stm32wb device.
* Enable USB for the nucleo_wb55rg board.
* Properly initialize USB power + clock for the platform.
Signed-off-by: Pete Johanson <peter@peterjohanson.com>
x-nucleo-iks02a1 shield is an arduino compatible companion board
which can be used on top of Nucleo standard boards for industrial
applications. It extends the Nucleo functionalities adding following
MEMS sensor support:
- ISM330DHCX 3-axis accelerometer and 3-axis gyroscope
- IIS2MDC 3-axis magnetometer
- IIS2DLPC 3-axis accelerometer
- IMP34DT05 digital microphone.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Enable I2S_STM32 in the soc common part, so it will no
longer be required in board default configuration.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Rename a few cases of DT_HAS_NODE to DT_HAS_NODE_STATUS_OKAY that snuck
in after the initial global change.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rename DT_HAS_NODE to DT_HAS_NODE_STATUS_OKAY so the semantics are
clear. As going forward DT_HAS_NODE will report if a NODE exists
regardless of its status.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds the asynchronous UART API testing support on the SAM
E54 Xplained Pro board.
The SERCOM1 module is used as the secondary loop-back UART, which is
required to run this test.
Note that no external UART loop-back connection is necessary to run
this test, because the SERCOM1 UART TX and RX pads are configured to be
internally connected; it is, however, still necessary to configure the
pinmux because the module pads are not connected until the pinmux is
configured.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Following other drivers, Kconfig based instances are now entirely
removed. In order to do this change, PWM nodes in board DT files have
been given a pwm{N} label so that both:
- DT API checks such as #if DT_HAS_NODE(DT_NODELABEL(pwmN)) can be
used (N being PWM instance number).
- DT references can be written as pwms = <&pwmN x y>; instead of
pwms = <&{/soc/timers@XXXXXXXX/pwm} x y>;
This approach is also used on the Linux Kernel.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
For auto doc generation purpose, get name value of boards' yaml files
in sync with name provided as board name in .rst file
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The Kconfig PWM_[0-3] sybmols don't have any meaning for kinetis family
SoCs. The driver doesn't utilize them and no sample or test code does
either so we can remove setting them in board Kconfig.defconfig files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The Kconfig PWM_[0-3] sybmols don't have any meaning for nrf family of
SoCs. The driver doesn't utilize them and no sample or test code does
either so we can remove setting them in board Kconfig.defconfig files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds the `i2c-0` alias for the Atmel SAM R21 Xplained Pro
board, as required by the I2C test.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds the `i2c-0` alias for the Atmel SAM E54 Xplained Pro
board, as required by the I2C test.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit configures the SERCOM2 peripheral to I2C mode for the Atmel
SAM D21 Xplained Pro board.
Note that the SERCOM2 on PA08/PA09 is the I2C peripheral/pin designated
by the board user guide.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit configures the SERCOM2 peripheral to I2C mode for the Atmel
SAM D20 Xplained Pro board.
Note that the SERCOM2 on PA08/PA09 is the I2C peripheral/pin designated
by the board user guide.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Remove the USART 2 definition from the nucleo_g474re board
as it could cause a pin conflict on LPUART1 TX pin (PA2).
The USART2 is not present on this nucleo hardware and then
the g474re board definition is aligned with the nucleo_g431rb.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The OpenOCD JTAG reset causes the SAM E54 SoC to prematurely start code
execution before the SoC is ready, and this causes hard faults when the
MPU is enabled -- causing OpenOCD to hang.
This commit disables the JTAG SRST reset mechanism and falls back to
using the Cortex-M SYSRESETREQ emulation reset mechanism, which does
not have experience this issue.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit enables the ARM memory protection unit for the SAM D54
Xplained Pro board, since `CPU_HAS_ARM_MPU` is now selected by the SoC
Kconfig.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit enables the QEMU icount mode for `mps2_an521`, in order to
decouple the host clock from the emulated guest clock.
This prevents guest timing instability from causing test failures when
the host CPU load is very high.
The icount `shift` value of 7 was empirically chosen to allow the tests
to complete in both realistic and reasonable amount of time.
The following are quick notes on the parameters used:
* -icount shift=7: Execute one instruction every 128ns of virtual time
* -icount align=off: Do not synchronise the host and guest clocks
* -icount sleep=off: Advance virtual time without sleeping/waiting
* -rtc clock=vm: Isolate the guest RTC time from the host
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
native_posix supports for some time now generating a 64bit
binary with the native_posix_64 target, but we never got
to document it.
Add a section describing it, and correct the WSL1
note/warning (also with a link with instructions on how to hack
WSL1 to make it run 32 bit binaries)
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Options summary:
-icount shift=5: Execute one instruction every 32ns of virtual time
-icount align=off: Do not synchronise the host and guest clocks
-icount sleep=off: Advance virtual time without sleeping/waiting
-rtc clock=vm: Isolate the guest RTC time from the host
64-bit still has some issues that are being looked at.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
For autogeneration on board pages and indexes, consistency in naming is
required, few board names did not match the images of the boards.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Removing this flag allows to find the spi binary generation tool
in cmake's default paths. This also aligns this CMakeList with
the version currently found in the MEC EVB
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
Add board definition for the NXP LPCXpresso55S16 development
board. Only non-secure (ns) access is supported for now.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Kukui has two I2C ports with various peripherals including a battery
charger and a TCPCi-compatible port controller
Enable I2C so that these can be used. No drivers are provided so far.
Also update the GPIO documentation while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Remove dts_fixup.h files that are not used (empty) or the defines aren't
used anymore and thus can be removed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert linker scripts and arc_mpu_regions.c setup to use new
devicetree.h macros to extract the base address and size of the various
memory regions (DDR, SRAM, FLASH, DCCM, ICCM). We also remove the
scaling up and down since DT_REG_SIZE() returns the value in bytes.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Do not assume in the SoC level device trees that NXP Kinetis FlexTimer
nodes will always be configured as PWM. Instead, configure FlexTimer
nodes for PWM at the board level for NXP Kinetis boards.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add ESP-8266 modules shield. The ESP-01 needs to be loaded with
ESP8266 AT Bin V1.6.2 which is compatible with ESP8266 AT Bin
V1.7.x which is the minimal supported version by ESP WIFI driver.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The board efr32_radio_brd4250b replaces this removed board. This
commit removes this duplication.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
The HTML documentation generation does not work properly if
we try to put more than one board into same directory. So rename
the directory to reflect this.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
This commit enables the QEMU icount mode for `mps2_an385`, in order to
decouple the host clock from the emulated guest clock.
This prevents guest timing instability from causing test failures when
the host CPU load is very high.
The icount `shift` value of 7 was empirically chosen to allow the tests
to complete in both realistic and reasonable amount of time.
The following are quick notes on the parameters used:
* -icount shift=7: Execute one instruction every 128ns of virtual time
* -icount align=off: Do not synchronise the host and guest clocks
* -icount sleep=off: Advance virtual time without sleeping/waiting
* -rtc clock=vm: Isolate the guest RTC time from the host
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Convert CAN to use a chosen node property that is similar to how we
handle zephyr,entroy or zephyr,flash-controller as the means to select a
specific peripheral instance utilized by a subsystem.
Replace references of the form:
alias {
can-primary = &can1;
};
with:
chosen {
zephyr,can-primary = &can1;
};
Replace various macro/define references with either
DT_CHOSEN(zephyr_can_primary) or replace DT_ALIAS_CAN_PRIMARY_LABEL
with DT_CHOSEN_ZEPHYR_CAN_PRIMARY_LABEL.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rework the atom/linker.ld to match how ia32/linker.ld works with regards
to how PHYS_LOAD_ADDR & PHYS_RAM_ADDR are set based on CONFIG_XIP and
from which DT_PHYS_{RAM,LOAD}_ADDR defines. We update the minnowboard
dts and atom.dtsi files to keep in sync with this.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The SoC node has compatibles for the specific SoC in place, having the
same compatible at the top level is technically a conflict and the
top-level one should really just be about the board. Remove the SoC
related compatibles at the top-level.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert old style ifdef(DT_NS16550_400F2400_BASE_ADDRESS) to
if DT_HAS_NODE(DT_NODELABEL(uart0)) to decide to config pins for UART0
and similarly for UART1.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use new DT_INST macros throughout. Removed per
instance Kconfig symbols and replaced with DT_NODELABEL references
where needed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use new DT_INST macros throughout. Removed per
instance Kconfig symbols and replaced with DT_NODELABEL references
where needed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replace use of CAN_X Kconfig symbols by access to dt instances
Control of enabled instances is now done using dts nodes status
field ('okay'/'disabled'). For boards supporting only can2,
can1 instance is disabled.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Update STM32WB HCI lib support to version 1.5.0.
Additionally provide a doc section to clarify compatibility
with stm32wb wireless co-processor binaries.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Convert driver to use the new device tree macro's instead of
dts_fixup.h based macros. This moves us closer to removing both
dts_fixup.h and per instance Kconfig symbols.
The pinmux_mchp_xec is also being updated since it's using DT
from GPIO.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Convert driver to use the new device tree macro's instead of
dts_fixup.h based macros. This moves us closer to removing both
dts_fixup.h and per instance Kconfig symbols.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Convert driver to use instance macro's instead of dts_fixup.h based
macros. This moves us closer to removing both dts_fixup.h and per
instance Kconfig symbols.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Pinmux needs to be set for UART_2 if it is enabled. So use
the new DT macro to refer to the DT node.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Pinmux needs to be set for UART_2 if it is enabled. So use
the new DT macro to refer to the DT node.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Replace DT_FLASH_DEV_NAME with DT_CHOSEN_ZEPHYR_FLASH_CONTROLLER_LABEL.
We now set zephyr,flash-controller in the chosen node of the device
tree to the flash controller device.
NOTE: For a SoCs with on die flash, this points to the controller and
not the 'soc-nv-flash' node. Typically the controller is the
parent of the 'soc-nv-flash' node).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit renames the Kconfig `FLOAT` symbol to `FPU`, since this
symbol only indicates that the hardware Floating Point Unit (FPU) is
used and does not imply and/or indicate the general availability of
toolchain-level floating point support (i.e. this symbol is not
selected when building for an FPU-less platform that supports floating
point operations through the toolchain-provided software floating point
library).
Moreover, given that the symbol that indicates the availability of FPU
is named `CPU_HAS_FPU`, it only makes sense to use "FPU" in the name of
the symbol that enables the FPU.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Use DT_INST_FOREACH macro to combine code used for multiple instances.
Remove unnecessary Kconfig options and dts fixups for GPIO instances.
A side-effect to using DT_INST_FOREACH is that GPIO ports A0 and A3
are now enabled, whereas they were originally disabled by default as
an optimization.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Reworked spi_sam driver to utilize new DT_INST macros as part of
this rework we also now get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from dts_fixup.h and soc_pinmap.h and associated
Kconfig symbols that are no longer needed due to getting all that
information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit enables the ARM memory protection unit for the SAM 4S
Xplained board, since the `CPU_HAS_ARM_MPU` is now selected by the SoC
Kconfig.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit enables the ARM memory protection unit for the SAM 4E
Xplained Pro board, since the `CPU_HAS_ARM_MPU` is now selected by the
SoC Kconfig.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Sort the supported lists alphabetically for some boards. I'm not
trying to do this for all boards, just some DKs I'm using for testing.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Tests were failing as they were looking for an alias which didn't exist
Also, because some code in kscan_handlers.c wasn't compilable
Signed-off-by: Mark Olsson <mark@markolsson.se>
Changes dependency for I2C so that it's enabled if kscan is enabled.
This is to allow the kscan_ft5336 sample to run.
Note: LVGL has KSCAN as a dependency.
Applies to the mimxrt10{50,60,64}_evk boards.
Signed-off-by: Mark Olsson <mark@markolsson.se>
Adds device tree nodes, pinmux definitions and configures Kconfig
defaults for the ft5336 touch panel driver on the
stm32f746g_disco board.
Signed-off-by: Mark Olsson <mark@markolsson.se>
Adding port information for uart tx and rx pins in dts, so that it can
be more systematically retrieved in the uart driver.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Convert driver to use DT_INST_ defines. As part of this conversion we
remove the Kconfig options for per GPIO controller enables and instead
get that information from device tree. This means we now disable each
GPIO controller by default in the DTS and have each board dts enable the
GPIO controller ports it needs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds the asynchronous UART API testing support on the SAM
R21 Xplained Pro board.
The SERCOM3 module is used as the secondary loop-back UART, which is
required to run this test.
Note that no external UART loop-back connection is necessary to run
this test, because the SERCOM3 UART TX and RX pads are configured to be
internally connected; it is, however, still necessary to configure the
pinmux because the module pads are not connected until the pinmux is
configured.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Replace DT_ALIAS_GPIO_x_LABEL with DT_NODELABEL references to get the
device name for the gpio ports.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Adding support for nRF9160 based InnBlue board V2.1. Supports both
Secure and Non-Secure configurations along with various sensors
(lis2dh12 / hts221) and devices(i2c / pwm).
Signed-off-by: Bilal Wasim <bilalwasim676@gmail.com>
Move the FPGA GPIO init to use the devicetree.h macros instead of
dts_fixup.h. This allows us to remove dts_fixup.h on mps2 based
platforms.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
SPI1, which is used by the LoRa radio, has the following
configuration:
SCK: PB_3
MISO: PA_6
MOSI: PA_7
NSS: PA_15
Update the pinmux configuration and documentation to reflect this.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Convert old DT defines of the form DT_ARM_SCC_BASE_ADDRESS to
DT_REG_ADDR(DT_INST(0, arm_scc)). This allows us to remove dts_fixup.h
on musca boards.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In conversion of nodelabels to match SoC docs, we missed a case in the
board dts files. However these delete-node commands are not needed as
we normally handle this via the 'status' property being disabled which
enet2 is by default in the SoC dtsi files. So we can safely just remove
the stale /delete-node/ eth1 lines.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Adding support for nRF9160 based InnBlue board V2.2. Supports both
Secure and Non-Secure configurations along with various sensors
(lis2dh12 / hts221) and devices(i2c / pwm).
Signed-off-by: Bilal Wasim <bilalwasim676@gmail.com>
Set the default value of SYS_PM_MIN_RESIDENCY_SLEEP_1 and
SYS_PM_MIN_RESIDENCY_SLEEP_2 to something more reasonable for these
platforms, as the latency of entering/exiting these sleep modes
is low.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
The nvs sample requires a storage_partition of 3 flash pages, but these
boards only provided 2 flash pages. Because of this the nvs sample
failed.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
Add script signing and flashing up_squared_adsp board. Can be used:
$ west flash \
<zephyr>/boards/xtensa/up_squared_adsp/tools/up_squared_adsp_flash.sh
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Reworked i2c_sam_twi driver to utilize new DT_INST macros as part of
this rework we also now get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from dts_fixup.h and soc_pinmap.h and associated
Kconfig symbols that are no longer needed due to getting all that
information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Reworked i2c_sam_twi driver to utilize new DT_INST macros as part of
this rework we also now get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from dts_fixup.h and soc_pinmap.h and associated
Kconfig symbols that are no longer needed due to getting all that
information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Given that nsim_em can run the tests instead of just building them as
with em_starterkit_em7d, make it a default platform instead of
em_starterkit_em7d to get most of the testing when nsim simulator is
installed on the developer machine.
Tests run are 1000x more useful than just building them, even if we do
not have a large installed base of nsim.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Update documentation about IC variations. Now SoC supports both
variations A and B and this board is compatible with both.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Update documentation about IC variations. Now SoC supports both
variations A and B and this board is compatible with both.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Convert driver to use new DT_INST macros throughout. Removed per
instance Kconfig symbols and replaced with DT_NODELABEL references
where needed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replace use of Kconfig UART_X symbols by calls to DT API.
Clean driver from symbols definitions
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Convert driver to use DT_INST macros and remove related board per
instance Kconfig symbol usage. We also remove dts_fixup.h defines that
are no longer needed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Mark all the individual PWMs as disabled in dts and enable the one
explicitly used on the mimxrt1064_evk.dts in the board dts file.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As prep for drivers being converted to utilize DT_INST and removal of
per instance Kconfig symbols, move board pinmux.c code to utilize
DT_NODELABEL instead.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Have nodelabels match the SoC docs so when a nodelabel reference is
made in the code its easier to relate to the SoC.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Change the board defconfig to use the provided 24MHz Crystal instead
of the internal resonator.
This improves the clock precision and stability.
Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
Change the board defconfig to use the provided 24MHz Crystal instead
of the internal resonator.
This improves the clock precision and stability.
Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
Now the ARC SecureShield related features are experimental. The ARC
normal application cannot run alone, need the secure service example to
initialize the context and boot.
Here move ARC normal related configurations out of board dir to
avoid the impact of CI test and the confusion to users.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Reworked usart_sam driver to utilize new DT_INST macros as part of
this rework we also now get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from dts_fixup.h and soc_pinmap.h and associated
Kconfig symbols that are no longer needed due to getting all that
information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Reworked uart_sam driver to utilize new DT_INST macros as part of this
rework we also now get pin ctrl/mux configuration information from the
device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from dts_fixup.h and soc_pinmap.h and associated
Kconfig symbols that are no longer needed due to getting all that
information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The return value of the interrupt is never used, so remove the
functionality from the API. We ripple this change into the
ARCH_IRQ_CONNECT and ARCH_IRQ_DIRECT_CONNECT implementations. With
this change we can also remove the compound expression as that is
not needed anymore.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As prep for drivers being converted to utilize DT_INST and removal of
per instance Kconfig symbols, move board pinmux.c code to utilize
DT_NODELABEL instead.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As prep for drivers being converted to utilize DT_INST and removal of
per instance Kconfig symbols, move board pinmux.c code to utilize
DT_NODELABEL instead.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Have nodelabels match the SoC docs so when a nodelabel reference is
made in the code its easier to relate to the SoC.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Have nodelabels match the SoC docs so when a nodelabel reference is
made in the code its easier to relate to the SoC.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Have nodelabels match the SoC docs so when a nodelabel reference is
made in the code its easier to relate to the SoC.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Have nodelabels match the SoC docs so when a nodelabel reference is
made in the code its easier to relate to the SoC.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Have nodelabels match the SoC docs so when a nodelabel reference is
made in the code its easier to relate to the SoC.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We don't need to define DT_NUM_IRQ_PRIO_BITS or DT_NUM_MPU_REGIONS in
dts_fixup.h files anymore, so we can remove them.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The documentation references now out-dated links to websites for
board landing page, and firmware download and instructions. This
commit updates the links and adds a link to the latest firmware
development for reference.
Fixes#24325
Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
This commit enables the GMAC Ethernet support for the `atsame54_xpro`
board which includes an on-board RMII PHY.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
In order to use its serial peripheral SERCOMs SAMD socs require their
pins to be configured with pinmux. Currently pins are muxed only for the
boards' default serial interfaces. The pinmux code is written to throw
a compiler error if a user tries to use any sercom in a way it wasn't
pre-defined to be used.
This commit changes compiler errors to warnings so that user can provide
custom pinmuxing code in their app.
Fixes#23133
Signed-off-by: Kuba Sanak <contact@kuba.fyi>
This commit enables the newly added GMAC instance in the `sam4e_xpro`
device tree.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This enable GMAC driver by default if the end application selects
NETWORKING. The driver will set MII interface since is the only one
available for SAM4E and will select a random MAC value.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This patch adds the selection of the necessary CONFIG_*
options for allowing the use of privacy on VEGA platform
Signed-off-by: Jeanina Dragusin <ancajeanina.dragusin@nxp.com>
The radio on the VEGA platform will now be able to resolve Resolvable
Private Addresses through the use of the CAUv3 hardware. With this
patch the RPA feature is now fully supported on the Controller:
RPA addresses are generated with local IRK and resolved with
previously exchanged peer IRK.
Signed-off-by: Jeanina Dragusin <ancajeanina.dragusin@nxp.com>
This board contains an on-board Winbond W25Q16.
The chip is connected to spi1 using PB3-PB5 and PB0 as CS.
Signed-off-by: Bjarne Steinsbo <bjarne@gmail.com>
While the Cortex-R arch port does not currently support memory
protection and userspace, the `memory_protection` and `userspace` test
tags should not be ignored because doing so can unintentionally disable
other relevant tests.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Following conversion of stm32 i2c driver to use of DT_NODELABEL
macros, configuration of i2c instance in stm32 boards should
no more be done thanks to Kconfig symbols, but is done thanks
to device tree file.
Clean boards files from these symbols.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This adds the support of openocd for nucleo board stm32g474re
It requires the openocd that supports stm32G4xx
(zephyrproject-rtos/openocd#24)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This adds the support of openocd for nucleo board stm32g431rb
It Requires the openocd that supports stm32G4xx
(zephyrproject-rtos/openocd#24)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This adds the support of openocd for nucleo board stm32g071rb
It requires the openocd that supports stm32G0xx
(zephyrproject-rtos/openocd#24)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
