In order to avoid pin configuration conflicts between peripherals,
add CONFIG_SERIAL flag to for each serial pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add an additional check for CONFIG_PWM to decide if pins associated with
LED are configured for GPIO or PWM.
Fixes#25337
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This makes the up_squared board default to x86_64.
This also adds a new board, up_squared_32, for when 32-bit
is desired.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Given that the UP Squared has relatively large memory, the default
number of pages allocated for page tables are not enough, and
resulting in asserting in the page table initialization code.
So change the number of pages to a large number to accomodate
various applications.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The APIC timer is not supported e.g. with SMP (which will be enabled
by default soon as well) so the sensible choice is to default to HPET.
Also, the default makes more sense to be on the SoC side, so move it
there from the board defaults.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Let the default value for SYS_CLOCK_HW_CYCLES_PER_SEC come from the
SoC instead. Furthermore, a default for HPET_TIMER didn't even make
sense since this timer doesn't do anything with the Kconfig value.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
OpenOCD currently uses a single-bank STM32 configuration for the
B_L072Z_LRWAN1 board. This causes flashing to fail when the firmware
image is larger than the first bank. Switch to the dual bank
configuration to make this work.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Enable icount mode for qemu_xtensa platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for hifive1 platform, The icount shift value is
selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_riscv64 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_riscv32 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_cortex_a53 platform, The icount shift
value is selectd based on cpu clock frequency of this platform.
The virtual cpu will execute one instruction every 2^shift ns of
virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_cortex_m3 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_cortex_m0 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_x86 platform, The icount shift value is
selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Remove the existing qemu icount configuration because icount mode
will be controlled by Kconfig QEMU_ICOUNT so that none suitable
cases(especially networking cases) can exclude icount configuration
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
The length field for the MCUBOOT slot partitions in Nordic platforms
has always had an extra leading zero suggesting it's a 40-bit value,
being stored in a 32-bit field. Remove the incorrect leading zero to
reduce misunderstanding of the field.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Several reviewers agreed that DT_HAS_NODE_STATUS_OKAY(...) was an
undesirable API for the following reasons:
- it's inconsistent with the rest of the DT_NODE_HAS_FOO names
- DT_NODE_HAS_FOO_BAR_BAZ(node) was agreed upon as a shorthand
for macros which are equivalent to
DT_NODE_HAS_FOO(node) && DT_NODE_HAS_BAR(node) &&
- DT_NODE_HAS_BAZ(node), and DT_HAS_NODE_STATUS_OKAY is an odd duck
- DT_NODE_HAS_STATUS(..., okay) was viewed as more readable anyway
- it is seen as a somewhat aesthetically challenged name
Replace all users with DT_NODE_HAS_STATUS(..., okay), which is
semantically equivalent.
This is mostly done with sed, but a few remaining cases were done by
hand, along with whitespace, docs, and comment changes. These special
cases include the Nordic SOC static assert files.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
When we build Zephyr as Secure image on nRF340 Application
MCU and nRF9160 SoC we would like to pass the information
about the reserved memory area allocated to the Non-Secure
images. The information may be needed to apply proper
security configuration. We add a "chosen" node in board .dts
file for this purpose.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We do not want sram0_ns and sram0_bsd to represent physical
ram; these are just portions of sram reserved for the non-secure
image and the bsd library, respectively. Thus we can remove the
compatible property from these nodes. We also make use of
'reserved-memory' to represent the different memory partitions
to be used by the nrf9160 builds.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
sram0 node is needed to hold the size of the
total, physical SRAM available on nRF9160 SoC.
We use sram0_s to represent the Secure image
SRAM for nRF9160_dk builds.
Signed-off-by: Håkon Øye Amundsen <haakon.amundsen@nordicsemi.no>
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We do not want sram0_shared to represent physical ram;
this is just a portion of sram reserved for shared memory
between Application and Network MCU. Therfore, we remove
the 'mmio' compatible property and transform this node to
a reserved-memory node definition, inside which we define
the sram0_shared node along with its reg property.
In addition we correct the documentation about the shared
memory, stressing that it is placed after the image RAM of
nrf5340 Application MCU (not after the secure SRAM).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We should not be using sram0 for image SRAM in nrf5340pdk.
sram0 represents the physical SRAM and that one includes the
shared memory between the two M33 CPUs on the SoC. We should
not be re-sizing sram0 to account for the shared RAM; instead
we would like to have sram0 representing the whole available
SRAM.
For that, we define a new memory node, sram0_image to
represent the 'image' SRAM that is available for Zephyr
on the board. sram0_image is the chosen image SRAM for
default builds, i.e. when TrustZone is ignored
(TRUSTED_EXECUTION_SECURE is not defined).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Move from a Kconfig to select/initialize the MAC address to using the
"local-mac-address" property in devicetree. If the property is set the
drivers will initialize the mac-address from the devicetree (unless the
mac address is all 0's). The MAC address might get overwritten by
either a driver specific means or by the setting of
"zephyr,random-mac-address" in the devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Utilize the devicetree property "zephyr,random-mac-address" to determine
if a driver should use a random mac address and remove the associated
Kconfig options that enabled this feature.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds support for TF-M to the MUSCA B1.
When the CONFIG_BUILD_WITH_TFM flag is set, a secure and
non-secure processing environment image pair will be
generated, with the Zephy application image running on
the non-secure side.
The secure and non-secure binary images will be signed
for use with the BL2 secure bootloader.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
This commit adds support for TF-M to the MPS2 AN521.
When the CONFIG_BUILD_WITH_TFM flag is set, a secure and
non-secure processing environment image pair will be
generated, with the Zephyr application image running on
the non-secure side.
The secure and non-secure binary images will be signed
for use with the BL2 secure bootloader.
An additional .hex file is also generated to enable
running QEMU with the AN521 binaries, `tfm_qemu.hex`,
which can be executed with the `-t run` option with
west, or `run` with ninja or make.
When configured for use with TF-M, the
`mps2_an521_nonsecure` board definition should be used.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
PSA level 1 requires secure boot. TF-M BL2 is the official
secure boot loader. It needs a BL2_HEADER_SIZE offset.
Align nonsecure address with TF-M's NS slot while TF-M BL2 enabled.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
Use DT_INST_SPI_DEV_HAS_CS_GPIOS() in drivers to determine if we should
utilize CS_GPIO base SPI chipselect handling. This allows us to remove
Kconfig option for this feature.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
For HPET devices, configure it with fixed delivery mode because HPET
timer interrupt is needed to fuel the scheduler for all CPUS.
For all other type of devices, like UART, I2C, GPIO, Ethernet, etc.
configure them as lowest priority delivery mode, in which IO APIC
delivers the interrupt to the processor core that is executing at the
lowest priority among all the processors listed in the specified
destination. In this case, the device drivers can avoid the trouble of
handling repeated interrupts delivered to all CPUS.
Signed-off-by: Zide Chen <zide.chen@intel.com>
Swap this out and make the status a parameter.
Leave a couple of cases of DT_NODE_HAS_COMPAT().
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
These are redundantly checking a node's status twice.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Usually, we want to operate only on "available" device
nodes ("available" means "status is okay and a matching binding is
found"), but that's not true in all cases.
Sometimes we want to operate on special nodes without matching
bindings, such as those describing memory.
To handle the distinction, change various additional devicetree APIs
making it clear that they operate only on available device nodes,
adjusting gen_defines and devicetree.h implementation details
accordingly:
- emit macros for all existing nodes in gen_defines.py, regardless
of status or matching binding
- rename DT_NUM_INST to DT_NUM_INST_STATUS_OKAY
- rename DT_NODE_HAS_COMPAT to DT_NODE_HAS_COMPAT_STATUS_OKAY
- rename DT_INST_FOREACH to DT_INST_FOREACH_STATUS_OKAY
- rename DT_ANY_INST_ON_BUS to DT_ANY_INST_ON_BUS_STATUS_OKAY
- rewrite DT_HAS_NODE_STATUS_OKAY in terms of a new DT_NODE_HAS_STATUS
- resurrect DT_HAS_NODE in the form of DT_NODE_EXISTS
- remove DT_COMPAT_ON_BUS as a public API
- use the new default_prop_types edtlib parameter
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
With the new RI-2018.0 XCC, xt-gdb complains about not being able
to find register f0. Turns out that xt-gdb needs to be told which
file to look at (the file command) before a load command can be
issued. So swap these two commands in the load_elf.txt file.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
