Commit graph

7,339 commits

Author SHA1 Message Date
Anas Nashif
1f1b10eb26 intel_adsp: move register definition from soc.c to shim header
Declare those register in the adsp_shim header instead of the code
applying ifdefs that limit the scope to only specific SoCs.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif
ad32077108 intel_adsp: move l1 memory definition to header
Move register definition to SoC header instead of hardcoding it where it
is being used.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif
01438a1998 intel_adsp: move imr configs to headers
Move those defines and values back to headers. Kconfig is not a good
place for this, later this should move to DTS.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif
af3d5331a1 intel-adsp: migrate cavs-mem.h to adsp_memory.h
Move header and make it soc specific.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif
3586227a7c intel_adsp: adsp_shim.h: run through clang-format
Run the files through clang-format to clean things up a bit.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif
453f37c3d9 intel_adsp: shim: cleanup shim header
Remove conditional code and SOC specific defines.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif
423264b96b intel_adsp: make shim header soc specific
using once single header to support multiple socs and product
generations is error prone and not easily maintained.

Over time we have been adding conditional code in headers and extending
structs  to support new HW features which becomes a problem.

Goal is to keep platform headers in sync with hardware specification and
allow of introduction of new platforms and hardware features by just
introducing a new SoC with its own set of headers.

This is now just a copy of existing cavs-shim.h with slight changes,
goal is to clean this up long term and sync with hardware datasheets and
align on naming as well.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif
51cd0dd682 intel_adsp: move soc headers into include/
Move headers into the include/ folder per soc and rename fw_defs.h to
adsp_memory to align with SOF.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif
f72cdeb896 intel_adsp: common: remove unnecessary ifndefs
cavs15 has its own boot path, so no need to check for it in code it does
not run.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif
2f83adae93 intel_adsp: common: build soc.c only for CAVS
build soc.c only for platforms that can use it.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Kumar Gala
2d88414c4e drivers: serial: pl011: Remove unused Kconfig symbols
The driver has be DT_INST based for a while so the Kconfig
symbols CONFIG_UART_PL011_PORT0<n> aren't used.  So lets
remove them.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-21 16:40:28 +00:00
Simon Hein
c29d0a3c4f soc: arm: comply to coding guidelines MISRA C:2012 Rule 14.4
MISRA C:2012 Rule 14.4 (The controlling expression of an if statement
and the controlling expression of an iteration-statement shall have
essentially Boolean type.)

Use `do { ... } while (false)' instead of `do { ... } while (0)'.

This commit is a subset of the original commit:
5d02614e34a86b549c7707d3d9f0984bc3a5f22a

Signed-off-by: Simon Hein <SHein@baumer.com>
2022-07-21 10:31:00 +02:00
Tom Burdick
ac84039060 tests: intel_adsp: Silence the hda tests
Uses a macro with a define flag to enable register dumps on the DSP
side. On the python side a simple booling flag.

The default disabled both debug flags and makes the tests
considerably quieter.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-07-19 16:10:47 -04:00
Tomislav Milkovic
0fe2c1fe90 everywhere: Fix legacy include paths
Any project with Kconfig option CONFIG_LEGACY_INCLUDE_PATH set to n
couldn't be built because some files were missing zephyr/ prefix in
includes
Re-run the migrate_includes.py script to fix all legacy include paths

Signed-off-by: Tomislav Milkovic <milkovic@byte-lab.com>
2022-07-18 16:16:47 +00:00
Bernard Lee
5658e9e30d soc: arm: nordic_nrf: include linker sections header
Include linker sections header to move z_arm_platform_init to text
section. It is now is placed in the TEXT section.

Signed-off-by: Bernard Lee <bernard.lee@nordicsemi.no>
2022-07-18 16:11:50 +00:00
Attie Grande
7ded40de84 soc: atmel_sam0: The ADC reference is locked while enabled for SAML21
For SAML21-based parts, the REFCTRL register is locked while the ADC is
enabled. Permit some parts to declare that they need the ADC to be
disabled before modifying REFCTRL.

Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
2022-07-18 10:35:46 +00:00
Attie Grande
a10b8cb1c0 soc: atmel_sam0: Add support for SAMR34 and SAMR35 parts
Implement support for SAMR34 and SAMR35 parts, tested on a SAMR34
Xplained Pro dev board. Confirmed operational peripherals: UART, GPIO,
PWM, ADC.

NOTE: The SAMR34 datasheet lists NVIC line 20 for the ADC's interrupt,
but the SAML21 datasheet gives line 22. It appears that the SAMR34 sheet
is incorrect (the ADC doesn't function with line 20), and as such, I have
also omitted the adjustments for TC4 and AC...

Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
2022-07-18 10:35:46 +00:00
Attie Grande
64e4200d94 soc: atmel_sam0: Add support for SAML21 parts
Implement support for SAML21 parts, tested on a SAML21 Xplained Pro dev
board. Confirmed operational peripherals: UART, GPIO, PWM, ADC.

Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
2022-07-18 10:35:46 +00:00
Enjia Mai
9b8726c101 soc: xtensa: include linker/section.h to fix the build error
Some tests was built failed due to cannot find the __imr macro:
Try to fix it by including the linker/section.h in soc.h.

Fixes #47830.

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-07-16 05:53:45 -04:00
Mulin Chao
24fb705cdd npcx: scfg: psl: cleanup unused functions and DT files
Clean up unused psl functions in scfg.c, unused DT macros, unused psl DT
nodes and related yaml files. Currently, PSL pad configurations are made
by pinctrl mechanism. Please refer
https://issuetracker.google.com/234861079 for more detail.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2022-07-15 10:00:15 +02:00
Johann Fischer
3c971307dc arch/kernel/soc/samples: use unsigned int for irq_lock()
irq_lock() returns an unsigned integer key.
Generated by spatch using semantic patch
scripts/coccinelle/irq_lock.cocci

Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
2022-07-14 14:37:13 -05:00
Tom Burdick
c225cf3b8a dma: HDA rename prefix from cAVS to ADSP
HDA is a common IP used across the entire ADSP line and deserves
a name respecting that alongside similiar IP drivers such as the
ADSP GPDMA driver.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-07-14 17:53:46 +00:00
Anas Nashif
76f990af8a intel_adsp: move attribute macros to dedicated linker header
Those belong where other attribute macros are usually defined. They are
not xtensa or ADSP specific and are used across Intel SoCs on all
architectures.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-13 11:15:46 -04:00
Anas Nashif
680df57582 intel_adsp: add a header for soc specific defines
Instead of ifdeffing on SOCs and missing things along the way, maintain
platform definitions that are different among SoCs in one single file
per SoC and use data from that file critical spots.

In this case, we were checking for CAVS25, setting one value where
everything else was set to 0, so new SoC like ACE was getting 0 as well,
although it has the same value as TGL.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-13 11:15:46 -04:00
Anas Nashif
e328508a66 intel_adsp: ace: run soc.c through clang-format
Just a minor cleanup.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-13 11:15:46 -04:00
Anas Nashif
fc67224864 intel_adsp: ace: simplify and cleanup sram init functions
Remove redundant code and simplify SRAM init functions.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-13 11:15:46 -04:00
Anas Nashif
332d9fb7d1 intel_adsp: ace: rename inx -> idx
Original author probably meant inx for index, use idx instead.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-13 11:15:46 -04:00
Anas Nashif
f82b271b1f intel_adsp: ace: convert delay count into a define
The delay count was converted to a define.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-13 11:15:46 -04:00
Mulin Chao
3468a02f72 npcx: scfg: pinmux: cleanup unused functions and macro
Clean up unused pinmux function 'npcx_pinctrl_mux_configure()' and
related 'NPCX_DT_IO_ALT*' macro functions.

Please refer https://issuetracker.google.com/234861079 for more detail.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2022-07-13 10:38:49 +02:00
Tim Lin
04c6d7569f ITE: drivers/i2c: Add command queue mode
Adding command queue mode can reduce the time between each byte to
improve the I2C bus clock stretching during I2C transaction.

I2C command queue mode of it8xxx2 can support I2C APIs including:
i2c_write(), i2c_read(), i2c_burst_read.

Test:
1. tests\drivers\i2c\i2c_api --> pass
2. Reading 16 bytes of data through i2c_burst_read() can reduce
   0.72ms(2.54ms->1.82ms) compared to the original pio mode when the
   frequency is 100KHz.
3. krabby platform can boot normally.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-07-13 10:15:32 +02:00
Jay Vasanth
7c88336171 soc: device_power: MEC172x: fix incorrect for loop check
fix incorrect iteration condition in MEC172x device_power.c

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-07-12 09:24:30 -05:00
Jeppe Odgaard
af6f975391 soc: select HAS_MCUX_SRC for MIMXRT1052
Select missing HAS_MCUX_SRC Kconfig symbol for MIMXRT1052,
that allows using NXP i.MX mcux SRC hwinfo driver.

Fixes https://github.com/zephyrproject-rtos/zephyr/issues/47025

Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
2022-07-12 10:17:38 +02:00
Pieter De Gendt
3cde5a0aaa soc: mimxrt1064: Remove unused low power header include
The included header file wasn't used.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2022-07-11 17:51:18 -05:00
Pieter De Gendt
3556bf6fa9 soc: mimxrt1064: Fix low power build issue with video PLL
Fix build error if CONFIG_PM and CONFIG_INIT_VIDEO_PLL are enabled.
Added 2 missing semicolons.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2022-07-11 17:51:18 -05:00
Peter Ujfalusi
e243122c1e dma/cavs_hda: Configure DGMBS only for host DMA configuration
The DGMBS should be only set for the host side and not on the link DMA.

Fixes: #46632
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
2022-07-11 18:04:54 +00:00
Carlo Caione
2f5fef960e sample: s2ram: Introduce S2RAM sample
Introduce a template / sample for S2RAM running on rf5340dk.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-11 15:26:26 +02:00
Carlo Caione
541024eb43 riscv: litex-vexriscv: Add missing header
soc.h is using sys_read* functions. Add the proper header for that.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-11 14:31:39 +02:00
Carlo Caione
5d104f20ab riscv: Introduce API for CLIC and PLIC
Introduce a new interface for CLIC and PLIC to be used by the drivers.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-11 14:31:39 +02:00
Carlo Caione
56466a14e1 riscv: Decouple CLIC and PLIC
Try to decouple CLIC and PLIC as much as possible.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-11 14:31:39 +02:00
Carlo Caione
31c5dc2230 Kconfig: Introduce RISCV_HAS_CLIC
Introduce a new RISCV_HAS_CLIC symbol for platforms using CLIC,
reorganize the Kconfigs and make the Nuclei ECLIC depending on the new
symbol.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-11 14:31:39 +02:00
Julien Massot
08f5fb5cdb soc: arm: fvp_aemv8r_aarch32: define static mpu regions
Add static MPU regions for this SoC.
These regions will be initialized as static region during system boot.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
2022-07-11 11:17:02 +02:00
Flavio Ceolin
ad8ae7f735 dma: intel: Merge cavs and ace gpdma
cAVS and ACE gpdma driver have several similarities. This commit merge
this two drivers into a single one for Intel ADSP devices.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-11 10:21:17 +02:00
Flavio Ceolin
b1abe896e6 intel_adsp: ace: Fix function return
zephyr/soc/xtensa/intel_adsp/ace_v1x/irq.c: In function
'z_soc_irq_is_enabled':

zephyr/soc/xtensa/intel_adsp/ace_v1x/irq.c:47:3: warning: 'return'
with no value, in function returning non-void [-Wreturn-type]

   47 |   return;

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-08 21:13:29 -04:00
Kumar Gala
a22ac090db soc: xtensa: intel_adsp: ace_v1x: irq: Convert to use DEVICE_DT_GET
Move to use DEVICE_DT_GET instead of device_get_binding as
we work on phasing out use of DTS 'label' property.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-08 20:03:32 +00:00
Kumar Gala
37fc9552e6 soc: xtensa: intel_adsp: irq: Convert to use DEVICE_DT_GET
Move to use DEVICE_DT_GET instead of device_get_binding as
we work on phasing out use of DTS 'label' property.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-08 20:03:32 +00:00
Kumar Gala
4faf362030 soc: apollo_lake: gpio: Drop use of DT_LABEL
Change APL_GPIO_DEV_* defines to be DT_NODELABELs instead of
"label" strings.  This lets us change users of these defines to
use DEVICE_DT_GET.

We update samples/board/up_squared/gpio_counter to use DEVICE_DT_GET
as part of this change.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-08 20:01:47 +00:00
Tom Burdick
572ccd531d intel_adsp: Use device tree to enable/disable each HDA driver
Uses the dt_compat_enabled Kconfig preprocessor to set defaults
for each HDA driver.

Each direction is uniquely selectable which can be useful when building
with SOF where only some directions may wish to be enabled at any given
time.

By default, given the device tree (intel_cavs.dtsi) only the host
directions are enabled but an overlay may adjust that as needed.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-07-08 14:33:06 -04:00
Francois Ramu
c1782a096e soc: arm: new stm32f412Rx device
This adds a new stm32f412Rx in the list of stm32F4 devices.
The module stm32cube/stm32f4/soc/stm32f412rx.h exists

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-07-08 10:49:31 +02:00
Marc Herbert
08baba2520 soc/intel_adsp: cavstool: add support for DSP power state: D3
Change some behaviors when --log-only is passed in order to add support
for DSP power state: D3. This makes it possible to keep `cavstool
--log-only` running permanently in the "real-world" use case where the
Linux kernel loads the firmware and powers down audio when not in use.

More specifically:
- Do not disable D3 when using --log-only.
- Wait forever for the FW at boot time.
- Check live status when an invalid IPC is received and wait forever if
  not alive.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-07-08 10:45:44 +02:00
Marc Herbert
ef4cd76970 soc/intel_adsp: cavstool: new parameter wait_fw_entered(timeout_s)
Add a new timeout_s parameter that can also be 'None' = infinite.

No functional change. Required to add future support for DSP power
state: D3

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-07-08 10:45:44 +02:00