Configures flexcomm4 to operate in USART mode and enables the associated
peripheral clock and pinmuxes. This instance is attached to the Arduino
serial header pins and can be used for Bluetooth serial HCI with a
frdm_kw41z or other BLE controller shield.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Switch from using internal 6pf to internal 7pf load capacitor for LFXO.
Use a default clock accuracy of 50PPM as this matches lab results.
50PPM should be sufficient for common operating temperatures of
25degC +- 15.
Signed-off-by: Johan Stridkvist <johan.stridkvist@nordicsemi.no>
Always source the Zephyr base soc and shield (board root) Kconfigs
directly from Kconfig instead of generated Kconfig files.
This has the benefit that it is no longer necessary to generate Kconfig
files to source SoC root and shield (board root) when no custom roots
are provided.
Also this cleans up the doc/CMakeLists.txt and ensures that the
doc/CMakeLists.txt is not getting out of sync with the Kconfig.cmake.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
To support west OpenOCD path image flashing, this generates an npcx hex
image from the npcx BIN image. Moreover, this also changes the name of
npcx output image by CONFIG_KERNEL_BIN_NAME.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Create the pinmux phandle to the ADC driver node in the
devicetree. When the pinmux_pin_set function in
adc_it8xxx2_channel_setup can refer to the setting of
this phandle. It is more flexible to use.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
NPCX7 variants allocate code RAM either at 0x10070000 or 0x10090000.
The MPU requires addresses and region sizes to be aligned, so the
generic cortex_m/arm_mpu_regions.c results in an ineffective setup with
the addresses above.
This adds a custom mpu_regions setup for the npcx7, which covers both
available sizes, resulting in these two possible setups:
- 192kB devices
Code ram: 0x10090000 to 0x100bffff
MPU region: 0x10080000 to 0x100bffff (256k)
- 320kB devices
Code ram: 0x10070000 to 0x100bffff
MPU region 0: 0x10040000 to 0x1007ffff (256k)
MPU region 1: 0x10080000 to 0x100bffff (256k)
In both cases MPU data RAM setting is from 0x200c0000 to 0x200cffff,
matching the generic Cortex-m setup.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add Kconfig options that allow configuration of optional internal
load capacitors for the high-frequency (HFXO) and low-frequency
(LFXO) crystal oscillators in nRF5340.
Default settings used for the new options are those that have been
in effect so far, i.e. external load capacitors for HFXO and 6 pF
internal capacitance for LFXO.
This commit also adds missing SOC_ENABLE_LFXO option dependency on
!TRUSTED_EXECUTION_NONSECURE.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This CL adds the support for npcx9m3f and npcx9m6f chips in ecst.py
script which generates the NPCX firmware header.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL replaces macros for miwu multi-registers' offset with internal
inline functions. This CL also uses soc series definitions to
distinguish the layout of miwu multi-registers between different npcx
series.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL adds the soc drivers for npcx9 series. There are two soc part
numbers, npcx9m3f and npcx9m6f, are introduced. We also move soc family
configurations from /nuvoton_npcx/npcx7/Kconfig.soc to
nuvoton_npcx/Kconfig.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
In npcx9, the number of pinmux registers (DEVALTx) is more than 16. We
need to extend the "group" member in the struct npcx_ALT to configure
the pinmux settings in npcx9.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL moves power policy source file for all npcx series to common
folder. It also abstracts the sources for checking register structures
to common/registers.c to avoid the duplicated sources in the later npcx
series.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL replaces series-prefix "npcx7-" with family-"npcx-" for npcx dts
nodes such as 'espi-vws-map' and 'miwus-int-map'. Since we plan to
introduce the npcx9 and later series, adding a new node such as
npcx9-espi-vws-map for each series is more complicated and not
necessary.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Commit f5c6afeccb attempted to avoid
accessing lpc55xxx flash registers in nonsecure mode by conditionalizing
part of the SoC clock initialization routine on whether the flash driver
was enabled. This caused secure applications without the flash driver
enabled (e.g., hello_world on lpcxpresso55s69_cpu0) to not boot or show
any console output. Fix this by changing the condition to depend on
whether we are building a nonsecure image.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
When we link in crtbegin.o for C++ exception support we end up pulling
in the .tm_clone_table section. We need to update the linker scripts
to handle this. soc/xtensa/sample_controller/linker.ld was already
updated, this fixes the others.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Set `ROM_START_OFFSET` for SAMD5X series to match the value
calculated in the linker file after forced alignments in
`vector_table.ld`.
Signed-off-by: Arvin Farahmand <arvinf@ip-logix.com>
Zephyr kernel masks interrupts before calling the SoC PM
sleep entry point. On the Cortex-Mx family this prevents
wake from peripheral interrupts. The SoC PM layer requires
interrupts to wake the SoC and must prevent the CPU from
vectoring to an interrup until PM exit. The SoC does this
by setting ARM NVIC PRIMASK to 1 and BASEPRI to 0. On
return to the kernel SoC sets PRIMASK to 0 allowing ISR's
to fire. In addition the MEC HW only clears its peripheral
sleep enables if the CPU vectors to an ISR. On wake we
clear the MEC PCR sleep control register which clears all
the peripheral sleep enables so peripherals will be active
before exiting the SoC PM layer.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Fixes part of: #32448
This commit updates the CMake CMAKE_CXX_LINK_EXECUTABLE to include
crtbegin.o and crtend.o at the right locations when linking with gcc.
It also updates linker scripts to ensure proper location of the
exception header frame sections.
This ensure proper handling of exceptions for those architectures
- x86
- xtensa
- riscv32
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Remove (disabled) MPU support for the NXP Kinetis K2x. At least the
MK22F51212, which is the only K2x supported by Zephyr so far, does not
contain an MPU.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Reduce the length of the Kconfig defines related to
null-pointed dereference detection in Cortex-M.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Increase FLASH_PAGE_ERASE_MAX_TIME_US of cpunet to be the same as the
value of cpuapp; FLASH_PAGE_ERASE_MAX_TIME_US is the execution window
duration when doing the flash operation synchronously along the radio
operations (SOC_FLASH_NRF_PARTIAL_ERASE not enabled); the previous
FLASH_PAGE_ERASE_MAX_TIME_US value of cpunet is lower than required.
Signed-off-by: Lang Xie <lang.xie@nordicsemi.no>
When using the LPC55S69 with TF-M, the ROM-based flash
controller is restricted to the secure processing environment
to prevent NS access to flash memory. Any access to the
flash controller will cause a secure fault, and the NS
application will halt execution.
This commit disables access to the IAP flash peripheral
when using the lpcxpresso55s69_ns target, enabling TF-M
to restrict IAP access to the secure side.
Signed-off-by: Kevin Townsend <kevin.townsend@linaro.org>
some mwdt compiler options not support cmake function
check_c_compiler_flag, let's add mwdt compiler options for
hsdk boards without check.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
arcmwdt toolchain has various pre build libraries, we can find it in
path: {METAWARE_HOME}/lib, and it will use av2em lib by default.
it's OK for em boards, but not suitable for hs boards. I have tested
hs38_full library for hs boards, it's OK. let's use it.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
NPCX series ROM code changes the chip basic setting by firmware binary
header for loading the firmware from flash to RAM. Add the following to
improve the ec firmware header setting:
- Move the ECST which generates the firmware binary header to NPCX
common folder. All the following NPCX series chips can use this.
- Add ecst setting option in Kconfig.
Signed-off-by: Yuval Peress <peress@chromium.org>
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Z_ITERABLE_SECTION_ROM symbols were empty, meaning
that those symbols were not taking place in the linker script.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This CL limits the compiler to consider the eSPI/LPC host wake-up
functions, such as npcx_host_disable_access_interrupt and
npcx_host_disable_access_interrupt, only if eSPI bus module is selected.
Otherwise, we will encounter compiler errors if the communication
between host and ec is via SPI, not eSPI/LPC bus.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit fixes the ADC driver flow. And add internal
reference voltage to ADC driver API. And correct the
data buffer that only need to store raw data.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Set TRACE_MODE to asynchronous and enable trace output pin.
Add soc_config.c in stm32 soc direcotry.
Fixes#34342
Signed-off-by: Andrés Manelli <am@toroid.io>
NPCX clock has some limitations about the frequency range &
synchronization between core clock & other clocks. Add build assert to
check whether NPCX clock setting correct. This also fixed soc_clock.h
to consist with datasheet.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Cleanup along the same lines as the last change to APL/up_squared.
Make sure all hardware configuration is at the board level where it
belongs and not in the soc, don't play games with defaulting timer
drivers. Unify the configuration where possible and make it clearer
which setting goes with which driver.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The addition of a timer driver made a messy situation worse. Move
board-level configuration like clock rates and dividers into the board
and don't try to default it in the soc. Make it clear which kconfig
goes with which driver. Likewise don't try to do driver selection in
the soc, the board (or app) is in a better position to choose.
Also clean up and better unify the up_squared 32/64 bit settings.
Really only CONFIG_BOARD_NAME needs to care about the difference
between these devices.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Add QEMU board with single core ARCv3 HS6x 64 bit CPU
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Add the missing .cached section on cAVS 2.0 and 2.5 to fix
compiler warnings.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
PLATFORM_RESET_MHE_AT_BOOT and
PLATFORM_DISABLE_L2CACHE_AT_BOOT have to be defined on cAVS 1.8
too, without them secondary cores cannot be used.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
uncache_to_cache(), cache_to_uncache() and is_uncached() macros
are currently unused in Zephyr, besides the former two are
dangerous because they add and subtract an offset instead of
masking and unmasking a bit, which can lead to wrong addresses
if applied repeatedly. Remove these macros for now, we can
re-add them later if needed in their fixed versions.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Currently only cAVS 1.5 Kconfig selects ARCH_HAS_COHERENCE,
which is wrong. cAVS 1.8, 2.0 and 2.5 have to select it too.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Added support for GPIO driver for Intel Elkhart Lake
board.
The GPIO driver will support pin value read/write operations,
pin direction and interrupt configuration. ACPI enumeration
support and support for different GPIO communities is also
present.
Verified on ehl_crb.
Signed-off-by: U Divya <u.divya@intel.com>
spi1 and i2c0 share peripheral ID number 3.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
UART0, TWI0, and SPI0 have different peripheral IDs (2, 3, and 4
respectively) on this SoC and therefore should not be mutually
exclusive to use.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
