Zephyr PM expects the SoC layer upon wake to unmask interrupts
the PM layer masked. MEC172x was re-enabling interrupt globally
in the Cortex-M4 but not clearing the mask set by Zephyr PM.
This worked in previous Zephyr releases but broke in the latest
Zephyr changes. Fixed the SoC to re-enable interrupts globally
and call irq_unlock(0) as Zephyr PM does if pm_state_exit_post_ops
is not implemented. Tested on MEC172x EVB with PLL clock out pin
enabled and verified PLL goes off in deep sleep, system wakes,
and interrupts are firing.
Signed-off-by: scott worley <scott.worley@microchip.com>
This commit introduces power management support for EFR32BG SoCs.
Tested on the efr32bg_sltb010a board.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The purpose of the GIC ITS is to translate message-passing interrupts into
LPIs. The LPI range starts at value 8192, which means the current default
value (200) is too low. Therefore, bump the highest IRQ number when ITS
is enabled.
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
There are some issues with the current version of the code, mainly the
improper use of the internal OSC8M as a source for the DFLL48m without
division. The DFLL48M is designed to accept a maximum of ~33KHz
at it's input, as higher values will bring the multiplier down,
leading to instability.
Also added the following features:
* Support for external HF oscillator (XOSC)
* Support for crystal/external oscillators on XOSC32K/XOSC
* Automatic dividers/multiplier computation based on DT cpu frequency
* Support for user configurable NVM wait states
* Added option to skip clock (re)initialization (bootloader usecase).
Tests were performed on a custom SAMD20G18 board using different clock
sources and cpu frequencies.
Clocks were routed to GPIO pins and observed on a scope.
According to the datasheet, architecture is identical on D21/R21.
Due to the nature of the internal architecture and the fact that
DFLL48M is not really meant to output anything other than 48MHZ
some combinations of requested DT cpu frequency and source
frequency will not result in a perfect match.
Mostly insipred by the SAML21 implementation.
Signed-off-by: Ionut Catalin Pavel <iocapa@iocapa.com>
1. Move the GPIO mux setting to the soc layer. The GPIO MUX
value may vary based on the SoC Family
2. Enable the digital input buffer if available
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add configuration items to select various ARM debug options
such as SWD only, SWD plus SWV, or SWD plus ETM. The default
is SWD only.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
LNL uses MM_DRV_INTEL_ADSP_MTL_TLB to save / restore context.
This is exactly the same like on MTL. Enable PM for ACE 2.0 then.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
LNL platform is ACE 2.0 series with changes in shim registers and HW
features. Initial definition replicates MTL as much as possible, however
it will vary after enabling LNL platform.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Added UART instances and changes to enabled
support for PCIe UART instances.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Added a new watchdog driver which can handle a multiple wdt_dw instances
and can control the pause signal.
The mlt platform has three designware watchdogs, one for each core.
I decided to create a separate intel watchdog driver for the following
reasons:
1. All three devices share the same interrupt number. Each watchdog reports
an interrupt to the core to which it has been assigned. The same interrupt
number cannot be used by multiple devices in the device tree. So, it would
be assigned to only one device. The other dw watchdog devices would use
this assignment, even though it would not be described for them in the dt.
The interrupt handler function in dw watchdog checks the interrupt flag.
If the interrupt was connected to the first watchdog, and the second or
third watchdog signal an interrupt, the interrupt handler of the first
device would ignore it because it would not have set the interrupt flag.
The watchdog device don't knows anything about the existence of the others
devices.
2. The designware watchdog only supports a hardware pause signal. It cannot
be paused programmatically. On the mtl platform, there is a separate group
of control registers for all per-core watchdogs. There are GPIO-like
registers that allows control of a hardware pause signal for subordinate
watchdogs. This separate block is shared by all three watchdogs.
3. The base addresses of the subordinate watchdogs are read from the
aforementioned control registers. As a result, in the device tree we have
only one base address for the intel watchdog, which points to the pause
control registers and containing the base addresses of the subordinate
devices.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Enable at SoC boot time when enabled through Kconfig. Cache management
API is not used since it could be built without its support enabled.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
When CONFIG_NOCACHE_MEMORY=y, the .nocache section is placed in between
__rodata_region_end and _app_smem_start/__kernel_ram_start. Make sure
this region is covered by the MPU background region so that the static
region for nocache is configured correctly.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
It's best practice to run as little code as possible as root (especially
when listening to network ports). When not itself running as root
already, remote-fw-service.py has always tried to invoke cavstool.py
with "sudo". Unfortunately this looks like it never worked; at least not
on Ubuntu 22 where this commit was tested. Moreover it did not fail
immediately but mysteriously timed out without any useful error message.
- The first, most obvious bug was that "sudo" does not propagate
SIGKILL (and a few other signals), see "man sudo". Compare:
```
$ sudo sleep 30 &
$ kill $! # sudo propagates the TERM signal and sleep is terminated
$ sudo sleep 30 & sudoPID=$!
$ kill -KILL $sudoPID
$ ps xfao pid,ppid,pgid,sid,comm | grep -C 5 -e PID -e sleep -e sudo
```
Fix this by invoking proc.terminate() first before proc.kill().
proc.terminate() is more "polite" with cavstool even when not using
sudo.
- Second issue: when signals are sent to sudo, strace shows that its
signal handler invokes `getpgid()` and then ignores signals coming from
its own process group. `man sudo` states: "sudo will not relay signals
that were sent by the command it is running...", which seems related.
`start_new_session=True` option moves sudo to a different PGID which
stops sudo from ignoring signals from its remote-fw-service.py parent.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Introduce the new stm32h5 soc serie from STMIcroelectronics.
Note that stm32h503x do not have TrustZone nor SAU
Signed-off-by: Francois Ramu <francois.ramu@st.com>
A recent change introduced the possibility to declare MPU memory
regions using the device tree and the framework described in
zephyr/linker/devicetree_regions.h.
So remove the device region declared in mpu_regions[] and the used
defines for the addresses, rename REGION_DEVICE_ATTR to REGION_IO_ATTR
in arm_mpu.h to be compatible with the framework and add a device tree
node to fvp_baser_aemv8r.dts to describe the device memory region.
Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Remove the manually created linker section, because it's already
automatically generated for all sram regions in the DTS with the
"zephyr,memory-region" compatibility.
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
Change device tree VW routing to a form allowing overrides.
Add two new DT optional properties for specifying the reset
source and reset value of each virtual wire. Only virtual
wires that are enabled using the status property are modified.
NOTE: eSPI virtual wires are controlled in groups of 4 by
hardware. The optional reset signal source properties applies
to all four virtual wires in the group. If this field is
changed from the hardware default, it should be changed for
only one virtual wire in the group. If the property exists
in more than one wire in the group it must be set to the
same value.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Modify Mircrochip MEC172x eSPI driver to get eSPI virtual wire
hardware routing from device tree.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
The clock control driver requires three pieces of information:
PCR register index, bit position, and clock domain. Clock domain
was missing from DT information and MCHP macros.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Start using zephyr power management in cavs platform in a similar way
that is already done in ace. This commit only addresses the power off/on
sequence. Runtime power management is not implemented.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
This reverts commit 7a85983ebc.
This commit was merged prematurely and is causing issues on multiple
platforms.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Some pico-sdk drivers call a panic function, originally implemented
as part of the Pico's C runtime. This commit adds a Zephyr compatible
implementation of panic, so that those drivers could be compiled with
Zephyr.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
Add initial version of clock control for Atmel SAM SoC series. This add
support to Power Management which allows control peripherals clock.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Product URL: https://www.ti.com/product/CC1352P7
Datasheet : https://www.ti.com/lit/ds/symlink/cc1352p7.pdf
Features:
Powerful 48-MHz Arm® Cortex®-M4F processor
* 704KB flash program memory
* 256KB of ROM for protocols and library functions
* 8KB of cache SRAM
* 144KB of ultra-low leakage SRAM with parity for
high-reliability operation
* Dual-band Sub-1 GHz and 2.4 GHz operation
Updates:
* Remove CC1352P7_LaunchXL due to compliance checks
* Add CC1352P7 updates
* Update hal_ti for CC1352P7 support
* Remove blank line at end of modules/Kconfig.simplelink
* Split struct and typedef for pinctrl_soc_pin/pinctrl_soc_pin_t
* Reference cc13x2_cc26x2/pinctrl_soc.h
* Reference cc13x2_cc26x2/soc.h
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
In general, RTC and TIMER driver implements counter API but there
are exception when those peripherals are used in a custom way
(e.g. for system timer or bluetooth). In that case, system must
prevent using counter based on a reserved instance. Previously,
it was managed by Kconfig options but that cannot be maintained
when switching to devicetree configuration of the counter driver.
A new approach removes Kconfig options and instead adds static
asserts in the files which are using direct peripherals. Those
asserts check if given node is not enabled in the device tree.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Some platforms need to define multiple memory regions with
various attribute. This patch adds dts defined regions in the mpu
configuration. The memory attribute can be set in the device tree.
Signed-off-by: Yanqin Wei <Yanqin.Wei@arm.com>
Now rimage can handle both cached and uncached addresses correctly,
ELF rewriting isn't needed any more.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Removed the EEPROM and ESPI configuration from file
Kconfig.defconfig.mec172xnsz. Since it overrides the
setting present in the Device Tree file.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
