Commit graph

974 commits

Author SHA1 Message Date
Ederson de Souza
28e07bf1ba soc/xtensa/intel_adsp: Fix clock selection when WOVCRO isn't available
If test for WOVCRO clock fails, code shouldn't just choose WOVCRO clock
as the lowest frequency one, but LPRO instead.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-07-28 11:04:05 -04:00
Flavio Ceolin
580f370867 intel_adsp: Rename multiprocessing cavs file
For intel adsp platforms we have a common multiprocessing.c file and
then another multiprocessing.c for ace and multiprocessing_cavs.c for
cavs. Rename the cavs specific implementation to follow the convention.
There is not need to "cavs" suffix since the file is already inside its
specific directory.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-27 17:50:52 -04:00
Flavio Ceolin
24f2fa96dc intel_adsp: Move cavs common files to a subdir
Inside the common directory there were files that are CAVS specific and
are not used by ACE_V1X. Lets create a subdir called cavs inside the
common to put files that are common for only cavs plaftorms.

Note that there are still remaining code that in the common folder that
are using cavs namespace like "cavs_ipc_*" that may need some additional
work.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-27 17:50:52 -04:00
Anas Nashif
43371d0414 intel_adsp: move cavs to be a series
Intel ADSP CAVS is now a proper series with all CAVS SoCs running under
it. This will give us to Intel ADSP series:
- CAVS
- ACE v1.x

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-25 16:50:24 -04:00
Anas Nashif
e33bb9b6c5 drivers: dmic: remove old intel dmic driver
We now have another intel dmic driver under DAI.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-25 13:14:49 -04:00
Flavio Ceolin
b1a968fca9 intel_adsp: ace: Add variables used in coredump
In order to coredump dump the ram memory, it is necessary that we define
in the linker scripts two variable to indicate the start and the end of
the ram area. Adding these variables to ace linker script.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-25 12:42:42 -04:00
Flavio Ceolin
7cbe74adb1 intel_adsp: cavs: Add variables used in coredump
In order to coredump dump the ram memory, it is necessary that we define
in the linker scripts two variable to indicate the start and the end of
the ram area. Adding these variables to cavs linker script.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-25 12:42:42 -04:00
Flavio Ceolin
f90082209d intel_adsp: Remove unused header
cavs/version.h was never used by Zephyr, it was supposed to be needed by
SoF. This no longer seems to be the case, just removing it.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-25 12:41:56 -04:00
Anas Nashif
987693c270 intel_adsp: rename obsolete adsp timer config
Use INTEL_ADSP_TIMER instead.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif
2af59e7d44 intel_adsp: unify timer registers and simplify timer driver
Declare clock control in the shim header per SoC and remove ifdeffry
from the driver simplifiying it and making it ready for the next
platform.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif
356779448c intel_adsp: minor header include reorg/fixups
Minor reorg of headers and when they get included.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif
9a28930ece intel_adsp: rename power_init_mtl
No need for the suffix here, this is built only for Meteorlake anyways.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif
1f1b10eb26 intel_adsp: move register definition from soc.c to shim header
Declare those register in the adsp_shim header instead of the code
applying ifdefs that limit the scope to only specific SoCs.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif
ad32077108 intel_adsp: move l1 memory definition to header
Move register definition to SoC header instead of hardcoding it where it
is being used.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif
01438a1998 intel_adsp: move imr configs to headers
Move those defines and values back to headers. Kconfig is not a good
place for this, later this should move to DTS.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif
af3d5331a1 intel-adsp: migrate cavs-mem.h to adsp_memory.h
Move header and make it soc specific.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif
3586227a7c intel_adsp: adsp_shim.h: run through clang-format
Run the files through clang-format to clean things up a bit.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif
453f37c3d9 intel_adsp: shim: cleanup shim header
Remove conditional code and SOC specific defines.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif
423264b96b intel_adsp: make shim header soc specific
using once single header to support multiple socs and product
generations is error prone and not easily maintained.

Over time we have been adding conditional code in headers and extending
structs  to support new HW features which becomes a problem.

Goal is to keep platform headers in sync with hardware specification and
allow of introduction of new platforms and hardware features by just
introducing a new SoC with its own set of headers.

This is now just a copy of existing cavs-shim.h with slight changes,
goal is to clean this up long term and sync with hardware datasheets and
align on naming as well.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif
51cd0dd682 intel_adsp: move soc headers into include/
Move headers into the include/ folder per soc and rename fw_defs.h to
adsp_memory to align with SOF.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif
f72cdeb896 intel_adsp: common: remove unnecessary ifndefs
cavs15 has its own boot path, so no need to check for it in code it does
not run.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif
2f83adae93 intel_adsp: common: build soc.c only for CAVS
build soc.c only for platforms that can use it.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Tom Burdick
ac84039060 tests: intel_adsp: Silence the hda tests
Uses a macro with a define flag to enable register dumps on the DSP
side. On the python side a simple booling flag.

The default disabled both debug flags and makes the tests
considerably quieter.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-07-19 16:10:47 -04:00
Tomislav Milkovic
0fe2c1fe90 everywhere: Fix legacy include paths
Any project with Kconfig option CONFIG_LEGACY_INCLUDE_PATH set to n
couldn't be built because some files were missing zephyr/ prefix in
includes
Re-run the migrate_includes.py script to fix all legacy include paths

Signed-off-by: Tomislav Milkovic <milkovic@byte-lab.com>
2022-07-18 16:16:47 +00:00
Enjia Mai
9b8726c101 soc: xtensa: include linker/section.h to fix the build error
Some tests was built failed due to cannot find the __imr macro:
Try to fix it by including the linker/section.h in soc.h.

Fixes #47830.

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-07-16 05:53:45 -04:00
Tom Burdick
c225cf3b8a dma: HDA rename prefix from cAVS to ADSP
HDA is a common IP used across the entire ADSP line and deserves
a name respecting that alongside similiar IP drivers such as the
ADSP GPDMA driver.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-07-14 17:53:46 +00:00
Anas Nashif
76f990af8a intel_adsp: move attribute macros to dedicated linker header
Those belong where other attribute macros are usually defined. They are
not xtensa or ADSP specific and are used across Intel SoCs on all
architectures.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-13 11:15:46 -04:00
Anas Nashif
680df57582 intel_adsp: add a header for soc specific defines
Instead of ifdeffing on SOCs and missing things along the way, maintain
platform definitions that are different among SoCs in one single file
per SoC and use data from that file critical spots.

In this case, we were checking for CAVS25, setting one value where
everything else was set to 0, so new SoC like ACE was getting 0 as well,
although it has the same value as TGL.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-13 11:15:46 -04:00
Anas Nashif
e328508a66 intel_adsp: ace: run soc.c through clang-format
Just a minor cleanup.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-13 11:15:46 -04:00
Anas Nashif
fc67224864 intel_adsp: ace: simplify and cleanup sram init functions
Remove redundant code and simplify SRAM init functions.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-13 11:15:46 -04:00
Anas Nashif
332d9fb7d1 intel_adsp: ace: rename inx -> idx
Original author probably meant inx for index, use idx instead.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-13 11:15:46 -04:00
Anas Nashif
f82b271b1f intel_adsp: ace: convert delay count into a define
The delay count was converted to a define.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-13 11:15:46 -04:00
Peter Ujfalusi
e243122c1e dma/cavs_hda: Configure DGMBS only for host DMA configuration
The DGMBS should be only set for the host side and not on the link DMA.

Fixes: #46632
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
2022-07-11 18:04:54 +00:00
Flavio Ceolin
ad8ae7f735 dma: intel: Merge cavs and ace gpdma
cAVS and ACE gpdma driver have several similarities. This commit merge
this two drivers into a single one for Intel ADSP devices.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-11 10:21:17 +02:00
Flavio Ceolin
b1abe896e6 intel_adsp: ace: Fix function return
zephyr/soc/xtensa/intel_adsp/ace_v1x/irq.c: In function
'z_soc_irq_is_enabled':

zephyr/soc/xtensa/intel_adsp/ace_v1x/irq.c:47:3: warning: 'return'
with no value, in function returning non-void [-Wreturn-type]

   47 |   return;

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-08 21:13:29 -04:00
Kumar Gala
a22ac090db soc: xtensa: intel_adsp: ace_v1x: irq: Convert to use DEVICE_DT_GET
Move to use DEVICE_DT_GET instead of device_get_binding as
we work on phasing out use of DTS 'label' property.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-08 20:03:32 +00:00
Kumar Gala
37fc9552e6 soc: xtensa: intel_adsp: irq: Convert to use DEVICE_DT_GET
Move to use DEVICE_DT_GET instead of device_get_binding as
we work on phasing out use of DTS 'label' property.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-08 20:03:32 +00:00
Tom Burdick
572ccd531d intel_adsp: Use device tree to enable/disable each HDA driver
Uses the dt_compat_enabled Kconfig preprocessor to set defaults
for each HDA driver.

Each direction is uniquely selectable which can be useful when building
with SOF where only some directions may wish to be enabled at any given
time.

By default, given the device tree (intel_cavs.dtsi) only the host
directions are enabled but an overlay may adjust that as needed.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-07-08 14:33:06 -04:00
Marc Herbert
08baba2520 soc/intel_adsp: cavstool: add support for DSP power state: D3
Change some behaviors when --log-only is passed in order to add support
for DSP power state: D3. This makes it possible to keep `cavstool
--log-only` running permanently in the "real-world" use case where the
Linux kernel loads the firmware and powers down audio when not in use.

More specifically:
- Do not disable D3 when using --log-only.
- Wait forever for the FW at boot time.
- Check live status when an invalid IPC is received and wait forever if
  not alive.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-07-08 10:45:44 +02:00
Marc Herbert
ef4cd76970 soc/intel_adsp: cavstool: new parameter wait_fw_entered(timeout_s)
Add a new timeout_s parameter that can also be 'None' = infinite.

No functional change. Required to add future support for DSP power
state: D3

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-07-08 10:45:44 +02:00
Flavio Ceolin
158a87018c intel: adsp: Simplify PM
Both idle and suspend states were just being used to set the cpu
idle. That is not necessary, if the pm policy does not find a suitable
power state the kernel automatically calls k_cpu_idle().

This remove unnecessary code and the weirdness of having
min-residency-us set to 0 and other arbitrary values.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-07 02:10:11 -04:00
Enjia Mai
faff3f7ecc soc: xtensa: partial fix of socket misuse and refine the code
1. Improve the firmware transfer reliability by fixing the misuse
of the socket. Fix the most frequent occurence of the common `recv()`
bug described here:

https://docs.python.org/3/howto/sockets.html#using-a-socket

The longer term fix is to switch to a higher level API like Python
Remote Objects.

2. Not rely on the client's command to disconnect. Previously we
rely on the SIGINT to send stop_command to the server, but it does
not work well in some environments. Refine the whole logic and the
sever disconnect service by checking if the client is alive or not.

These changes make the client-server-based cavstool more stable.

Fixes #46864

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-07-06 20:38:41 -04:00
Andrey Borisovich
e0b1d81acb soc: intel_adsp: added casting for C++ compiler in soc.h
Header soc.h is included during C++ source file compilation
and required adding C++ casts as implicit casting from void*
is forbidden. Fixed minor warning comparing signed with unsigned
integer.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-07-06 15:11:07 -04:00
Andrey Borisovich
aa253d9ab1 soc: intel_adsp: reading HP SRAM banks count for ACE1X from Devicetree
Replaced hardcoded for intel_adsp_ace15_mtpm board
HP_MEMORY_BANKS value used in SOF code with generic approach -
using PLATFORM_HPSRAM_EBB_COUNT read from Devicetree.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-07-06 15:11:07 -04:00
Flavio Ceolin
92725e3102 soc: adsp: sram: Assorted cosmetic fixes
General code style fixes.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-06 15:11:07 -04:00
Flavio Ceolin
7291c518a0 soc: ace: Organizing include headers
Properly prefixing some include files with "zephyr", also organizing
the order they are included.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-06 15:11:07 -04:00
Flavio Ceolin
65fbfcd480 soc: ace: Move power management to its own file
Move power management hooks to its own C file.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-06 15:11:07 -04:00
Flavio Ceolin
e4a3e2d8b6 intel_adsp: Unify cavs and ace timers
These two timers were sharing pretty much the same code. Actually
mtl timer was a "superset" of cavs timer. Just merge them into a
single one called intel audio dsp timer (intel_adsp_timer).

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-06 15:11:07 -04:00
Andrey Borisovich
e0e2dbf6f0 soc: ace1x: provided register names to addresses
Provided register names to hardcoded addresses in ace_v1x-regs
header.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-07-06 15:11:07 -04:00
Anas Nashif
8792dd800d soc: ace1.x: use common code
Do not duplicate code in new SoC and reuse code from intel_adsp/common.
Move SRAM code into own file in common code and setup SRAM in soc for
MTL platform.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-06 15:11:07 -04:00