Commit graph

2589 commits

Author SHA1 Message Date
Kumar Gala
e4dd77ed72 soc: arm: atmel_sam: Add support for pinctrl flags
Add devicetree support to specify bias-pull-up, bias-pull-down, and
drive-open-drain for pin configuration.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-09-03 18:09:24 -05:00
Mulin Chao
2612c50daa drivers: clk_ctrl: npcx: fixed 'line length exceeds 80 columns' warning.
Fixed 'line length exceeds 80 columns' warning by shortening the clock
controller device name from NPCX_CLOCK_CONTROL_NAME to
NPCX_CLK_CTRL_NAME.

Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-09-03 21:53:35 +02:00
Erwin Rol
742256f8ed drivers: dma: stm32: only set mem pool size when using DMAMUX
The general DMA driver doesn't use kmalloc anymore so it doesn't
need a memory pool. The DMAMUX_SMT32 driver still uses kmalloc,
so move the HEAP_MEM_POOL_SIZE config under DMAMUX_STM32.

Signed-off-by: Erwin Rol <erwin@erwinrol.com>
2020-09-03 21:50:58 +02:00
Martin Jäger
66dde3a968 drivers: dac: Enable for STM32F0 series
Add DAC nodes to devicetree, include LL headers in soc.h and add
pinmux defines for DAC.

Signed-off-by: Martin Jäger <martin@libre.solar>
2020-09-03 14:46:03 -05:00
Martin Jäger
1dab7751b5 drivers: dac: Enable for STM32G4 series
Add DAC nodes to devicetree, include LL headers in soc.h and add
pinmux defines for DAC.

Signed-off-by: Martin Jäger <martin@libre.solar>
2020-09-03 14:46:03 -05:00
Alexandre Bourdiol
980848af43 drivers: clock: stm32f7 needs power over-drive to reach 216Mhz
Assuming we stay on default Power Scale 1,
overdrive is required when System Core Clock frequency is higher
than 180MHz.

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-09-03 14:45:24 -05:00
Arnaud Ferraris
37a8592114 soc: arm: st_stm32: stm32mp1: enable HSEM clock on init
Most drivers make use of the HW semaphore (see `stm32_gpio.c`), but the
HSEM clock isn't currently setup on the MCU side. This means we rely on
the MPU to enable this clock, which is an unsafe bet: the OS running on
the MPU may not have support for HSEM, or it might enter sleep state,
which will disable the clock. As a consequence, firmwares loaded from
the MPU running this OS will block on the first `z_stm32_hsem_lock()`
call.

As it is required to run anything on the MCU core, we shouldn't assume
the HSEM clock is already active when booting and enable it in the SoC
init, the same way it is done for the STM32H7.

Signed-off-by: Arnaud Ferraris <arnaud.ferraris@collabora.com>
2020-09-03 14:44:26 -05:00
Crist Xu
956a767cd6 soc: arm: Fix SDRAM linker section size for i.mx rt
Change DT_REG_REG ==> DT_REG_SIZE for the SDRAM node

Signed-off-by: Crist Xu <crist.xu@nxp.com>
2020-09-03 14:43:28 -05:00
Henrik Brix Andersen
140841fc73 soc: arm: arm: designstart: add cortex-m3 designstart fpga support
Add support for the ARM Cortex-M3 DesignStart FPGA SoC.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-09-02 15:02:03 +02:00
Alexandre Bourdiol
6bc559bdaa soc: arm: st_stm32: update HSEM ID from STM32WB cube update
New Hardware semaphore ID have been defined in STM32WB cube

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-09-02 14:13:49 +02:00
Tomasz Bursztyka
e18fcbba5a device: Const-ify all device driver instance pointers
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.

A coccinelle rule is used for this:

@r_const_dev_1
  disable optional_qualifier
@
@@
-struct device *
+const struct device *

@r_const_dev_2
 disable optional_qualifier
@
@@
-struct device * const
+const struct device *

Fixes #27399

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-09-02 13:48:13 +02:00
Mulin Chao
b3188f1c32 drivers: npcx: replace type of register base address with uintptr_t
Replace npcx register base address type, uint32_t, with uintptr_t.
It is easier to know what type of base address and for linear
addresses treated as integral values.

This CL also modified IS_BIT_SET() macro function to fit MISRA code
guidelines.

Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-09-01 13:35:25 +02:00
Mulin Chao
1eca7ab46a drivers: npcx: remove suffix '_t' of device register structure.
Remove the '_t' suffix of device register structure since it is used
mainly with typedefs.

Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-09-01 13:35:25 +02:00
Mulin Chao
6deb68a517 driver: gpio: add gpio driver support in NPCX series
Add gpio support for Nuvoton NPCX series. This CL includes:

1. Add GPIO device tree declarations.
2. Introduce wui_maps property in yaml file to present relationship
   between Wake-Up
   Input (WUI) and 8 IOs belong to the device.
3. Zephyr GPIO api implementation.
4. GPIO callback functions implementation with MIWU api functions.
5. Overlay file for gpio basic tests

Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-09-01 13:35:25 +02:00
Mulin Chao
84d90e456a driver: intc: add MIWU driver support in NPCX series.
The device Multi-Input Wake-Up Unit (MIWU) supports the embedded
controller (EC) to exit 'Sleep' or 'Deep Sleep' power state which allows
chip has better power consumption. Also, it provides signal conditioning
such as 'Level' and 'Edge' trigger type and grouping of external
interrupt sources of NVIC. The NPCX series has three identical MIWU
modules: MIWU0, MIWU1, MIWU2. Together, they support a total of over 140
internal and/or external wake-up sources.

In this CL, we use device tree files to present the relationship bewteen
MIWU and the other devices in different npcx series. For npcx7 series,
it include:
1. npcx7-miwus-int-map.dtsi: it presents relationship between MIWU group
   and NVIC interrupt in npcx7. Please notice it isn't 1-to-1 mapping.
2. npcx7-miwus-wui-map.dtsi: it presents relationship between input of
   MIWU and its source device such as gpio, timer, eSPI VWs and so on.

This CL also includes:
1. Add MIWU device tree declarations.
2. MIWU api function declarations and implementation to configure signal
   conditions and callback function mechanism. They can be be classified
   into two types. One is for GPIO which connects original gpio callback
   implemetation and the other is for generic devices such as timer,
   eSPI, and so on.

Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-09-01 13:35:25 +02:00
Andrzej Głąbek
c519184211 soc: nordic_nrf: Add definition of nRF52805 SoC
Add definition of the nRF52805 SoC together with the corresponding
dts files.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2020-08-31 15:40:19 +02:00
Andrzej Głąbek
d2027b3b98 soc: nordic: nrf51: Add missing peripheral Kconfig options
To indicate that the CLOCK and POWER peripherals are present in those
SoCs, thus the corresponding nrfx drivers can be used.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2020-08-31 12:40:47 +02:00
Mahesh Mahadevan
f75f8bec20 MXRT600: Add DMA support
Add DMA support for MCUX LPC SoC's

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-08-28 14:24:21 -05:00
Alexandre Bourdiol
5ae149a17b board: arm: nucleo_f207zg: add DAC support
Add DAC support to nucleo_f207zg:

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-08-27 16:06:34 +02:00
Mahesh Mahadevan
fe2b393fff MXRT600: Add support for SPI
Enable access to the arduino pins on the mxrt600 evk board

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-08-24 16:19:12 -05:00
Hake Huang
ebd0a3759e counter: enable k6s pit support support
enable k6s pit counter support

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2020-08-21 14:27:59 -05:00
Hake Huang
f976de4767 counter: enable pit support for k8x series
enable PIT in k8x series

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2020-08-21 14:27:59 -05:00
Maureen Helm
654a49a9f8 soc: nxp_imx: Set entry to _vector_start in boot header
Commit e80e655b01 introduced linker script
enforcement of Cortex-M vector table alignment. Update the i.MX RT boot
header to account for the possibility that the vector table may not be
placed at the address CONFIG_FLASH_BASE_ADDRESS +
CONFIG_ROM_START_OFFSET anymore.

For example, the RT1060 vector table has 176 entries and therefore must
be aligned to 0x400 bytes. If CONFIG_FLASH_BASE_ADDRESS=0x60000000 and
CONFIG_ROM_START_OFFSET=0x2200, the linker script will place the vector
table at 0x60002400 instead of 0x60002200.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-08-20 09:20:38 +02:00
Jose Alberto Meza
319be27041 boards: arm: mec15xx: Allow to use some of ADC pins for JTAG tracing
Use new KConfig switches to configure debug support.
Correct ADC configuration where all ADC pins are in ADC mode.

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2020-08-19 10:40:07 -05:00
Jose Alberto Meza
357638955a soc: arm: mchp: Add switch to configure JTAG pins
Currently JTAG debug is enabled by default.
In some designs is desirable to disable JTAG functionality.

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2020-08-19 10:40:07 -05:00
Manivannan Sadhasivam
2aae0b7b5b soc: arm: nxp_imx: Add i.MX8M Mini SoC support
Add SoC support for the NXP i.MX8M Mini series MIMX8MM6 SoC. This SoC
has a quad Cortex-A53 cluster and a single core Cortex-M4 core. Zephyr
support is added to the Cortex-M4 core for running at 800MHz.

More information about the SoC can be found here: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i.mx-applications-processors/i.mx-8-processors/i.mx-8m-mini-arm-cortex-a53-cortex-m4-audio-voice-video:i.MX8MMINI

Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
2020-08-14 14:51:50 -05:00
Henrik Brix Andersen
f9aee9f8dc soc: arm: add Cortex-M1 ARM DesignStart FPGA SoC support
Add support for the Cortex-M1 ARM DesignStart FPGA SoC. This is not an
SoC in the traditional sense but more of a base to build an SoC upon.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-08-14 13:35:39 -05:00
Mulin Chao
cd296f41a3 boards: arm: npcx7m6fb_evb: Add npcx7m6fb_evb board
Skeleton board support for the npcx7m6fb evaluation board from Nuvoton
Technology. This CL also includes:

1. Add ecst python scripts to append the header used by NPCX ROM.
2. Add openocd configuration scripts for "west flash".
3. Add monitor FW binary file for programing/verifying embedded flash
   in NPCX series.

Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-08-13 16:42:20 +02:00
Mulin Chao
1162747574 driver: serial: Add UART support in NPCX series.
Add UART support for Nuvoton NPCX series. This CL includes:

1. Add UART controller device tree declarations.
2. UART controller driver implementation.

Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-08-13 16:42:20 +02:00
Mulin Chao
9cb73abbdc driver: pinctrl: Add pin control support in NPCX series.
Add pin controller support for Nuvoton NPCX series
Add pin-mux controller support for Nuvoton NPCX series.

This CL includes:
1. Add pin controller device tree declarations and introduce alt-cells
   to select pads' functionality.
2. Add npcx7-alts-map.dtsi since the mapping between IO and controller
   is irregular and vary in each chip series.
3. Add nuvoton,npcx-pinctrl-def.yaml and its declarations to change all
   pads' functionality to GPIO by default.
4. Pinmux controller driver implementation.

Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-08-13 16:42:20 +02:00
Mulin Chao
0245a27bc5 driver: clock: Add clock controller support in NPCX series.
Add clock controller support for Nuvoton NPCX series. This CL includes:

1. Add clock controller device tree declarations.
2. Introduce clock-cells in yaml file clock tree to get module's source
clock and turn off/on the its clock
3. Clock controller driver implementation.

Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-08-13 16:42:20 +02:00
Mulin Chao
ec50b1846f soc: arm: Add Nuvoton NPCX7M6FB SoC
Initial support for Nuvoton NPCX7M6FB SoC of NPCX series which is a chip
family of embedded controllers (EC) and targeted for a wide range of
portable applications. We implemented the SoC skeleton in
soc/arm/nuvoton_npcx since there're many chip families in Nuvoton and
aim to different markets such as PC, General MCU, and Audio. The
architectures and hardware modules are different between them. Hence, we
suggest using the company name plus with chip series for better
understanding.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2020-08-13 16:42:20 +02:00
Martí Bolívar
e6341de714 soc: silabs_exx32: add missing ifs to Kconfig.defconfig
This file is setting Kconfig options even when it is not the chosen
SoC. I noticed this because without this patch, CONFIG_SOC_GECKO_EMU=y
when building for an unrelated board with SYS_POWER_MANAGEMENT=y.

Hide any subtrees in this file when the EXX32 family isn't selected.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2020-08-10 08:57:37 -05:00
Alexander Kozhinov
2505daf28f soc: arm: stm32h7: remove explicit full libc selection
remove explicit full libc selection
	following same approach as for stm32f7 series

Signed-off-by: Alexander Kozhinov <AlexanderKozhinov@yandex.com>
2020-08-07 10:01:34 -04:00
Hubert Miś
3182af00d7 boards: Move 802.15.4 SOC configuration from Nordic boards to SOCs
IEEE 802.15.4 is available for each board with Nordic SOC implementing
this protocol. Because of that protocol configuration shall be tied to
SOC instead of board.

Signed-off-by: Hubert Miś <hubert.mis@nordicsemi.no>
2020-08-07 11:56:35 +02:00
Vincent Wan
ddefef9d32 soc: ti_simplelink: build power.c when device PM is enabled
On CC13x2/CC26x2, power.c should be built when either system or device
power management is enabled. Currently it is only doing so for the
former.

Fixes #27392

Signed-off-by: Vincent Wan <vwan@ti.com>
2020-08-06 09:36:08 -04:00
Alexander Kozhinov
9c2c77e4df soc: arm: stm32h7: entropy generator support
add entropy generator

Signed-off-by: Alexander Kozhinov <AlexanderKozhinov@yandex.com>
2020-08-06 11:54:20 +02:00
Steven Lemaire
128b72e041 soc: silabs_exx32: Remove const keyword for clock configuration
Some parameters (e.g., tuning capacitors) can be configured in the
CMU_HFXOInit_TypeDef and CMU_LFXOInit_TypeDef structures before calling
CMU_HFXOInit() and CMU_LFXOInit() during clock initialisation.

Signed-off-by: Steven Lemaire <steven.lemaire@zii.aero>
2020-08-06 11:49:16 +02:00
Steven Lemaire
3ae6c67771 soc: silabs_exx32: Add support for SiLabs EFR32MG21 SoC
This commit adds support for Silicon Labs EFR32MG21 (Mighty Gecko) SoC.

Signed-off-by: Steven Lemaire <steven.lemaire@zii.aero>
2020-08-06 11:49:16 +02:00
2b6783aa15 drivers: dac: add a driver for the SAM0 DAC
The Atmel SAM0 DAC is a single channel 10 bit DAC with selectable
reference.

Signed-off-by: Michael Hope <mlhx@google.com>
2020-08-04 16:08:48 -05:00
Jiří Keresteš
3a87517c5e drivers: watchdog: mcux_wwdt: add driver for NXP LPC 55xxx WWDT
Adds shim driver for LPC 55xxx Windowed Watchdog Timer (WWDT).

Also updates the "Supported features" table in LPCXpresso55S69
board documentation page.

Fixes #22704.

Signed-off-by: Jiří Keresteš <jiri@kerestes.cz>
2020-08-04 15:13:25 -05:00
Alexandre Bourdiol
8978071334 STM32H7: manage Dual core boot whatever option bytes configuration
Manage Dual core boot automatically whatever Option Bytes
configuration.
No more need of KConfig STM32H7_DUAL_CORE_BOOT to match
Option Bytes.

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-07-31 11:09:18 -05:00
Mahesh Mahadevan
209084e745 MXRT600: Add I2C support
Enable I2C access to FXOS7000 sensor on the mxrt685_evk board

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-07-31 08:23:20 -05:00
Maxime Bittan
9ca6b704a7 drivers: i2c: Add support for LPC11U6X I2C controllers
This commit adds a driver for the LPC11U6X I2C controllers

Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
2020-07-29 20:12:24 +02:00
Simon Guinot
84e0d8c78d soc: nxp_lpc: lpc11u6x: add IAP interface
This patch adds the iap.h header file which provides an entry function
for the IAP (In-Application Programming) interface. Note that the IAP
commands are located in the boot ROM code. Mostly they provide access
to the on-chip flash and EEPROM devices.

Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
2020-07-29 20:12:24 +02:00
Maxime Bittan
4edf475d1c drivers: serial: Add support for LPC11U6X UART controllers
This commit adds support for UART0-4 controllers present on
LPC11U6X MCUs.

Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
2020-07-29 20:12:24 +02:00
Maxime Bittan
ed4511ea8c drivers: clock_control: lpc11u6x: Add support for clock controller
This commit adds basic support for the clock controller used in
lpc11u6x MCUs.

Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
2020-07-29 20:12:24 +02:00
Simon Guinot
fb92dd1bc7 drivers: pinmux: add driver for NXP LPC11U6X MCUs
This patch adds a pinmux driver allowing to configure the IOCON (I/O
control) registers found on the LPC11U6x MCUs.

Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
2020-07-29 20:12:24 +02:00
Maxime Bittan
9931eca5f9 soc: arm: Add basic support for LPC11U6X series
This commit adds basic support for the NXP lpc11u6x soc series.

Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
2020-07-29 20:12:24 +02:00
Mahesh Mahadevan
14beecbdbe MXRT600: Lower clock speed to avoid using power library
We cannot call into the power library API as it is currently
available in binary format which cannot be included

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-07-28 18:24:19 -05:00