Commit graph

2589 commits

Author SHA1 Message Date
Maureen Helm
7bebab862c soc: arm: Refactor i.mx rt device configuration data default
Refactors the i.mx rt soc series to enable device configuration data
(DCD) by default when the smart external memory controller (SEMC) is
present. This is in preparation for removing the DATA_LOCATION Kconfig
symbol and using a device tree chosen node instead.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-10-22 09:32:11 -05:00
Gerson Fernando Budke
73e9217e73 soc: arm: cypress: Introduce PSoC-63 BLE
Add initial support for PSoC-63 BLE Series.

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2020-10-22 08:18:27 -05:00
Abhishek Shah
b53f62d259 drivers: pcie_ep: iproc: Add MSI-X PVM feature for Viper
Add support for interrupt driven MSI-X PVM feature for Viper.
Function mask bit update is tracked with snoop interrupt
and vector mask bit update is tracked with pcie pmon lite
address range access detection interrupt.
Both the interrupts are required to enable this feature.

Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
2020-10-22 11:07:39 +02:00
Mulin Chao
d55aa5a71b driver: npcx7: replace platform specific functions with 'npcx_' prefix.
Replace all platform specific functions with 'npcx_' prefix.

Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-10-21 12:49:02 -05:00
Kumar Gala
b6b7e4c770 arm: v2m_musca: Mark Musca-A board support deprecated for 2.6.0
Deprecate the Musca-A board and SoC support to be removed in 2.6.0.
There are a number of issues with the Musca-A and there exists both the
Musca-B and Musca-S1.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-10-21 07:23:22 -05:00
Mulin Chao
173704859a dts: npcx7: rename pinctrl property to pinctrl-0
rename 'pinctrl' property to 'pinctrl-0' in device-tree files

Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-10-21 06:33:20 -05:00
Mahesh Mahadevan
76cc0ddc3e soc: LPC55S69: Add DMA support
Add DMA configuration for LPC55S69

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-10-21 06:26:40 -05:00
Øyvind Rønningstad
22eb8f496a nrf53: soc.c: Replace bespoke nrf53_has_erratum19() with MDK variant
Use nrf53_errata_19() from nrf_erratas.h, which is more robust

Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2020-10-20 12:28:54 +02:00
Mahesh Mahadevan
f025700d8f soc: LPC54xxx, LPC55xxx: Update to use clock control
Use the clock control driver to get flexcomm clock
frequency

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-10-15 11:17:24 -05:00
Mahesh Mahadevan
350edf9415 soc: RT600: Update to use clock control
Use the clock control driver to get flexcomm clock
frequency

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-10-15 11:17:24 -05:00
Yestin Sun
d6e718f414 soc: arm: st_stm32: add support for stm32l562Xe
Add support for the stm32l562Xe SoC

Signed-off-by: Yestin Sun <sunyi0804@gmail.com>
2020-10-15 09:53:00 -05:00
Frank Li
53cc090c39 boards: mm_swiftio: enable pwm devices
Enable pwm device for mm_swiftio.
select HAS_MCUX_PWM for rt1052.

Signed-off-by: Frank Li <lgl88911@163.com>
2020-10-14 15:33:10 -05:00
Thorvald Natvig
8db1e20639 boards: arm: efm32gg_*: Enable TRNG
This defines the TRNG for EFM32GG11 and enables it for trng0
in the dts for the matching development kits.

Signed-off-by: Thorvald Natvig <thorvald@natvig.com>
2020-10-14 08:35:20 -05:00
Toby Firth
dc37f988e0 drivers: adc: added support adc driver for lpcexpresso55s69
Added shim driver for the LPADC for lpcexpresso55s69 board.

Fixes #22703.

Signed-off-by: Toby Firth <tobyjfirth@gmail.com>
2020-10-12 14:59:40 -05:00
Thorvald Natvig
7f9f4e6597 boards: Add SiLabs SLWSTK6121A (WGM160P)
The WGM160P module combines the WF200 Wi-Fi transceiver with
an EFM32GG11 MCU
This code is based on the efm32gg_stk3701a board definitions

Signed-off-by: Thorvald Natvig <thorvald@natvig.com>
2020-10-12 14:46:19 -05:00
Erwan Gouriou
b74a2162cb soc/arm: stm32: swap argument order in ST_STM32 PINCTRL macros
In order to be in line with other DT_INST macros in zephyr code base,
swap the arguments order in following macro definitions:
*ST_STM32_DT_PINCTRL
*ST_STM32_DT_INST_PINCTRL
Update the users accordingly.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-10-09 11:52:59 +02:00
Erwan Gouriou
155f3c5eba soc/arm: stm32: Provide node label based pinctrl devicetree helpers
As an alternative to ST_STM32_DT_INST_PINCTRL, provide
ST_STM32_DT_PINCTRL macro and set of matching internal macros.

This could be used by device drivers that can't use directly
device instances but rather the node label identifier. For instance:
ST_STM32_DT_PINCTRL(0, i2c1);

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-10-09 11:52:59 +02:00
Erwan Gouriou
2d3cda7663 soc/arm: stm32: use _INST_ namespace in devicetree pinctrl helpers
Current set of helpers provided for STM32 pinctrl devicetree are
using device instance as input.
In order to prepare for next version that will take node identifier
as input, change existing set of macros using _INST_ namespace.

Additionally rename NODE_ID_FROM_PINCTRL to
ST_STM32_DT_INST_NODE_ID_FROM_PINCTRL.

Finally update existing macros users to this new name scheme.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-10-09 11:52:59 +02:00
Erwan Gouriou
4b3a6a0e91 soc/arm: stm32: Clean up pinctrl devicetree helper macros
Before adding new macros, clean up existing file:
* Provide full length description for each macro
* Cascade the device instance pinctl- property index so that
any pinctrl- instance number could be used
* Remove intermediate ST_STM32_DT_PIN macro

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-10-09 11:52:59 +02:00
Alexander Mihajlovic
c88f85b25c soc: arm: stm32l0: Add STM32L071 series
L072 was also redefined as a superset of the
new L071, and the common elements moved.

Signed-off-by: Alexander Mihajlovic <a@abxy.se>
2020-10-09 11:52:06 +02:00
Eric Hay
e51b24b429 drivers: clock_control: stm32g0: Enable the Q divisor on g0X1 variants
The PLL Q divisor does not exist on stm32g0X0 variants. It should only
be configured for g0X1 variants.

Signed-off-by: Eric Hay <EHay@sierrawireless.com>
2020-10-09 11:49:39 +02:00
Eric Hay
31fca27d83 soc: arm: stm32g0: Set IRQs to 30 for stm32g070 series
The number of IRQs for the g070 is 30, not 32.

Signed-off-by: Eric Hay <EHay@sierrawireless.com>
2020-10-09 11:49:39 +02:00
Eric Hay
5f42ba52d8 soc: arm: stm32g0: add STM32G070 SoC series
This commit adds support for the STM32G070xx SoCs
by STMicroelectronics.

Signed-off-by: Eric Hay <EHay@sierrawireless.com>
2020-10-09 11:49:39 +02:00
Mulin Chao
dd99fbebe6 drivers: pwm: add pwm driver support in NPCX7 series
In npcx7 series, there're 8 Pulse Width Modulator (PWM) modules and each
one support generating a single 16-bit PWM output. A 16-bit clock
prescaler (PRSCn) and a 16-bit counter (CTRn) determine the cycle time,
the minimal possible pulse width, and the duty-cycle steps.

Beside introducing pwm driver for Nuvoton NPCX series, this CL also
includes:

1. Add PWM device tree declarations.
2. Zephyr PWM api implementation.
3. Add aliases in npcx7m6fb_evb board device tree file for supporting
   samples/basic/blinky_pwm application and pwm test suites

Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-10-06 18:16:02 -05:00
Carlo Caione
6f9ca9c15a qemu_cortex_a53: Switch to GICv3
QEMU support for GICv3 is mature enough that we can switch to that by
default.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2020-10-06 12:53:58 -04:00
Mulin Chao
fd54701b49 drivers: gpio: npcx7: change default pinmux of functional pads to GPIO
Change default pinmux of functional pads to GPIOs. It includes:
1. PIN96.A0.A2.A4 - If internal flash is supported
2. PIND2.00 - Default PSL inputs
3. PIN31.30.27.26.25.24.23.22 - Keyboard inputs
4. PIN21.20.17.16.15.14.13.12.11.10.07.06.05.04.82.83.03.B1 - Keyboard
   outputs
5. Add description for soc_pinctrl_mux_configure() usage.

It also fixed the typo and inverse mistakes in npcx7-alts-map.dtsi.

Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-10-02 11:44:06 +02:00
Mulin Chao
99c208f36a soc: npcx7: add comments for macro funcs used for device tree files.
This CL adds more comments for each macro functions used for device tree
file for better explanations. It also changes all hex values in soc.c to
lower case.

Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-10-02 11:33:15 +02:00
Mulin Chao
e42a3a5a96 drivers: espi: add host sub-modules support for NPCX7 series.
This CL contains the drivers of NPCX Host Sub-Modules that serve as an
interface between the Host and Core domains. For most of them, the Host
can configure these modules via eSPI(Peripheral Channel)/LPC by
accessing 'Configuration and Control register Set' which IO base address
is 0x4E as default. And the interrupts in core domain help handling any
events from host side.

In this commit, we introduced six host sub-modules. It includes:
 1. Keyboard and Mouse Controller (KBC) interface.
 2. Power Management (PM) channels.
 3. Shared Memory mechanism (SHM).
 4. Core Access to Host Modules (C2H).
 5. Mobile System Wake-Up functions (MSWC).
 6. Serial Port (Legacy UART)

The tasks in application layer such as 8042, ACPI and host command can
cooperation with this driver by connecting api or callback functions.

Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-10-02 11:33:15 +02:00
Mulin Chao
be217e4a3a drivers: eSPI: add eSPI driver support for NPCX7 series.
In npcx7 series, all of them support the Intel Enhanced Serial
Peripheral Interface (eSPI) Revision 1.0. This specification provides a
path for migrating host sub-devices via LPC to a lower pin count, higher
bandwidth bus. In addition to Host communication via the peripheral
channel, it provides virtual wires support, out-of-band communication,
and device mastering option over the Chipset SPI flash.

Becisdes introducing eSPI device in npcx7, this CL also includes:

1. Add eSPI device tree declarations.
2. Add npcx7-espi-vws-map.dtsi to present the relationship between eSPI
   Virtual-Wire signals, eSPI registers, and wake-up input sources.
3. Zephyr eSPI api implementation.
4, Add OOB (Out of Band tunneled SMBus) support.
5. Add configuration files for eSPI test suites.

Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-10-02 11:33:15 +02:00
Erwan Gouriou
0f95e31e7e soc: stm32f1: Update DT macros for dt pinctrl support
ST_STM32_PINCFG requires slight modification to support
encoding pincfg structure from pinctrl dt bindings.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-10-01 11:08:42 -05:00
Erwan Gouriou
d1afd83df0 drivers/pinmux: stm32: provide dt pinctrl to gpio driver interface
Provides tool set to be used by device drivers in order to be able
to configure device signals.
This does not involve the implementation of a dedicated pinctrl
driver. In this regard, this is equivalent to implementation used
for treatment of current pinmux.c files.

Since STM32F1 uses a different GPIO configuration scheme, its
support is exlcuded for now.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-10-01 11:08:42 -05:00
Noelle Clement
762b806c3d soc: arm: stm32: Add support for STM32L151xC SoC
STM32L151xC SoC differs from other L1 SoCs in RAM (32KiB) and
flash (256KiB) size, and amount of interrupts (57, see STM32Cube).
Devicetree and Kconfig support.

Signed-off-by: Noelle Clement <noelleclement@hotmail.com>
2020-09-30 10:32:33 -05:00
Nicolai Glud
bc72b67a5d dts: clocks: kinetis: set pllfll and er32k clock settings from dts
Setup osc clock settings from dts.

Signed-off-by: Nicolai Glud <nicolai.glud@prevas.dk>
2020-09-29 14:05:50 -05:00
Rick Talbott
60e5e79ca1 drivers: mcux: imx rt flexcan support
Adds imx rt support.
Allows n-number of can interfaces based on device-tree.
Adds a "common" irq name.
Added CAN bus pins and dts for 1060 and 1064 EVK.

Signed-off-by: Rick Talbott <rtalbott@fastmail.com>
2020-09-29 14:03:10 -05:00
Carlo Caione
a5f34d85c2 soc: arm: qemu_cortex_a53: Remove SRAM region
The standard and static MMU regions (_code, _rodata and _data) are
already covering all the available SRAM region and all the needed
sections. Remove the overlapping SRAM region.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2020-09-28 16:06:44 +02:00
Ioannis Glaropoulos
142219896d boards: arm: musca_b1: do not offset the image by default by 0x400.
We only need to offset the start of the non-secure image
by 0x400, if TFM is built with BL2 support. In this case
we use the ROM_START_OFFSET Kconfig switch  and set to
0x400. This instructs the linker to offset the beginning
of the ROM section by 0x400. In other words, we do not need
to statically move the start of the image by 0x400. This
fixes an issue that prevents from running Zephyr + TFM
without BL2 on Musca B1.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-09-22 19:38:51 +02:00
Ioannis Glaropoulos
96ce274d03 boards: mps2_an521: do not offset the image by default by 0x400.
We only need to offset the start of the non-secure image
by 0x400, if TFM is built with BL2 support. In this case
we use the ROM_START_OFFSET Kconfig switch  and set to
0x400. This instructs the linker to offset the beginning
of the ROM section by 0x400. In other words, we do not need
to statically move the start of the image by 0x400. This
fixes an issue that prevents from running Zephyr + TFM
without BL2 on MPS2 AN521.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-09-22 19:38:51 +02:00
Julien D'Ascenzio
babc6b9e61 soc: arm: stm32[l4|wb]: fix power state exit
When we wake-up of deep sleep power state, we want to disable it.
Otherwise, when the cpu will go next to idle mode during a
SYS_POWER_STATE_ACTIVE, it will go into deep sleep mode
instead of a sleep mode.

fixes: #26896

Signed-off-by: Julien D'Ascenzio <julien.dascenzio@paratronic.fr>
2020-09-21 09:57:40 -05:00
Alexandre Bourdiol
2e1499eb4b soc: arm: st_stm32: stm32f0: take into account SW_VECTOR_RELAY
This STM32 serie redefines function relocate_vector_table()
It should take into account features:
SW_VECTOR_RELAY and SW_VECTOR_RELAY_CLIENT

fixes #28289

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-09-21 11:19:22 +02:00
Joakim Andersson
4cc6098af8 Bluetooth: controller: Select controller features from SoC capabilities
Select the controller feature support for data length and LE 2M PHY
based on the SoC hardware capabilities instead of relying on SoC
family.

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2020-09-18 18:11:35 +02:00
Simon Guinot
fbcaa84a6c soc: lpc11u6x: fix pinmux initialization priority
The commit aac9e2c5e3
("device: Revise how initialization status is being handled") highlights
an initialization priority issue between the clock and pinmux device.
Since this commit Zephyr is not booting anymore on LPC11U6x MCUs. The
clock driver gets a NULL pointer when calling device_get_binding() to
retrieve the pinmux device. It is because the pinmux device is not
initialized yet due to a lesser priority.

This patch fixes this issue by ensuring that Zephyr initializes the
pinmux device before the clock device.

Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
2020-09-14 12:47:32 -05:00
Ioannis Glaropoulos
394d2912a1 arch: arm: cortex-m: implement timing.c based on DWT
For Cortex-M platforms with DWT we implement
the timing API (timing.c).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-09-05 13:28:38 -05:00
Ioannis Glaropoulos
61d1d2ea06 soc: arm: nrf: conditionally employ nRF-specific timing framework
Employ the nRF-specific timing calculations framework
(based on TIMER peripheral) only if the DWT is not present
on the SoC.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-09-05 13:28:38 -05:00
Ioannis Glaropoulos
a681291ef4 soc: arm: nordic nrf: use bitmode-16 for timing measurements in nrf51
nRF51 TIMER2 periperhal does not have the 32-bit
bitmode, so we need to fallback to the bitmode 16.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-09-05 13:28:38 -05:00
Anas Nashif
4b41cb14a8 soc: mec1501: add timing support
Use custom timing implementation specific for this SoC.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-09-05 13:28:38 -05:00
Anas Nashif
a180b33c55 timing: add support for nordic SoCs with RTC timer
Add abstraction for nordic SoCs using Nordic RTC as the source for
timestamps and cycles.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-09-05 13:28:38 -05:00
Gerson Fernando Budke
ab31a2e543 soc: arm: atmel: Introduce sam4l SoC
Introduce SAM4L SoC initial files.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-09-04 16:29:19 -05:00
Jan Kowalewski
36ba3d4abd soc: add EOS S3 SoC
Add basic port for QuickLogic EOS S3 SoC.

Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2020-09-04 14:48:49 -04:00
Francois Ramu
fafb72f8ed drivers: dma: dmamux init needs k_malloc
The dmamux requires HEAP size definition, so that k_malloc
is valid. The HEAP size config is defined in the common for
any stm32 soc instead of specific to dma Kconfig

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2020-09-04 10:42:18 -05:00
Øyvind Rønningstad
77e75eab72 soc: arm: Kconfig: Add more nrf flash protection block sizes
Add
- NRF_MPU_FLASH_REGION_SIZE
- NRF_BPROT_FLASH_REGION_SIZE
- NRF_ACL_FLASH_REGION_SIZE

NRF_SPU_FLASH_REGION_SIZE is already available.

Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2020-09-04 13:38:38 +02:00