Change subsystem to use struct pm_state with substate-id instead of
using only the power state category.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Remove conditionals (PM_DEEP_SLEEP_STATES and PM_SLEEP_STATES) from
power management code. Now these features are always available when
power management is enabled.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Migrate the whole pm subsystem to use new power states information
from power_state.h and get states and residency properties from
device tree.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
PSoC-6 SoC needs that user define the nvic interrupt number to bind
with the peripheral interrupt line for the Cortex-M0+ CPU. It uses
a multiplex before any NVIC interrupt line. The interrupt vector is
selected using interrupt-parent property with the intmux_chN number
reference.
Note: The PSoC-6 SoC allows that both CPUs receive the same interrupt.
A tipical use is GPIO interrupt handle and user is responsable to
define interrupt line, priority and take care of enable same peripheral
instance on both CPUs only when appropriated.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Update <soc.h> include files. This removes the unnecessary
<kernel_includes.h> file. In addition, add <sys/util.h> to
expose macros and <devicetree.h> following general standards.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
This commit add support for i2c on imx6sx.
I2C support is based on imx7d and requires NXP HAL.
The Device Tree binding is also changed to better reflect that i2c
driver support both imx6sx and imx7d.
Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
Part of GPIO pads in npcx series support low-voltage (1.8V) level
detection. In order to introduce this feature, this CL adds a new
NPCX-specific controller property, lvol_io_pads, in devicetree file.
For example, here is devicetree fragment which turn on low-voltage
support of i2c1_0 port.
/ {
def_lvol_io_list {
compatible = "nuvoton,npcx-lvolctrl-def";
lvol_io_pads = <&lvol_io90 /* I2C1_SCL0 1.8V support */
&lvol_io87>; /* I2C1_SDA0 1,8V support */
};
};
Then these pads will turn on 1.8V level detection during initialization.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add some helper macros that will be convenient to use from device
drivers for accessing and error checking pin mux information in the
devicetree:
- NRF_DT_GPIOS_TO_PSEL(): converts a devicetree GPIO phandle
<&gpioX pin flags> to the "PSEL style" registers found in
nRF SoC family IPs. The conversion is done at
build time and relies on devicetree properties.
- NRF_DT_CHECK_GPIO_CTLR_IS_SOC(): make sure a GPIO controller
in a phandle-array property is one of the SoC GPIO controllers
by checking its compatible is nordic,nrf-gpio.
See comments in the patch for more details.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
In npcx7 series, the Timer and Watchdog module (TWD) generates the
clocks and interrupts used for timing periodic functions in the system.
It also provides watchdog reset signal generation in response to a
failure detection.
The CL also includes:
— Add npcx watchdog device tree declarations.
— Zephyr watchdog api implementation.
— Add Watchdog definitions for npcx7 series in
tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c for
supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Sets the device tree chosen node for instruction tightly coupled memory
(ITCM) on all i.MX RT boards. Leverages the common Cortex-M linker
section instead of the SoC-specific one.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds missing DTCM_ADDR and CCM_ADDR macros needed by the linker script
generated by scripts/gen_relocate_app.py.
Moves associated bss_end, noinit_end, and data_end linker symbols to
account for section relocation. Without this change, the section sizes
calculated in z_bss_zero() and z_data_copy() are incorrect.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
STM32L152xC SoC differs from other L1 SoCs in RAM (32KiB) and
flash (256KiB) size, EEPROM size (8Kib) and amount of interrupts
(57, see STM32Cube). Devicetree and Kconfig support.
Signed-off-by: Noelle Clement <noelleclement@hotmail.com>
Add check that validates that the base addresses specified in DT nodes
representing the ECB peripheral match the addresses of that peripheral
defined in MDK.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
All other silabs_exx32 socs already have this change applied, only
efr32bg13p was missing. This is now done, so all silabs_exx32 are
similar.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
In order to simplify the handling of DMA_STM32_V1/V2 and DMAMUX_STM32
symbols, set them directly based on related compatible status.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Cnfigures the LPC55xxx SoC with dual-core (first core boots the second)
and enables the on-SoC mailbox to handle inter-core communication.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
The STM32F105xx is effectively an STM32F107xx without Ethernet. As such,
it's possible to include the STM32F105's device tree from STM32F107, and
add in any additional nodes (currently just DMA2, though according to
the datasheet, this may be supported by the STM32F105xx and other parts
too).
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Leftover from old renaming commits. This function is not private and
should not start with underscore.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Some SoCs try to select power management in a way that can bypass the
dependency on system clock. Make the selection conditional on the
dependency.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The NPCX SMB modules provides full support for a two-wire SMBus/I2C
synchronous serial interface. Each SMBus/I2C interface is a two-wire
serial interface that is compatible with both Intel SMBus and Philips
I2C physical layer. There are 8 SMBus modules and 10 buses in NPCX7
series.
In NPCX7 series, the SMB5 and SMB6 modules contain a two-way switch to
support two separate SMBus/I2C buses (ports) with one SMB module
(controller) Please refer Section 4.7.2 in the datasheet. In order to
support it, this CL seperates the i2c driver into port and controller
drivers. The controller driver is in charge of i2c module operations
and internal state machine. The port driver is in charge of pin-mux
and connection between Zehpyr i2c api interface and controller driver.
All of modules have separate 32-byte transmit FIFO and 32-byte receive
FIFO buffers. These FIFO buffers reduce firmware overhead during long
SMBus transactions by allowing the Core to write or read more than one
data byte at a time to/from the SMB module.
The CL also includes:
— Add npcx i2c port/controller device tree declarations.
— Zephyr i2c api implementation.
— Add "i2c-0" aliases in npcx7m6fb.dts for i2c test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
The System Glue module includes the three major functions:
— Power Switch Logic (PSL)
— SMBus multi-bus, wake-up support
— Simple Debug Port (SDP)
In NPCX7 series, the SMB5 and SMB6 modules contain a two-way switch to
support two separate SMBus/I2C buses (ports) with one SMB module
(controller). Since a single SMB module is able to serve only one
SMBus/I2C bus at a time, SMB_SEL registerin Glue module is used to
control theconnection of I2Cn_0 and I2Cn_1 interface pins to the SMBn
module (where n is 5, 6).
This CL provides a soc specific pin-control function called
"soc_pinctrl_i2c_port_sel" to switch buses (port) of the same SMB module
(controller). It will be used in the following i2c driver.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This CL introduces two kinds of op codes for espi_api_lpc_read_request
and espi_api_lpc_write_request Zephyr espi api functions.
One is for supporting ACPI and shared memory region to access ACPI data.
The other is customized for certain platforms such as Chromebook and so
on.
This CL also introduced the following configurations to add the
flexibility of these settings.
1. ESPI_PERIPHERAL_ACPI_SHM_REGION_PORT_NUM:
Host I/O peripheral port number for shared memory region. The default
value is default 0x0900
2. ESPI_NPCX_PERIPHERAL_ACPI_SHD_MEM_SIZE:
Host I/O peripheral port size for shared memory in npcx series.
Please notice the valid value in npcx ec series for this option is
8/16/32/64/128/256/512/1024/2048/4096 bytes. The default value is 256
bytes.
This CL also turn off hardware-wire feature which generates VW events
that connected to hardware signals such as SMI and SCI. We will set
VW output events directly via espi_api_send_vwire() api function.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Musca-S1 is a Cortex-M33 based SoC. It's similar to the
Musca-B1, but among other things the embedded flash has
been replaced with embedded MRAM (eMRAM) memory.
The Musca-S1 files have been created based on the Musca-B1
SoC and board files.
Add the Musca-S1 board to the list of allowed platforms
for the TF-M integration examples.
Change-Id: I4f517d28d0a5b8c4a3fc3fab73adb5519acfc3c2
Signed-off-by: David Vincze <david.vincze@linaro.org>
This commit adds the soc config for the STM32F303x8.
Add the STM32F303x8 as choice to the Kconfig.soc.
Fixing indention error in Kconfig.soc.
Signed-off-by: Sebastian Schwabe <sebastian.schwabe@mailbox.tu-dresden.de>
Set rom offset to 0x400 if application is compiled with
CONFIG_BOOTLOADER_MCUBOOT.
Please note that mcuboot is not yet supported on stm32h7 devices
Signed-off-by: Nicolas VINCENT <nicolas.vincent@vossloh.com>
Fix TIMER0 and RTC0 being selectable when using out-of-tree Bluetooth
controller.
Generalize the Kconfig to have the features that use the HW peripheral
select them as reserved to make the dependencies more manageable.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
- Remove SYS_ prefix
- shorten POWER_MANAGEMENT to just PM
- DEVICE_POWER_MANAGEMENT -> PM_DEVICE
and use PM_ as the prefix for all PM related Kconfigs
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This CL replaces all DT_ prefix with NPCX_DT_ for all macros used
for providing npcx device information in soc_dt.h It avoided the
ambiguity with the DT_ prefix for system DT macros/defines.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
As best any of us could figure this was intended to indicate that the
macro is a function to be passed to UTIL_LISTIFY.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Set rom offset to 0x400 if application is compiled with
CONFIG_BOOTLOADER_MCUBOOT.
Please note that mcuboot is not yet supported on stm32h7 devices
Signed-off-by: Nicolas VINCENT <nicolas.vincent@vossloh.com>
NPCX7 includes a 10-bit resolution Analog-to-Digital Converter (ADC). Up
to 10 voltage inputs can be measured and a internal voltage reference
(VREF), 2.816V (typical) is used for measurement. It can be triggered
automatically in Autoscan mode. Each input channel is assigned a
separate result register, which is updated at the end of the conversion.
The CL also includes:
— Add npcx adc device tree declarations.
— Zephyr adc api implementation.
— Add adc definitions of npcx7 in
tests/drivers/adc/adc_api/src/test_adc.c for supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
STM32H753xx is similar to STM32H743xx except that it has crypto/hash
hardware acceleration and the memory configuration is always 2Mbytes
flash and 1Mbyte RAM.
Signed-off-by: Petri Oksanen <petri@iote.ai>
