According to RM0041.pdf clock tree for stm32f100xx devices is
different from both STM32F10X density and connectivity lines devices,
but is a combination of both.
Rework symbols definitions so that STM32F100xx is neither of those
and uses:
- CLOCK_STM32_PLL_MULTIPLIER as on SOC_STM32F10X_DENSITY_DEVICE
- CLOCK_STM32_PLL_PREDIV1 as on SOC_STM32F10X_CONNECTIVITY_LINE_...
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Fixes an issue with mcuboot where the SoC will freeze when the dpll is
disabled since `atmel_samd_init` was already run in the bootloader.
Signed-off-by: Abram Early <abram.early@gmail.com>
During configuring the low-voltage power supply of IO pads, the npcx
GPIO driver needs to set the related PORTx_OUT_TYPE bit to 1, i.e.
select to 'Open Drain IO type', also. This CL provides a mechanism that
configuring these bits via 'def-lvol-io-list' node automatically in case
the flag of gpios that have been configured to low-voltage power supply
doesn't contain GPIO_OPEN_DRAIN.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Move the STM32F0 specific ram vector table sections into a dedicated
linker snippet included by the new `SRAM_VECTOR_TABLE` symbol.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add a new Kconfig symbol that explicitly controls whether the vector
table should be placed in RAM. This eliminates the side effect of
`IS_BOOTLOADER` controlling vector table location. Making the condition
a positive assertion also allows the config to be used in CMakeLists
conditions (`zephyr_linker_sources_ifdef()`, etc).
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
The NPCX power management code gets a compile error if CONFIG_PM is
enabled but CONFIG_ARM_MPU is disabled.
Signed-off-by: Keith Short <keithshort@google.com>
It was found that npcx7 series' GPIOs which support low-voltage power
supply, there is an excessive power consumption if they are selected to
low-voltage mode and their input voltage is 1.8V.
To avoid this excessive power consumption, this CL suspends the
connection between IO pads and hardware instances before ec enters deep
sleep mode. Then restore them after waking up.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Fixes#29915.
Implements the memory layout and MPU configuration for Ethernet buffers
for STM32H7 controllers as recommended by ST. 16 KB of SRAM3 are
are reserved for this. The first 256 B are for the RX/TX descriptors and
configured as strongly ordered, shareable memory. The rest is for RX/TX
buffers and configured as non cacheable memory. This configuration is
automatically applied for H7 chips if the SRAM3 memory is enabled in the
device tree.
Signed-off-by: Mario Jaun <mario.jaun@gmail.com>
Optionally configure Kconfig SYS_CLOCK_HW_CYCLES_PER_SEC using
clock-frequency provided by dt if sysclk node is enabled
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
To allow transition to device tree based clock configuration on
stm32 targets, rework clock_control driver to use intermediate
STM32_ macros initially defined as the equivalent Kconfig macros
for now.
Propagate the change in all code using these macros.
The reason to introduce these new macros instead of configuring
Kconfig flags using dt kconfigfunctions is that we'll need
to be able to inform users that Kconfig flags are deprecated
once the whole family conversion is done, to encourage
out of tree users to adopt this new configuration scheme.
Note: For now STM32H7 series and code is excluded.
This is the same for some series specific code such as
PLL mul/div for L0/L1 and XTRE prescaler on F1 series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This CL adds a override mechanism for pwm module's input clock source
assignment. If the 'clock-bus' property exists, the NPCX_DT_PROP_ENUM_OR
macro function will return an enum upper token value. Otherwise, it
expands to default value in 'clocks' property.
For example, if the users want to select LFCLK as pwm0's input clock,
ths node can be overridden by adding 'clock-bus' property with an enum
string, "NPCX_CLOCK_BUS_LFCLK".
&pwm0 {
status = "okay";
clock-bus = "NPCX_CLOCK_BUS_LFCLK";
};
Signed-off-by: Keith Short <keithshort@google.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Kconfig symbol NFCT_PINS_AS_GPIOS may be defined for all
Nordic nRF SoCs that have the NFCT hardware, so we move
the option definition in nRF common Kconfig file. Also,
we correct the help text to reflect that nRF52 series DKs
and nRF5340 DK have different pins for NFC.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds the soc config for the STM32F031k6 and STM32F031X6.
Add the STM32F031k6 as choice to the Kconfig.soc.
Signed-off-by: Sebastian Schwabe <sebastian-schwabe@gmx.de>
NPCX host access IRQ enables before entering deep sleep. The pending
bit lets chip wake up from sleep immediately. Clear host access IRQ
pending bit before enabling.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Most of the Renesas RCar Gen3 based SoC contains a Cortex R7
processor.
This processor has access to the same memory mapped devices than
the Cortex-A5x cores.
- CPU operates upto 800MHz
- Can use ram area from 0x40040000 to 0x42000000
- Has 512 interrupts on GIC-400 compliant with Arm GICv2
Add support for r8a77951 as first SoC of this series which is also
known as H3 ES2.0 and is present present on different boards such as
Salvator and R-Car Starter Kit(H3ulcb).
This first SoC definition is just enough to print Hello World in a
ram console.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
The bootloader application itself should contain the IVT/DCD
in the header, but the chainable application doesn't.
The ROM_START_OFFSET defaults to 0x400 otherwise the linker
alignment isn't taken into account.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
This change allows writing to the flash while running in XIP mode,
and enables mcuboot or NVS settings to be used on i.MX RT socs.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Move the definition of the two IPC RAM blocks from `#define`'s in family
linker scripts to proper devicetree nodes. Use the devicetree nodes to
generate the memory regions.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
The final else was missing in the if ... else if ... construct.
This commit adds a non-empty else {} to comply with coding
guideline 15.7.
Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
Fixed the name of nodes in in espi-vw, miwu-wui, and miwu-int
device-tree node. This CL fixed missing nodes in CL d3a94fa8ab.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Change the GPIO_MMIO32_INIT to take a devicetree node since we want
to use DEVICE_DT_DEFINE. This makes it so that code using
GPIO_DT_SPEC_GET works correctly with GPIO controllers that utilize
GPIO MMIO32.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
With this patch, the UCPD1 _CC1 and _CC2 pins
are disabling the USB Type-C and Power Delivery Dead Battery.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
With this patch, the UCPD1 _CC1 and _CC2 pins
are disabling the USB Type-C and Power Delivery Dead Battery.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
With this patch, the UCPD1 _CC1 and _CC2 pins
are disabling the USB Type-C and Power Delivery Dead Battery.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This CL adds support for console expired mechanism. It implements the
notification to power management module that the module for console is
in use. If the interval that module doesn't receive any input message
exceeds CONFIG_SOC_POWER_CONSOLE_EXPIRED_TIMEOUT, the power management
module is allowed to enter deep sleep mode. This mechanism gives a
window in which the users can organize console input.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Fixed the name of nodes in device-tree files by following rules:
If object is 'phandles', use underscores for object name.
If not, such as 'node' or 'property', use hyphens for object name.
This CL also applies normal style for all nodes in npcx device-tree
files.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The Write Protect pin of the internal SPI flash can be controlled by
WP_IF bit in DEV_CTL4 register. Add functions to set/get the status of
WP pin.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I8a0ce131f006f919a3b38a65722d0d312314ff0a
Initially the flexspi device only supported a flash driver for
external NOR flash. As the controller supports HyperBus devices,
which can be either volatile or non-volatile, the driver iss moved
to drivers/memc.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
soc/arm/st_stm32/CMakeLists.txt already has a
zephyr_include_directories(common) so including in again
soc/arm/st_stm32/common/CMakeLists.txt is redudant.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Use a combination of fixed-clock and fixed-factor-clock devicetree
nodes for describing the clock dividers/multipliers of the NXP Kinetis
System Clock Generator (SCG) present in the KE1xF SoC series.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Split ARM and ARM64 architectures.
Details:
- CONFIG_ARM64 is decoupled from CONFIG_ARM (not a subset anymore)
- Arch and include AArch64 files are in a dedicated directory
(arch/arm64 and include/arch/arm64)
- AArch64 boards and SoC are moved to soc/arm64 and boards/arm64
- AArch64-specific DTS files are moved to dts/arm64
- The A72 support for the bcm_vk/viper board is moved in the
boards/bcm_vk/viper directory
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The compiler shows the array bounds warning message for some boards
which don't set the PSL function.
Change npcx_pinctrl_psl_input_asserted() input parameter from int to
uint32_t to fix it.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
The low power states 0∕1∕2 are added to the stm32wb.
The substate-id is mapping the same Zephyr power state.
They correspond to the stm32wb low power stop0/1/2 modes.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The debug config will let the clocks active in STOP mode
at init.
The substate-id is mapping the same Zephyr power state.
Plus a minor fix in the Kconfig.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The low power modes are available on the stm32l5 soc
with the mcu STOP0/1/2 modes, depending on the CONFIG_PM
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The low power states 0∕1∕2 are added to the stm32l4.
The substate-id is mapping the same Zephyr power state.
They correspond to the stm32l4 low power stop0/1/2 modes.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Hex firmware file is flashed by default if JLink is used. Since all
of the SiLabs dev boards have an on-board JLink, enable generating hex
file.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
This CL introduces the implementation of configurating PSL input pads
and setting PSL_OUT to inactive level for ultra-low power consumption.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces the Power Switch Logic (PSL) pads which detect the
wake-up events and turn on/off core power supply (VCC1) for ultra-low
-power consumption in npcx device-tree file.
By adding PSL input-pad objects, psl_in1, psl_in2, and so on, into
'psl-in-pads' property and configuring their 'flag' properties, the
related driver will configure them via soc specific functions later.
For example, if PSL input 1 pad that is plan to detect a 'falling edge'
event, this property should be:
vsby-psl-in-list {
psl-in-pads = <&psl_in1>;
};
And the flag property in psl_in1 should change to
&psl_in1 {
flag = <NPCX_PSL_FALLING_EDGE>;
};
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
PWR clock is required for various operations.
It is enabled by default in clock control driver,
but disabled at clock init.
It appears soc init is run after clock control driver init
and hence PWR is disabled to to this piece of code at
soc init level.
Don't disable PWR here.
(But keep PWR clock enable in case of ...).
A whole clock clean up will be required later on,
but waiting for that to happen, this is the safest we can do.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This config CPU_CORTEX_M_HAS_DWT, is to avoid the
pragma message "Null-Pointer exception detection cannot
be configured on un-mapped flash areas"
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The AN547 is a Soft Macro Model implementation of the SSE-300 subsystem
with Ethos-U55 and Cortex-M55 components targeting the MPS3 board.
The SoC support is based on the AN521 MPS2+ support that already exists
in Zephyr.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In NPCX chips, System Configuration module can configure not only
pinctrl but also misc. functionality such as glue and flash write
protection. This change moves the scfg driver from the pinctrl folder
to soc/arm/nuvoton_npcx/common and renames it to avoid confusion.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This CL solves an interrupt storm caused by plenty of host access
messages when system is in S0. It only turns on the host access
interrupt before ec enters sleep and turns it off after leaving
sleep.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add SoC support to enable Cypress PSoC-6 pinctrl. This add devicetree
macros to handle pinctrl nodes and SoC GPIO methods to configure pins.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
CORTEX_M_SYSTICK should be disabled if LPTIM is selected.
Current implementation is not efficient to do so.
Rework the way the dependency is stated.
Fixes#33342
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add GPIO driver for QuickLogic EOS S3 SoC.
Co-authored-by: Jan Kowalewski <jkowalewski@antmicro.com>
Signed-off-by: Wojciech Tatarski <wtatarski@antmicro.com>
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
In some stm32 series systick was disabled in order to
allow alternate use of lptim timer as kernel low power ticker.
Doing this, dts based definition of CORTEX_M_SYSTICK Kconfig symbol
is disabled and CORTEX_M_SYSTICK was redefined with 'default y'
in stm32 soc files which makes things more complex to handle to
alternate with LPTIM activation.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This CL prevents changing data content in the write function of host
interface by declaring it as constant pointer.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
All users of ATMEL_SAM0_DT_INST_DMA_NAME are now using
ATMEL_SAM0_DT_INST_DMA_CTLR so we can remove the macro.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a macro similar to ATMEL_SAM0_DT_INST_DMA_NAME but instead
provides the devicetree node back via DT_INST_DMAS_CTLR_BY_NAME
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Use kinetis SIM clock divider options set in device tree
instead of hardcoded values.
The kl25z device tree did not previously define a MCG node.
This has now been added with the general "nxp,kinetis-mcg"
binding.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Use kinetis SIM clock divider options set in device tree
instead of kconfig.
The kv5x device tree originally used the undefined
"nxp,kv58-mcg" binding for the MCG node. This has been
replaced by the general "nxp,kinetis-mcg" binding.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Use kinetis SIM clock divider options set in device tree
instead of kconfig.
Both the kw40z and kw41z device tree originally used an
undefined "nxp,kw41z-mcg" binding for the MCG node.
This has been replaced with the general "nxp,kinetis-mcg"
binding instead.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
SYSCLK_DEFAULT_IOSC_HZ and BUSCLK_DEFAULT_IOSC_HZ are
not used anywhere in the tree and can be removed
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
New power states have more granularity than deep sleep and sleep
states. Just get rid of this and keep the same behavior for now.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Maximum GIC SPI is 228, so maximum INTID is 228 + 32 = 260.
So, _sw_isr_table needs to support 260 entries
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Update register addresses and NVIC/GIC interrupt numbers
according to the latest viper RTL version.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
There is no strict reason to use assembly for the reset routine. Move as
much code as possible to C code using the proper helpers.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The name for registers and bit-field in the cpu.h file is incoherent and
messy. Refactor the whole file using the proper suffixes for bits,
shifts and masks.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Enable the driver for the Kinetis Digital-to-Analog (DAC) modules
present in the NXP Kinetis K2x SoC series.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Add some helper macros that will be convenient to use from device
drivers for accessing and error checking pin mux information in the
devicetree:
- NRF_DT_PSEL(): get a PSEL value out of the DT from either a
'foo-pin' or a 'foo-gpios' style property.
- NRF_DT_PSEL_CHECK_NOT_BOTH(), NRF_DT_PSEL_CHECK_EXACTLY_ONE():
helpers for checking that a given devicetree is OK according to
different criteria for setting PSEL properties (NAND or XOR on
whether the properties exist, respectively).
See comments in the patch for more details.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add the declaration and check of debug interface register.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: Ib8ecd53f1d6139613f39243aee83bdd75a30f5be
In NPCX7 series, it contains two tachometer (TACH) modules that contains
two Independent timers (counter 1 and 2). They are used to capture a
counter value when an event is detected via the external pads (TA or
TB).
The CL also includes:
— Add npcx tachometer device tree declarations.
— Zephyr sensor api implementation for tachometer.
— Enable "tach1" device in npcx7m6fb.dts for testing.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Since the uart device clock will be stopped after ec entered sleep or
deep sleep state and restore its clock automatically, there is no need
to implement code for suspending and resuming devices manually.
The driver still needs to check the current status of uart device when
it wants to change its power state to LOW or SUSPEND power state. It is
crucial to forbid ec enters sleep or deep sleep state when uart device
is busy with transmitting data. Or we will observe broken characters on
the uart console.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces power management driver that improves the efficiency
of ec operation by adjusting the chip’s power consumption to the level
of activity required by the application in npcx series.
The following list summarizes the main properties of the various chip
power states. Please refer the power.c file for more detail.
Main power states in npcx series include:
- Active: Core, RAM and modules operate at the clocks generated by PLL.
- Idle: Enter this state when the Core executes WFI or WFE instruction.
- Sleep: clock is stopped for most of modules but PLL is enabled.
- Deep Sleep: As Sleep mode but PLL is disabled.
- Standby: All power rails are turned off besides standby and battery
power rails.
And this CL implements one power state, PM_STATE_SUSPEND_TO_IDLE, with
two sub-states for Zephyr power management system.
Sub-state 0 - "Deep Sleep" mode with “Instant” wake-up if residency
time is greater or equal to 1 ms
Sub-state 1 - "Deep Sleep" mode with "Standard" wake-up if residency
time is greater or equal to 201 ms
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces a kernel device driver implemented by the internal
64/32-bit timers in Nuvoton NPCX series. Via these two kinds of timer,
the driver provides an standard "system clock driver" interface.
It includes:
- A system timer based on an ITIM64 (Internal 64-bit timer) instance,
clocked by APB2 which freq is CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
- Its prescaler is set to 1 and provide the kernel cycles reading
without handling overflow mechanism.
- A event timer based on an ITIM32 (Internal 32-bit timer) instance,
clocked by LCLK which frequency is 32KHz and still activated when ec
entered "idle/deep idle" power state for better power consumption.
- Its prescaler is set to 1 and provide timeout event mechansim.
- Compensate system timer which clock is gating for better power
consumption after ec left"idle/deep idle" power state.
This CL passed starve, timer_api, and timer_monotonic test suites.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
stm32wb and stm32l4 are devices which supports the low power
from the Kernel PM, so is the PM_DEVICE defined.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In case the policy is not available or defined by th application
the pm_policy_low_power_devices is still valid
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The clock configuration is restored by the stm32_clock_control_init
function of the clock_stm32_ll_common driver
when exiting the low power mode
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In case the policy is not available or defined by th application
the pm_policy_low_power_devices is still valid
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The clock configuration is restored by the stm32_clock_control_init
function of the clock_stm32_ll_common driver
when exiting the low power mode.
Keeping the stm32wbxx_ll_utils.h in case the PLL is used for wb.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Erratum 19 applies to earlier revisions of nRF5340 DK,
which are no longer supported in the tree, so we can
remove the code that handles it.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add Kconfig options to signify that the nRF5340
HW has support for QDEC instances. Select the
options in the nRF5340 Application core definition.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This driver missed #32228 PR that converted STM32 drivers
to use DEVICE_DT_GET for clock activation.
Due to the renaming of STM32_CLOCK_CONTROL_NAME to
STM32_CLOCK_CONTROL_NODE, driver could not compile anymore
Fix this.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Remove support for the Musca-A board. This board is rarely used, few
are available and superceded by Musca-B and Musca-S.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The NPCX clock driver was already using devicetree, just need to make a
small tweak to use DEVICE_DT_INST_DEFINE and update NPCX_CLK_CTRL_NAME
to match the label for the "nuvoton,npcx-pcc" clock controller.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add ESPI SAF features to the Microchip eSPI driver as
a separate file. ESPI SAF depends upon the core eSPI
driver adding the ability to attach the system SPI
flash to the EC eSPI endpoint instead of the host
eSPI controller.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
When exiting Stop mode, if system clock is MSI, MSI oscillator is
selected as wakeup from stop clock; otherwise HSI16 oscillator is
selected.
Signed-off-by: Giancarlo Stasi <giancarlo.stasi.co@gmail.com>
nxp_k2x.dtsi: Corrects Multipurpose Clock Generator binding
to utilize nxp,kinetis-mcg. Assign MCG to FlexTimer devices.
Enable FlexTimer clocks via System Integration Module clock
gate control registers.
Kconfig.defconfig.mk22f12: Enable default use of
CLOCK_CONTROL_MCUX_MCG when CLOCK_CONTROL is selected.
Signed-off-by: Ryan Holleran <rhollerar@gmail.com>
In this CL, npcx_miwu_interrupt_configure is no longer responsible for
turning the interrupt off. Although the default state of WK_EN is
disabled, the users still have the chance to configure them when WK_EN
is enabled via npcx_miwu_irq_enable(). Hence, this CL also ensures that
WK_EN is disabled before configuring them.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Simplify pm subsystem removing PM_STATE_LOCK option. Constraints API is
small and is a key component of power subsystem.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This activates spi support for this soc. Closes#26428
```tests/drivers/spi/spi_loopback``` succeeded.
Signed-off-by: Bernhard Krämer <bdkrae@gmail.com>
Add support for backup SRAM initialization found in multiple STM32
microcontrollers. Linker script facilities are also provided to make it
easy to define variables in the backup SRAM.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This was merged by mistake without being tested and is not working
properly. We need to avoid doing a BUILD_ASSERT() when the relevant
property is missing, because we can't use DT_GPIO_CTLR() on an
undefined property. Handle this with COND_CODE_1().
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
According to https://www.arm.com the correct spelling is now "Arm".
Change the Kconfig input prompts to comply.
Signed-off-by: Detlev Zundel <dzu@member.fsf.org>
This is a trivial patch replacing the spaces at the beginning of the
line with tabs. Otherwise checkpatch will not be happy with any
changes in here.
Signed-off-by: Detlev Zundel <dzu@member.fsf.org>
The STM32F2x was the only one of the STM32 series with a lowercase
input prompt. This looks odd in the SoC selection in 'menuconfig'.
Signed-off-by: Detlev Zundel <dzu@member.fsf.org>
Rather than Kconfig vendor symbols, select stm32 watchdog using
compatible.
So user only has to enable the requested node and set
CONFIG_WATCHDOG=y.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This CL added more additional details for KBC (Keyboard and Mouse
Controller) bus in espi_event structure. It helps the application to
handle different 8042 events in the callback function.
The format of event data for KBC 8042 protocol is:
[23:16] - 8042 event type: 1: Input buf full, 2: Output buf empty.
[15:8] - 8042 data: 8-bit 8042 data.
[0:7] - 8042 protocol type: 0: data type, 1: command type.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The network core doesn't have access to the regulators necessary to
support system power management. That has to be done on the
application core.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This reverts commit f38ba314ea.
nrf5340dk_nrf5340_cpunet doesn't support power management, but that
should be handled another way.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The soft off power state should be supported as it is closest to what
used to be deep sleep state 1, which corresponds to the device off
state supported by hardware.
Fixes#31727.
Signed-off-by: Vincent Wan <vanti.coder@gmail.com>
Based upon discussions with HW designers the 32KHz
programming sequence can be simplified. When FW writes
a value to the VBAT 32KHz Clock Enable register HW checks
if the value is the same as the current value. If the same
the HW does nothing. If different HW begins a sequence to
switch off the current 32KHz source, revert to ring oscillator,
and switch to the new source. FW should program the new value
and then spin until the PCR OSC ID PLL Lock bit goes to 1.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This commit adds minimal support for running zephyr as Xen guest. It
does not use xen PV console, which is somewhat hard to implement, as it
depends on xenbus infrastructure. Instead SBSA-compatible PL011 uart is
used.
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Enables the FlexSPI flash driver on the i.MX RT SoC family and
configures the peripheral clocks accordingly. We are careful to only
configure the peripheral clocks if we are not executing in place from
the FlexSPI flash.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds a hidden config symbol HAS_MCUX_FLEXSPI selected by NXP SoCs when
the FlexSPI peripheral is present. It will be used as a dependency for a
new FlexSPI flash driver to prevent users from accidentally enabling the
driver on platforms that don't have the necessary hardware.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This targets was previously enabling PM but the code was doing nothing
because the logic was under an unsatisfied ifdef condition.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Change subsystem to use struct pm_state with substate-id instead of
using only the power state category.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Remove conditionals (PM_DEEP_SLEEP_STATES and PM_SLEEP_STATES) from
power management code. Now these features are always available when
power management is enabled.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Migrate the whole pm subsystem to use new power states information
from power_state.h and get states and residency properties from
device tree.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
PSoC-6 SoC needs that user define the nvic interrupt number to bind
with the peripheral interrupt line for the Cortex-M0+ CPU. It uses
a multiplex before any NVIC interrupt line. The interrupt vector is
selected using interrupt-parent property with the intmux_chN number
reference.
Note: The PSoC-6 SoC allows that both CPUs receive the same interrupt.
A tipical use is GPIO interrupt handle and user is responsable to
define interrupt line, priority and take care of enable same peripheral
instance on both CPUs only when appropriated.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Update <soc.h> include files. This removes the unnecessary
<kernel_includes.h> file. In addition, add <sys/util.h> to
expose macros and <devicetree.h> following general standards.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
This commit add support for i2c on imx6sx.
I2C support is based on imx7d and requires NXP HAL.
The Device Tree binding is also changed to better reflect that i2c
driver support both imx6sx and imx7d.
Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
Part of GPIO pads in npcx series support low-voltage (1.8V) level
detection. In order to introduce this feature, this CL adds a new
NPCX-specific controller property, lvol_io_pads, in devicetree file.
For example, here is devicetree fragment which turn on low-voltage
support of i2c1_0 port.
/ {
def_lvol_io_list {
compatible = "nuvoton,npcx-lvolctrl-def";
lvol_io_pads = <&lvol_io90 /* I2C1_SCL0 1.8V support */
&lvol_io87>; /* I2C1_SDA0 1,8V support */
};
};
Then these pads will turn on 1.8V level detection during initialization.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add some helper macros that will be convenient to use from device
drivers for accessing and error checking pin mux information in the
devicetree:
- NRF_DT_GPIOS_TO_PSEL(): converts a devicetree GPIO phandle
<&gpioX pin flags> to the "PSEL style" registers found in
nRF SoC family IPs. The conversion is done at
build time and relies on devicetree properties.
- NRF_DT_CHECK_GPIO_CTLR_IS_SOC(): make sure a GPIO controller
in a phandle-array property is one of the SoC GPIO controllers
by checking its compatible is nordic,nrf-gpio.
See comments in the patch for more details.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
In npcx7 series, the Timer and Watchdog module (TWD) generates the
clocks and interrupts used for timing periodic functions in the system.
It also provides watchdog reset signal generation in response to a
failure detection.
The CL also includes:
— Add npcx watchdog device tree declarations.
— Zephyr watchdog api implementation.
— Add Watchdog definitions for npcx7 series in
tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c for
supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Sets the device tree chosen node for instruction tightly coupled memory
(ITCM) on all i.MX RT boards. Leverages the common Cortex-M linker
section instead of the SoC-specific one.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds missing DTCM_ADDR and CCM_ADDR macros needed by the linker script
generated by scripts/gen_relocate_app.py.
Moves associated bss_end, noinit_end, and data_end linker symbols to
account for section relocation. Without this change, the section sizes
calculated in z_bss_zero() and z_data_copy() are incorrect.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
STM32L152xC SoC differs from other L1 SoCs in RAM (32KiB) and
flash (256KiB) size, EEPROM size (8Kib) and amount of interrupts
(57, see STM32Cube). Devicetree and Kconfig support.
Signed-off-by: Noelle Clement <noelleclement@hotmail.com>
Add check that validates that the base addresses specified in DT nodes
representing the ECB peripheral match the addresses of that peripheral
defined in MDK.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
All other silabs_exx32 socs already have this change applied, only
efr32bg13p was missing. This is now done, so all silabs_exx32 are
similar.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
In order to simplify the handling of DMA_STM32_V1/V2 and DMAMUX_STM32
symbols, set them directly based on related compatible status.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Cnfigures the LPC55xxx SoC with dual-core (first core boots the second)
and enables the on-SoC mailbox to handle inter-core communication.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
The STM32F105xx is effectively an STM32F107xx without Ethernet. As such,
it's possible to include the STM32F105's device tree from STM32F107, and
add in any additional nodes (currently just DMA2, though according to
the datasheet, this may be supported by the STM32F105xx and other parts
too).
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Leftover from old renaming commits. This function is not private and
should not start with underscore.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Some SoCs try to select power management in a way that can bypass the
dependency on system clock. Make the selection conditional on the
dependency.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The NPCX SMB modules provides full support for a two-wire SMBus/I2C
synchronous serial interface. Each SMBus/I2C interface is a two-wire
serial interface that is compatible with both Intel SMBus and Philips
I2C physical layer. There are 8 SMBus modules and 10 buses in NPCX7
series.
In NPCX7 series, the SMB5 and SMB6 modules contain a two-way switch to
support two separate SMBus/I2C buses (ports) with one SMB module
(controller) Please refer Section 4.7.2 in the datasheet. In order to
support it, this CL seperates the i2c driver into port and controller
drivers. The controller driver is in charge of i2c module operations
and internal state machine. The port driver is in charge of pin-mux
and connection between Zehpyr i2c api interface and controller driver.
All of modules have separate 32-byte transmit FIFO and 32-byte receive
FIFO buffers. These FIFO buffers reduce firmware overhead during long
SMBus transactions by allowing the Core to write or read more than one
data byte at a time to/from the SMB module.
The CL also includes:
— Add npcx i2c port/controller device tree declarations.
— Zephyr i2c api implementation.
— Add "i2c-0" aliases in npcx7m6fb.dts for i2c test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
The System Glue module includes the three major functions:
— Power Switch Logic (PSL)
— SMBus multi-bus, wake-up support
— Simple Debug Port (SDP)
In NPCX7 series, the SMB5 and SMB6 modules contain a two-way switch to
support two separate SMBus/I2C buses (ports) with one SMB module
(controller). Since a single SMB module is able to serve only one
SMBus/I2C bus at a time, SMB_SEL registerin Glue module is used to
control theconnection of I2Cn_0 and I2Cn_1 interface pins to the SMBn
module (where n is 5, 6).
This CL provides a soc specific pin-control function called
"soc_pinctrl_i2c_port_sel" to switch buses (port) of the same SMB module
(controller). It will be used in the following i2c driver.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This CL introduces two kinds of op codes for espi_api_lpc_read_request
and espi_api_lpc_write_request Zephyr espi api functions.
One is for supporting ACPI and shared memory region to access ACPI data.
The other is customized for certain platforms such as Chromebook and so
on.
This CL also introduced the following configurations to add the
flexibility of these settings.
1. ESPI_PERIPHERAL_ACPI_SHM_REGION_PORT_NUM:
Host I/O peripheral port number for shared memory region. The default
value is default 0x0900
2. ESPI_NPCX_PERIPHERAL_ACPI_SHD_MEM_SIZE:
Host I/O peripheral port size for shared memory in npcx series.
Please notice the valid value in npcx ec series for this option is
8/16/32/64/128/256/512/1024/2048/4096 bytes. The default value is 256
bytes.
This CL also turn off hardware-wire feature which generates VW events
that connected to hardware signals such as SMI and SCI. We will set
VW output events directly via espi_api_send_vwire() api function.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Musca-S1 is a Cortex-M33 based SoC. It's similar to the
Musca-B1, but among other things the embedded flash has
been replaced with embedded MRAM (eMRAM) memory.
The Musca-S1 files have been created based on the Musca-B1
SoC and board files.
Add the Musca-S1 board to the list of allowed platforms
for the TF-M integration examples.
Change-Id: I4f517d28d0a5b8c4a3fc3fab73adb5519acfc3c2
Signed-off-by: David Vincze <david.vincze@linaro.org>
This commit adds the soc config for the STM32F303x8.
Add the STM32F303x8 as choice to the Kconfig.soc.
Fixing indention error in Kconfig.soc.
Signed-off-by: Sebastian Schwabe <sebastian.schwabe@mailbox.tu-dresden.de>
Set rom offset to 0x400 if application is compiled with
CONFIG_BOOTLOADER_MCUBOOT.
Please note that mcuboot is not yet supported on stm32h7 devices
Signed-off-by: Nicolas VINCENT <nicolas.vincent@vossloh.com>
Fix TIMER0 and RTC0 being selectable when using out-of-tree Bluetooth
controller.
Generalize the Kconfig to have the features that use the HW peripheral
select them as reserved to make the dependencies more manageable.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
- Remove SYS_ prefix
- shorten POWER_MANAGEMENT to just PM
- DEVICE_POWER_MANAGEMENT -> PM_DEVICE
and use PM_ as the prefix for all PM related Kconfigs
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This CL replaces all DT_ prefix with NPCX_DT_ for all macros used
for providing npcx device information in soc_dt.h It avoided the
ambiguity with the DT_ prefix for system DT macros/defines.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
As best any of us could figure this was intended to indicate that the
macro is a function to be passed to UTIL_LISTIFY.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Set rom offset to 0x400 if application is compiled with
CONFIG_BOOTLOADER_MCUBOOT.
Please note that mcuboot is not yet supported on stm32h7 devices
Signed-off-by: Nicolas VINCENT <nicolas.vincent@vossloh.com>
NPCX7 includes a 10-bit resolution Analog-to-Digital Converter (ADC). Up
to 10 voltage inputs can be measured and a internal voltage reference
(VREF), 2.816V (typical) is used for measurement. It can be triggered
automatically in Autoscan mode. Each input channel is assigned a
separate result register, which is updated at the end of the conversion.
The CL also includes:
— Add npcx adc device tree declarations.
— Zephyr adc api implementation.
— Add adc definitions of npcx7 in
tests/drivers/adc/adc_api/src/test_adc.c for supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
STM32H753xx is similar to STM32H743xx except that it has crypto/hash
hardware acceleration and the memory configuration is always 2Mbytes
flash and 1Mbyte RAM.
Signed-off-by: Petri Oksanen <petri@iote.ai>
Include generic header stm32_ll_hsem.h from stm_hsem.h (which is used
by multiple drivers) instead of depending on soc.h.
Signed-off-by: Martin Jäger <martin@libre.solar>
The current SAM4S define at board level common flags that should be on
soc defines. Add common flags at SoC Kconfig defines and drop the
correspondent at board defines.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current SAM4E define at board level common flags that should be on
soc defines. Add common flags at SoC Kconfig defines and drop the
correspondent at board defines.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add separated Kconfig file for Bluetooth 5.1 Direction Finding.
Enable controller support for:
- transmission of CTE
- 2us antenna switching
- 1us antenna switching
if build for nRF52833 SOC.
Add HAS_HW_NRF_RADIO_BLE_DF to nrf52833 SOC configuration.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
This commit adds a new driver category for memory controller
peripherals. There is no API involved for now, as it has not been found
necessary for first implementation.
STM32 Flexible Memory Controller (FMC) is the only controller supported
for now. This peripheral allows to access multiple types of external
memories, e.g. SDRAM, NAND, NOR Flash...
The initial implementation adds support for the SDRAM controller only.
The HAL API is used, so the implementation should be portable to other
STM32 series. It has only been tested on H7 series, so for now it can
only be enabled when working on H7.
Linker facilities have also been added in order to allow applications to
easily define a variable in SDRAM.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Configures i.MX RT SoCs that support cacheable external SDRAM to use the
DTCM linker section for Segger RTT and SystemView data.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The SAM4L have a unique I2C driver. It shares simultaneously pins for
both master and slave controllers. Each controller have their own
instance. This introduces the TWIM controller that handles only the
master part.
The TWIM controller uses no copy and the driver was prepared to work
with both 7 and 10 bits address. The controller can handler up to 256
bytes for a single transfer allowing long data communication with
almost no CPU intervention.
The driver was wrote specifically to Zephyr. It receives a transfer
list of from upper layers to a specific device on the bus. It programs
the first and second transfer, if it exists, before start. At end of
full read/write interrupt, will program the next data block. This
process repeats until all transfers be executed. The driver uses
interrupt from TWIM to check for erros or program next tranfer.
Future work can enable low power mode on the driver allowing long
transfers with low power consumption.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add i2c1 interface for stm32l552xx and stm32l562xx microcontrollers
and enable i2c1 that connects to lsm6dso sensor module on the
stm32l562e_dk board.
Signed-off-by: Yestin Sun <sunyi0804@gmail.com>
Change adds missing TX power dependencies. nRF52833 and nRF52820 SoCs
also support higher TX power values.
Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
1. Code for the power mananagement is available
in source format
2. Increase the core speed to 250MHz.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
These MCUs have 32Kbytes of Flash and 8Kbytes of RAM. They are still
able to run a number of samples.
Signed-off-by: Steven Daglish <s.c.daglish@gmail.com>
In CMakeLists.txt, the MEC1501 specific timing functions are
only compiled if CONFIG_CORTEX_M_DWT=n. However, in SoC's
kconfig, CONFIG_SOC_HAS_TIMING_FUNCTIONS is defaulted to y
unconditionally. This results in the timing subsys looking
for SoC-based timing functions but those are not compiled.
So add a condition to kconfig similar to CMakeLists.txt where
SoC timing functions are only enabled when CONFIG_CORTEX_M_DWT=n.
Fixes#29969
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add a Kconfig option (enabled by default) the enables the low-frequency
oscillator (LFXO) functionality on the XL1 and XL2 pins in the nRF53
SoC initialization routine. This cannot be done in the clock control
driver, as it was done so far, because that won't work in a setup where
the application core image does not use the system clock at all.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Replace direct register accesses in the SoC initialization routine
with proper calls to nrfx HAL functions.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
We should not be initializing/starting/stoping timing functions
multiple times. So this changes how the timing functions are
structured to allow only one initialization, only start when
stopped, and only stop when started.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The nRF5340 (P)DK is equipped with the MX25R64 flash memory. Add a dts
node for that chip in the board definition as well as the missing QSPI
node in the nRF5340 SoC definition.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This change adds IEEE 802.15.4g (Sub GHz) support for the
cc1352r.
The 2.4 GHz radio and the Sub GHz radio are capable of
operating simultaneously.
Fixes#26315
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
The current MMU code is assuming that both kernel and threads are both
running in EL1, not supporting EL0. Extend the support to EL0 by adding
the missing attribute to mirror the access / execute permissions to EL0.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This change reworks the cc13xx_cc26xx IEEE 802.15.4 driver to use
the TI RF driver API that is available in modules/hal/ti.
There are a number of benefits to using TI's API including
- a stable multi-OS vendor library and API
- API compatibility with the rest of the SimpleLink SDK and SoC family
- potential multi-protocol & multi-client radio operation
(e.g. both 15.4 and BLE)
- coexistence support with other chipsets via gpio
- vetted TI RF driver resources, such as
- the radio command queue
- highly tuned / coupled RTC & RAT (RAdio Timer) API
Fixes#26312
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
This qemu device is REALLY slow in icount mode. When I run it outside
of icount and watch the simulator advance the clock device in real
time, it looks to me like it expects the counter to be running at ~125
MHz. But it's set to a 12 MHz clock rate in its config, and trying to
use a 1000 Hz tick rate.
At those settings (and with the shift=3 argument to icount), I'm
measuring about 10k cycles to handle a minimal timer interrupt. But
if you do the math, that comes to 12k cycles per tick. The interrupt
takes as long as a tick! That would never work, except for the fact
that the timer driver on this device cheats and doesn't try to align
to ticks (basically ignoring all the lost time). And even that breaks
on the scheduler_api test (which does both tick and cycle math and
tries to compare them) when it's fixed to properly align itself.
One solution might be to set the clock rate to what qemu appears to
believe is the correct 125 MHz value. And that causes the test to
complete, but all tests now take ~10 minutes of real time because the
simulator is so slow!
So just make up some clock rates, it's a simulated platform after all.
I chose 5 MHz cycle time and 100 Hz tick rate, which on my device is
about half of "real" speed and very acceptable.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Enables the mcux flexcan driver on i.mx rt socs by default when
CONFIG_CAN=y.
This fixes a runtime failure in tests/subsys/canbus/isotp/conformance on
the mimxrt1064_evk board:
Assertion failed at WEST_TOPDIR/zephyr/tests/subsys/canbus/isotp/conformance/src/main.c:883: test_main: (can_dev is NULL)
CAN device not not found
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
With STM32Cube updates
https://github.com/zephyrproject-rtos/hal_stm32/pull/75
'..._hal_rcc.c' and '..._hal_rcc_ex.c' are now systematically
compiled, due to more and more dependencies from HAL IP on rcc.
So USE_STM32_HAL_RCC and USE_STM32_HAL_RCC_EX becomes useless.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Sets the device tree chosen node for data tightly coupled memory (DTCM)
on i.mx rt boards that aren't already using DTCM as the chosen SRAM.
Leverages the common cortex-m linker section instead of the soc-specific
one.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Removes the DATA_LOCATION Kconfig symbol from the i.mx rt soc series and
refactors corresponding boards to use a device tree chosen node instead.
The external SDRAM is chosen on all boards that can support it;
otherwise the internal DTCM is chosen.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Refactors the i.mx rt soc series to enable device configuration data
(DCD) by default when the smart external memory controller (SEMC) is
present. This is in preparation for removing the DATA_LOCATION Kconfig
symbol and using a device tree chosen node instead.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add support for interrupt driven MSI-X PVM feature for Viper.
Function mask bit update is tracked with snoop interrupt
and vector mask bit update is tracked with pcie pmon lite
address range access detection interrupt.
Both the interrupts are required to enable this feature.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Deprecate the Musca-A board and SoC support to be removed in 2.6.0.
There are a number of issues with the Musca-A and there exists both the
Musca-B and Musca-S1.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This defines the TRNG for EFM32GG11 and enables it for trng0
in the dts for the matching development kits.
Signed-off-by: Thorvald Natvig <thorvald@natvig.com>
The WGM160P module combines the WF200 Wi-Fi transceiver with
an EFM32GG11 MCU
This code is based on the efm32gg_stk3701a board definitions
Signed-off-by: Thorvald Natvig <thorvald@natvig.com>
In order to be in line with other DT_INST macros in zephyr code base,
swap the arguments order in following macro definitions:
*ST_STM32_DT_PINCTRL
*ST_STM32_DT_INST_PINCTRL
Update the users accordingly.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
As an alternative to ST_STM32_DT_INST_PINCTRL, provide
ST_STM32_DT_PINCTRL macro and set of matching internal macros.
This could be used by device drivers that can't use directly
device instances but rather the node label identifier. For instance:
ST_STM32_DT_PINCTRL(0, i2c1);
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Current set of helpers provided for STM32 pinctrl devicetree are
using device instance as input.
In order to prepare for next version that will take node identifier
as input, change existing set of macros using _INST_ namespace.
Additionally rename NODE_ID_FROM_PINCTRL to
ST_STM32_DT_INST_NODE_ID_FROM_PINCTRL.
Finally update existing macros users to this new name scheme.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Before adding new macros, clean up existing file:
* Provide full length description for each macro
* Cascade the device instance pinctl- property index so that
any pinctrl- instance number could be used
* Remove intermediate ST_STM32_DT_PIN macro
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The PLL Q divisor does not exist on stm32g0X0 variants. It should only
be configured for g0X1 variants.
Signed-off-by: Eric Hay <EHay@sierrawireless.com>
In npcx7 series, there're 8 Pulse Width Modulator (PWM) modules and each
one support generating a single 16-bit PWM output. A 16-bit clock
prescaler (PRSCn) and a 16-bit counter (CTRn) determine the cycle time,
the minimal possible pulse width, and the duty-cycle steps.
Beside introducing pwm driver for Nuvoton NPCX series, this CL also
includes:
1. Add PWM device tree declarations.
2. Zephyr PWM api implementation.
3. Add aliases in npcx7m6fb_evb board device tree file for supporting
samples/basic/blinky_pwm application and pwm test suites
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Change default pinmux of functional pads to GPIOs. It includes:
1. PIN96.A0.A2.A4 - If internal flash is supported
2. PIND2.00 - Default PSL inputs
3. PIN31.30.27.26.25.24.23.22 - Keyboard inputs
4. PIN21.20.17.16.15.14.13.12.11.10.07.06.05.04.82.83.03.B1 - Keyboard
outputs
5. Add description for soc_pinctrl_mux_configure() usage.
It also fixed the typo and inverse mistakes in npcx7-alts-map.dtsi.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This CL adds more comments for each macro functions used for device tree
file for better explanations. It also changes all hex values in soc.c to
lower case.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This CL contains the drivers of NPCX Host Sub-Modules that serve as an
interface between the Host and Core domains. For most of them, the Host
can configure these modules via eSPI(Peripheral Channel)/LPC by
accessing 'Configuration and Control register Set' which IO base address
is 0x4E as default. And the interrupts in core domain help handling any
events from host side.
In this commit, we introduced six host sub-modules. It includes:
1. Keyboard and Mouse Controller (KBC) interface.
2. Power Management (PM) channels.
3. Shared Memory mechanism (SHM).
4. Core Access to Host Modules (C2H).
5. Mobile System Wake-Up functions (MSWC).
6. Serial Port (Legacy UART)
The tasks in application layer such as 8042, ACPI and host command can
cooperation with this driver by connecting api or callback functions.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
In npcx7 series, all of them support the Intel Enhanced Serial
Peripheral Interface (eSPI) Revision 1.0. This specification provides a
path for migrating host sub-devices via LPC to a lower pin count, higher
bandwidth bus. In addition to Host communication via the peripheral
channel, it provides virtual wires support, out-of-band communication,
and device mastering option over the Chipset SPI flash.
Becisdes introducing eSPI device in npcx7, this CL also includes:
1. Add eSPI device tree declarations.
2. Add npcx7-espi-vws-map.dtsi to present the relationship between eSPI
Virtual-Wire signals, eSPI registers, and wake-up input sources.
3. Zephyr eSPI api implementation.
4, Add OOB (Out of Band tunneled SMBus) support.
5. Add configuration files for eSPI test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Provides tool set to be used by device drivers in order to be able
to configure device signals.
This does not involve the implementation of a dedicated pinctrl
driver. In this regard, this is equivalent to implementation used
for treatment of current pinmux.c files.
Since STM32F1 uses a different GPIO configuration scheme, its
support is exlcuded for now.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32L151xC SoC differs from other L1 SoCs in RAM (32KiB) and
flash (256KiB) size, and amount of interrupts (57, see STM32Cube).
Devicetree and Kconfig support.
Signed-off-by: Noelle Clement <noelleclement@hotmail.com>
Adds imx rt support.
Allows n-number of can interfaces based on device-tree.
Adds a "common" irq name.
Added CAN bus pins and dts for 1060 and 1064 EVK.
Signed-off-by: Rick Talbott <rtalbott@fastmail.com>
The standard and static MMU regions (_code, _rodata and _data) are
already covering all the available SRAM region and all the needed
sections. Remove the overlapping SRAM region.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
We only need to offset the start of the non-secure image
by 0x400, if TFM is built with BL2 support. In this case
we use the ROM_START_OFFSET Kconfig switch and set to
0x400. This instructs the linker to offset the beginning
of the ROM section by 0x400. In other words, we do not need
to statically move the start of the image by 0x400. This
fixes an issue that prevents from running Zephyr + TFM
without BL2 on Musca B1.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We only need to offset the start of the non-secure image
by 0x400, if TFM is built with BL2 support. In this case
we use the ROM_START_OFFSET Kconfig switch and set to
0x400. This instructs the linker to offset the beginning
of the ROM section by 0x400. In other words, we do not need
to statically move the start of the image by 0x400. This
fixes an issue that prevents from running Zephyr + TFM
without BL2 on MPS2 AN521.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
When we wake-up of deep sleep power state, we want to disable it.
Otherwise, when the cpu will go next to idle mode during a
SYS_POWER_STATE_ACTIVE, it will go into deep sleep mode
instead of a sleep mode.
fixes: #26896
Signed-off-by: Julien D'Ascenzio <julien.dascenzio@paratronic.fr>
This STM32 serie redefines function relocate_vector_table()
It should take into account features:
SW_VECTOR_RELAY and SW_VECTOR_RELAY_CLIENT
fixes#28289
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Select the controller feature support for data length and LE 2M PHY
based on the SoC hardware capabilities instead of relying on SoC
family.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
The commit aac9e2c5e3
("device: Revise how initialization status is being handled") highlights
an initialization priority issue between the clock and pinmux device.
Since this commit Zephyr is not booting anymore on LPC11U6x MCUs. The
clock driver gets a NULL pointer when calling device_get_binding() to
retrieve the pinmux device. It is because the pinmux device is not
initialized yet due to a lesser priority.
This patch fixes this issue by ensuring that Zephyr initializes the
pinmux device before the clock device.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
Employ the nRF-specific timing calculations framework
(based on TIMER peripheral) only if the DWT is not present
on the SoC.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
nRF51 TIMER2 periperhal does not have the 32-bit
bitmode, so we need to fallback to the bitmode 16.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The dmamux requires HEAP size definition, so that k_malloc
is valid. The HEAP size config is defined in the common for
any stm32 soc instead of specific to dma Kconfig
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add devicetree support to specify bias-pull-up, bias-pull-down, and
drive-open-drain for pin configuration.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fixed 'line length exceeds 80 columns' warning by shortening the clock
controller device name from NPCX_CLOCK_CONTROL_NAME to
NPCX_CLK_CTRL_NAME.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
The general DMA driver doesn't use kmalloc anymore so it doesn't
need a memory pool. The DMAMUX_SMT32 driver still uses kmalloc,
so move the HEAP_MEM_POOL_SIZE config under DMAMUX_STM32.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
Assuming we stay on default Power Scale 1,
overdrive is required when System Core Clock frequency is higher
than 180MHz.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Most drivers make use of the HW semaphore (see `stm32_gpio.c`), but the
HSEM clock isn't currently setup on the MCU side. This means we rely on
the MPU to enable this clock, which is an unsafe bet: the OS running on
the MPU may not have support for HSEM, or it might enter sleep state,
which will disable the clock. As a consequence, firmwares loaded from
the MPU running this OS will block on the first `z_stm32_hsem_lock()`
call.
As it is required to run anything on the MCU core, we shouldn't assume
the HSEM clock is already active when booting and enable it in the SoC
init, the same way it is done for the STM32H7.
Signed-off-by: Arnaud Ferraris <arnaud.ferraris@collabora.com>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Replace npcx register base address type, uint32_t, with uintptr_t.
It is easier to know what type of base address and for linear
addresses treated as integral values.
This CL also modified IS_BIT_SET() macro function to fit MISRA code
guidelines.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Add gpio support for Nuvoton NPCX series. This CL includes:
1. Add GPIO device tree declarations.
2. Introduce wui_maps property in yaml file to present relationship
between Wake-Up
Input (WUI) and 8 IOs belong to the device.
3. Zephyr GPIO api implementation.
4. GPIO callback functions implementation with MIWU api functions.
5. Overlay file for gpio basic tests
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
The device Multi-Input Wake-Up Unit (MIWU) supports the embedded
controller (EC) to exit 'Sleep' or 'Deep Sleep' power state which allows
chip has better power consumption. Also, it provides signal conditioning
such as 'Level' and 'Edge' trigger type and grouping of external
interrupt sources of NVIC. The NPCX series has three identical MIWU
modules: MIWU0, MIWU1, MIWU2. Together, they support a total of over 140
internal and/or external wake-up sources.
In this CL, we use device tree files to present the relationship bewteen
MIWU and the other devices in different npcx series. For npcx7 series,
it include:
1. npcx7-miwus-int-map.dtsi: it presents relationship between MIWU group
and NVIC interrupt in npcx7. Please notice it isn't 1-to-1 mapping.
2. npcx7-miwus-wui-map.dtsi: it presents relationship between input of
MIWU and its source device such as gpio, timer, eSPI VWs and so on.
This CL also includes:
1. Add MIWU device tree declarations.
2. MIWU api function declarations and implementation to configure signal
conditions and callback function mechanism. They can be be classified
into two types. One is for GPIO which connects original gpio callback
implemetation and the other is for generic devices such as timer,
eSPI, and so on.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
To indicate that the CLOCK and POWER peripherals are present in those
SoCs, thus the corresponding nrfx drivers can be used.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Commit e80e655b01 introduced linker script
enforcement of Cortex-M vector table alignment. Update the i.MX RT boot
header to account for the possibility that the vector table may not be
placed at the address CONFIG_FLASH_BASE_ADDRESS +
CONFIG_ROM_START_OFFSET anymore.
For example, the RT1060 vector table has 176 entries and therefore must
be aligned to 0x400 bytes. If CONFIG_FLASH_BASE_ADDRESS=0x60000000 and
CONFIG_ROM_START_OFFSET=0x2200, the linker script will place the vector
table at 0x60002400 instead of 0x60002200.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Use new KConfig switches to configure debug support.
Correct ADC configuration where all ADC pins are in ADC mode.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Currently JTAG debug is enabled by default.
In some designs is desirable to disable JTAG functionality.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Add support for the Cortex-M1 ARM DesignStart FPGA SoC. This is not an
SoC in the traditional sense but more of a base to build an SoC upon.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Skeleton board support for the npcx7m6fb evaluation board from Nuvoton
Technology. This CL also includes:
1. Add ecst python scripts to append the header used by NPCX ROM.
2. Add openocd configuration scripts for "west flash".
3. Add monitor FW binary file for programing/verifying embedded flash
in NPCX series.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Add pin controller support for Nuvoton NPCX series
Add pin-mux controller support for Nuvoton NPCX series.
This CL includes:
1. Add pin controller device tree declarations and introduce alt-cells
to select pads' functionality.
2. Add npcx7-alts-map.dtsi since the mapping between IO and controller
is irregular and vary in each chip series.
3. Add nuvoton,npcx-pinctrl-def.yaml and its declarations to change all
pads' functionality to GPIO by default.
4. Pinmux controller driver implementation.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Add clock controller support for Nuvoton NPCX series. This CL includes:
1. Add clock controller device tree declarations.
2. Introduce clock-cells in yaml file clock tree to get module's source
clock and turn off/on the its clock
3. Clock controller driver implementation.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Initial support for Nuvoton NPCX7M6FB SoC of NPCX series which is a chip
family of embedded controllers (EC) and targeted for a wide range of
portable applications. We implemented the SoC skeleton in
soc/arm/nuvoton_npcx since there're many chip families in Nuvoton and
aim to different markets such as PC, General MCU, and Audio. The
architectures and hardware modules are different between them. Hence, we
suggest using the company name plus with chip series for better
understanding.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This file is setting Kconfig options even when it is not the chosen
SoC. I noticed this because without this patch, CONFIG_SOC_GECKO_EMU=y
when building for an unrelated board with SYS_POWER_MANAGEMENT=y.
Hide any subtrees in this file when the EXX32 family isn't selected.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
IEEE 802.15.4 is available for each board with Nordic SOC implementing
this protocol. Because of that protocol configuration shall be tied to
SOC instead of board.
Signed-off-by: Hubert Miś <hubert.mis@nordicsemi.no>
On CC13x2/CC26x2, power.c should be built when either system or device
power management is enabled. Currently it is only doing so for the
former.
Fixes#27392
Signed-off-by: Vincent Wan <vwan@ti.com>
Some parameters (e.g., tuning capacitors) can be configured in the
CMU_HFXOInit_TypeDef and CMU_LFXOInit_TypeDef structures before calling
CMU_HFXOInit() and CMU_LFXOInit() during clock initialisation.
Signed-off-by: Steven Lemaire <steven.lemaire@zii.aero>
Manage Dual core boot automatically whatever Option Bytes
configuration.
No more need of KConfig STM32H7_DUAL_CORE_BOOT to match
Option Bytes.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
This patch adds the iap.h header file which provides an entry function
for the IAP (In-Application Programming) interface. Note that the IAP
commands are located in the boot ROM code. Mostly they provide access
to the on-chip flash and EEPROM devices.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
This commit adds basic support for the clock controller used in
lpc11u6x MCUs.
Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
This patch adds a pinmux driver allowing to configure the IOCON (I/O
control) registers found on the LPC11U6x MCUs.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
We cannot call into the power library API as it is currently
available in binary format which cannot be included
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add HSE,HSI,CSI,PLL as system clock options.
Also add correct configuration of the PLL.
New sysclk options:
- HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y
- HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y
- CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y
Existing sysclk options:
- PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
PLL clock options:
- More PLL source clocks:
Existing:
1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
New:
2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y
- PLL vco input range is auto-calculated based on PLL DIVM1
-> Example for sysclock 96MHz generated with PLL from HSI
CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4
CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2
Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h
instead to setup the correct latency.
Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
This adds a new config option for SAM0 targets that use the BOSSA
bootloader. If the CDC ACM driver is also enabled, then the
programmer can automatically reset the board into the bootloader for
programming.
Signed-off-by: Michael Hope <mlhx@google.com>
x19 is callee saved register. z_arch_el3_plat_init being a callee,
it should save it before using it. However, at this point, stack
has not been setup. So, let's just use x20 instead which is not
being used caller yet. This bug was causing VBAR_EL1 corruption,
but since [10:0] bits are reserved, bug was hidden.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
The `TEXT_SECTION_OFFSET` symbol is used to specify the offset between
the beginning of the ROM area and the address of the first ROM section.
This commit renames `TEXT_SECTION_OFFSET` to `ROM_START_OFFSET` because
the first ROM section is not always the `.text` section.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
In case of dualcore, STM32H7, STM32W and STM32MP1,
protect concurrent register write access with HSEM.
Done for following drivers:
clock_control, counter, flash, gpio, interrupt_controller
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
When building for nRF5340 PDK board, enable Kconfig option
for Erratum 19. Do not enable when building on nRF5340 DK.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add and mark PCIe highmem outbound memory as nGnRnE device memory
in Viper SoC MMU configuration.
Increase VA/PA bits to 36-bits to support the same.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
This patch introduces the support of low power modes
for the STM32WBxx from STMicroelectronics based on the lptim
Here, the power modes are sleep modes have lptimer as wakeup source.
The sleep modes are configured by the SYS_POWER_MANAGEMENT.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add initial support for nuvoton numicro m48x SoC series, basic
init and uart functionality are covered with gpio and clock
directly relies on HAL.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
This enables PWM and connects it to the main LED. Tested by running
samples/basic/blinky_pwm and /fade_led.
Signed-off-by: Michael Hope <mlhx@google.com>
The SAM0 Timer/Counter for Control Applications can act as a counter
or generator. Add a binding for the TCC in PWM mode and helper to
check the compat mode.
Signed-off-by: Michael Hope <mlhx@google.com>
Add reset interrupt handlers for all three types of reset
interrupts that iProc PCIe EP can receive - namely PERST,
INB PERST and FLR.
Signed-off-by: Shivaraj Shetty <shivaraj.shetty@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Change the SAM0 to match other boards by selecting the SAM0 specific
driver when a driver class is selected.
For example, automatically enable CONFIG_SPI_SAM0 when CONFIG_SPI is
enabled.
Signed-off-by: Michael Hope <mlhx@google.com>
Only boards with at least 64K Flash will activate MPU because:
MPU + UERSPACE + All switches implicity activated
(CONFIG_MPU_STACK_GUARD, CONFIG_ARM_STACK_PROTECTION ...)
will consume about 40K Flash
(value computed on nucleo_f767_zi on tests/arch/arm/arm_ramfunc/).
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
The PWM drivers has been refactored using the HAL LL API. Not only that,
but the set pin_set function is now faster, as channel output compare is
just initialized if needed.
NOTE: Has been tested using H743zi board for now.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Those MCUs have 2KB RAM and 16KB FLASH memory, but they are still
powerful enough to run small configuration of Zephyr RTOS.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Added / Tested support for RNG on the STM32F767ZI nucleo board.
Updated the SoC defconfig to auto-enable the driver when
ENTROPY_GENERATOR is enabled, and updated the board README.
Signed-off-by: Bilal Wasim <bilalwasim676@gmail.com>
This patch introduces the support of low power modes
for the STM32L4xx from STMicroelectronics based on the lptim
Here, the power modes are sleep modes with lptimer as wakeup.
Depending on the SYS_POWER_MANAGEMENT configuration.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
tested on mimxrt1060_evt
MEMORY_NOCACHE is needed
test on frdmk64f
special test slot need configure with
CONFIG_DMA_TEST_SLOT_START
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
This option controls whether additional BLE support is
enabled for the cc13xx_cc26xx platform in hal/ti and
subsys/bluetooth.
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
Introduce switch to allow board configuration for VCI pins to
remain HW-controled depending on the design.
Currently pins are always configured as GPIOs which is not always
desirable.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
The NXP's Kinetics K66F is able to run with max frequency of 180MHz.
To achieve this goal the SMC's PMPROT and PMCTRL registers need to be
adjusted.
On the contrary the K64F doesn't support HSRUN run mode.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This option enables support for High Speed RUN operation mode for
K66F. The K64F SoC doesn't support this mode.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Add the necessary clock configuration to support STM32L-based
SoCs. This change likely adds support for other STM32 SoCs as well
since the HSI48 clock is configured for all SoCs that support it
(except the STM32L4x) instead of just the STM32G4X.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
This commit fixes Cortex-M header inclusions from the deprecated paths.
The Cortex-M headers were relocated from `include/arch/arm/cortex_m` to
`include/arch/arm/aarch32/cortex_m` by the refactoring done in the
commit d048faacf2.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This is defining the SYS_CLOCK_TICKS_PER_SEC default value
depending on the LPTIM CLOCK frequency in case of LPTIMER,
to get a TICK value as a divider of the LPTIM clock source.
It gives a better result in formulas when converting
ticks to count unit.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Several reviewers agreed that DT_HAS_NODE_STATUS_OKAY(...) was an
undesirable API for the following reasons:
- it's inconsistent with the rest of the DT_NODE_HAS_FOO names
- DT_NODE_HAS_FOO_BAR_BAZ(node) was agreed upon as a shorthand
for macros which are equivalent to
DT_NODE_HAS_FOO(node) && DT_NODE_HAS_BAR(node) &&
- DT_NODE_HAS_BAZ(node), and DT_HAS_NODE_STATUS_OKAY is an odd duck
- DT_NODE_HAS_STATUS(..., okay) was viewed as more readable anyway
- it is seen as a somewhat aesthetically challenged name
Replace all users with DT_NODE_HAS_STATUS(..., okay), which is
semantically equivalent.
This is mostly done with sed, but a few remaining cases were done by
hand, along with whitespace, docs, and comment changes. These special
cases include the Nordic SOC static assert files.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The Atmel SAM D21 SoC, according to the original Atmel datasheet
(Atmel-42181N), has 28 interrupt lines (0-27).
There have been mysterious changes in the number of interrupt lines and
on-chip peripherals in the recent Microchip datasheet releases, but
there is no explicit information available for this (e.g. PCN), so we
take the safest approach by assuming the lowest interrupt line number.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
PSA level 1 requires secure boot. TF-M BL2 is the official
secure boot loader. It needs a BL2_HEADER_SIZE offset.
Align nonsecure address with TF-M's NS slot while TF-M BL2 enabled.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
Add infineon XMC4 series UART support. Driver supports
only poll mode using XMCLib.
Out of 4 available UART's on SoC, only UART1 is confgired
by default in UART mode until GPIO & pinctrl support.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Add infineon xmc series with XMC4500 support. XMC series comes with,
- CPU operates upto 120MHz
- 3 RAM (PSRAM1 - code, DSRAM1 - data and DSRAM2 - communiation)
- upto 1MB flash
init: clock control & gpio is not done, so SoC initialization directly
relies on HAL. Core operating clock is stored in no_init section, which
is kept under DSRAM1. Only DSRAM1 is used until clock support. Using
PSRAM1 and DSRAM1 needs adaptation in linker script - planned for next
revision.
Note: SystemInit cannot be consumed directly due to vector table +
HAL linker dependency.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Add initilizations for:
- Cortex-A72 L2 Controller configurations. This initialization to
be done when cluster is in quiscent state.
- 'ICC_SRE_EL3' init to allow GIC V3 ICC_SRE_ELx system interface.
This initialization can be done at 'EL3' only.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Swap this out and make the status a parameter.
Leave a couple of cases of DT_NODE_HAS_COMPAT().
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
These are redundantly checking a node's status twice.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Usually, we want to operate only on "available" device
nodes ("available" means "status is okay and a matching binding is
found"), but that's not true in all cases.
Sometimes we want to operate on special nodes without matching
bindings, such as those describing memory.
To handle the distinction, change various additional devicetree APIs
making it clear that they operate only on available device nodes,
adjusting gen_defines and devicetree.h implementation details
accordingly:
- emit macros for all existing nodes in gen_defines.py, regardless
of status or matching binding
- rename DT_NUM_INST to DT_NUM_INST_STATUS_OKAY
- rename DT_NODE_HAS_COMPAT to DT_NODE_HAS_COMPAT_STATUS_OKAY
- rename DT_INST_FOREACH to DT_INST_FOREACH_STATUS_OKAY
- rename DT_ANY_INST_ON_BUS to DT_ANY_INST_ON_BUS_STATUS_OKAY
- rewrite DT_HAS_NODE_STATUS_OKAY in terms of a new DT_NODE_HAS_STATUS
- resurrect DT_HAS_NODE in the form of DT_NODE_EXISTS
- remove DT_COMPAT_ON_BUS as a public API
- use the new default_prop_types edtlib parameter
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This commit adds basic support for nRF52820 SoC.
Changes affect introducing:
- architecuture files (dtsi)
- configuration of nrfx drivers
- adaptation of inclusions based on chosen SoC
Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
Changes:
- Added all required board files in /boards/arm/96b_aerocore2
- Modified pinmux for stm32f4
Most of the changes in this PR is based on reverse-engineering of the
PCB layout and following commits in the PX4 firmware repository for
the same board. The manufacturer does not provide and or generate
schematics and pinout tables for this board.
This PR includes almost all of the interfaces connected to the STM32
MCU, the only thing not included is the J9 and J8 headers that connect
to a 96Boards baseboard.
These headers are not vital to the functionality of the Aerocore2.
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
Add STM32F427. This is mainly aimed towards the stm32f427vi.
Changes:
- Add stm32f427 support based on previous work
done for the stm32f429.
- Rework currunt stm32f429 implimentation to now
be based on stm32f427.
- Introduce dedicated dtsi for the VI variant of both
stm32f427 and stm32f429. This is done to prevent stm32f4.dtsi
from being included twice.
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
The SAM V71 SoC configuration currently selects the `ARM_MPU` symbol
and this effectively forces MPU usage on the SoC.
This commit removes `ARM_MPU` selection from the SoC Kconfig since it
is intended to be selected by a board, and the `CPU_HAS_ARM_MPU` symbol
already indicates that the SoC supports ARM MPU.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The SAM E70 SoC configuration currently selects the `ARM_MPU` symbol
and this effectively forces MPU usage on the SoC.
This commit removes `ARM_MPU` selection from the SoC Kconfig since it
is intended to be selected by a board, and the `CPU_HAS_ARM_MPU` symbol
already indicates that the SoC supports ARM MPU.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Add initial support for Broadcom Viper SoC.
It has ARM Cortex-M7 and Cortex-A72 cores.
Signed-off-by: Arjun Jyothi <arjun.jyothi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Use MSI as PLL source. This enables to run system clock at 110MHz.
To achieve this, voltage regulator should be set to scale 0.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This patch defines the dma feature for the stm32wbXX
and the dmamux feature for the stm32wb55x
soc series from STMicroelectronics
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add support for ADC on H7 series. Note that ADC1 and ADC2 share the same
register set, so it is added as "adc1_2".
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
All pin configuration for ATMEL SAM SoC come from devicetree so we can
now remove the soc_pinmap.h header files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert i2s_sam_ssc driver to utilize devicetree. We replace Kconfig
options for specifying the DMA configuration (channel, DMA device name)
with getting that from devicetree. We also get pincfg from devicetree,
however we still have Kconfig sybmols to specify if the RF or RK pin is
enabled.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Due to a typo compiling the WWDG on the g4 family does not
work. This adds the correct include filename.
Signed-off-by: Richard Osterloh <richard.osterloh@gmail.com>
High Speed Flexcomm device that handles high speed SPI transfer are
mapped to the same High Frequency clock that the ARM core uses.
This allows for higher frequency SPI traffic.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Port the usage of the timeouts to the new timeout API, in order to be
able to deselect the legacy timeout option.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Convert to using DT_INST_LABEL() in the dma driver and convert dma users
to use the DMA property macros to get the dma controller name. We make
the assumption in the drivers that there is a single DMA controller
instance.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Some Kinetis SoCs have an instance of the the TPM module
that can be used for PWM control. As such, add the necessary
configurations to enable it on the SoCs that support it, as well as
enable the clock for the module to function.
In this case, the enablement is done only for the KW41Z SoCs,
but there are other SoCs that support it, f.i. KW38Z
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Enable I2S_STM32 in the soc common part, so it will no
longer be required in board default configuration.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Rename DT_HAS_NODE to DT_HAS_NODE_STATUS_OKAY so the semantics are
clear. As going forward DT_HAS_NODE will report if a NODE exists
regardless of its status.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As we phase out per instance Kconfig symbols convert to utilize
DT_NODELABEL for SPI and I2C instances instead.
Also updated comments to change from FLEXCOMM8 to HSLSPI.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Remove DT_ADC_{0..2}_NAME from dts_fixup.h, if this casues the
dts_fixup.h file to be empty we remove the file as well.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Reworked sam_gmac driver to get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from soc_pinmap.h that are no longer needed due to
getting all that information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds the `devicetree.h` header inclusion in the Atmel SAM-
family SoC header files, as required by the ARM SoC conventions.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds the `devicetree.h` header inclusion in the Atmel SAM0-
family SoC header files, as required by the ARM SoC conventions.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Enable the driver for the Kinetis Digital-to-Analog (DAC) modules
present in the NXP Kinetis K6x SoC series.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Enable the driver for the Kinetis Digital-to-Analog (DAC32) module
present in the NXP Kinetis KE1xF SoC series.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Remove dts_fixup.h files that are needed anymore, remove defines that
are used, and replace defines with new DT macros.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Remove dts_fixup.h files that are not used (empty) or the defines aren't
used anymore and thus can be removed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Remove dts_fixup.h files that are needed anymore, remove defines that
are used, and replace defines with new DT macros.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Complete STM32 conversion to new DT macros by removing
remaining occurences of DT_ST_STM32_ADC_FOO_LABEL.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Complete STM32 conversion to new DT macros by removing
remaining occurences of DT_ST_STM32_ADC_FOO_LABEL.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Convert ocram and sdram regions to use new macro DT_REG_ADDR() and
DT_REG_SIZE() with DT_NODELABEL to determine the various memories size
and base address.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use new DT_INST macros throughout. Removed per
instance Kconfig symbols and replaced with DT_NODELABEL references
where needed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert the code for setting the clock IP source of the various IPs
present in the NXP KE1xF SoC series to the new DT API.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Convert driver to use the new device tree macro's instead of
dts_fixup.h based macros. This moves us closer to removing both
dts_fixup.h and per instance Kconfig symbols.
The pinmux_mchp_xec is also being updated since it's using DT
from GPIO.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Convert driver to use the new device tree macro's instead of
dts_fixup.h based macros. This moves us closer to removing both
dts_fixup.h and per instance Kconfig symbols.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Convert driver to use instance macro's instead of dts_fixup.h based
macros. This moves us closer to removing both dts_fixup.h and per
instance Kconfig symbols.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Replace DT_ARM_CORTEX_*_0_CLOCK_FREQUENCY with a PATH based reference
to cpu@0 (DT_PATH(cpus, cpu_0)) and than getting the clock_frequency
property:
DT_ARM_CORTEX_*_CLOCK_FREQUENCY ->
DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit renames the Kconfig `FLOAT` symbol to `FPU`, since this
symbol only indicates that the hardware Floating Point Unit (FPU) is
used and does not imply and/or indicate the general availability of
toolchain-level floating point support (i.e. this symbol is not
selected when building for an FPU-less platform that supports floating
point operations through the toolchain-provided software floating point
library).
Moreover, given that the symbol that indicates the availability of FPU
is named `CPU_HAS_FPU`, it only makes sense to use "FPU" in the name of
the symbol that enables the FPU.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Use DT_INST_FOREACH macro to combine code used for multiple instances.
Remove unnecessary Kconfig options and dts fixups for GPIO instances.
A side-effect to using DT_INST_FOREACH is that GPIO ports A0 and A3
are now enabled, whereas they were originally disabled by default as
an optimization.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Reworked spi_sam driver to utilize new DT_INST macros as part of
this rework we also now get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from dts_fixup.h and soc_pinmap.h and associated
Kconfig symbols that are no longer needed due to getting all that
information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Added ATMEL_SAM_DT_NUM_PINS macro which will return the number of pins
to initialize for "pinctrl-0" devicetree property.
Added ATMEL_SAM_DT_PINS macro which will create an array initializer
with all the pins associated with "pinctrl-0" devicetree property.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add wdt0 node labels for all watchdogs. Keep the existing wdt node
labels in place for backwards compatibility.
Add a wdt1 node to the nRF5340 application core .dtsi, but leave it
disabled. Leave the wdt node's label set to "WDT" on this core for
backwards compatibility also, in case any users are getting it with a
string literal instead of asking the devicetree. This can be changed
later after this round of watchdog changes has been shaken out and
tested more.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Convert the driver to use the new dt macros. As part of this change we
remove a bunch of defines that happened in dts_fixup.h that didn't
belong there. Some of these should be converted to devicetree
properties at some point.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The SAM E54 series SoCs include a single-precision FPU; therefore, the
`CPU_HAS_FPU` symbol should be selected.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The SAM E53 series SoCs include a single-precision FPU; therefore, the
`CPU_HAS_FPU` symbol should be selected.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The SAM E51 series SoCs include a single-precision FPU; therefore, the
`CPU_HAS_FPU` symbol should be selected.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The SAM D51 series SoCs include a single-precision FPU; therefore, the
`CPU_HAS_FPU` symbol should be selected.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The SAM D51, E51 and E53 SoC series Kconfig files were missing the
`ARM` architecture symbol selection.
This symbol must be selected at the SoC level; otherwise, build will
fail because the symbol is not selected by anything and other ARM-
specific configurations depend on it.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Replace DT_CPU_CLOCK_FREQUENCY with a PATH based reference to cpu@0
(DT_PATH(cpus, cpu_0)) and than getting the clock_frequency property:
DT_CPU_CLOCK_FREQUENCY -> DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
This lets us remove DT_CPU_CLOCK_FREQUENCY from dts_fixup.h.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Change DT_GPIO_GECKO_SWO_LOCATION to use new DT_INST and DT_PROP macros
and remove defining it in dts_fixup.h.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move the FPGA GPIO init to use the devicetree.h macros instead of
dts_fixup.h. This allows us to remove dts_fixup.h on mps2 based
platforms.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert old DT defines of the form DT_ARM_SCC_BASE_ADDRESS to
DT_REG_ADDR(DT_INST(0, arm_scc)). This allows us to remove dts_fixup.h
on musca boards.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use instance macro's instead of dts_fixup.h based
macros. This moves us closer to removing both dts_fixup.h and per
instance Kconfig symbols.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Reworked adc_sam_afec driver to utilize new DT_INST macros as part of
this rework we also now get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from dts_fixup.h and soc_pinmap.h and associated
Kconfig symbols that are no longer needed due to getting all that
information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use new DT_INST macros throughout. We also remove
defines in dts_fixup.h as they are no longer needed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use new DT_INST macros throughout. We update one
sample app to use a nodelabel reference. We also remove defines in
dts_fixup.h as they are no longer needed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a common header for SAM0 drivers to use to extract data from
devicetree. The initial set of macros are for get the MCLK A*MASK
register address for clock enablement and a set of macros for use with
DMA to get the channel and trigger source or 0xff if there is no dmas
property.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In order for IO pins to work correctly after waking up from shutdown
mode, we need to unlatch them given they were automatically latched
when Power_shutdown() was invoked.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
The DT_I2S_* defines can be removed as the driver is now utilizing the
new dt macros that don't require these defines.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Reworked i2c_sam_twi driver to utilize new DT_INST macros as part of
this rework we also now get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from dts_fixup.h and soc_pinmap.h and associated
Kconfig symbols that are no longer needed due to getting all that
information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Reworked i2c_sam_twi driver to utilize new DT_INST macros as part of
this rework we also now get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from dts_fixup.h and soc_pinmap.h and associated
Kconfig symbols that are no longer needed due to getting all that
information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use new DT_INST macros throughout. Removed per
instance Kconfig symbols and replaced with DT_NODELABEL references
where needed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use new DT_INST macros throughout. We can remove
various defines from dts_fixup.h now as well.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert from using dts_fixup.h based macros to DT_INST macro. This lets
us remove the dependancy on dts_fixup.h for this driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use DT_INST macros and remove related board per
instance Kconfig symbol usage. We also remove dts_fixup.h defines that
are no longer needed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert from using dts_fixup.h based macros to DT_INST macro. This
lets us remove the dependancy on dts_fixup.h for this driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Reworked usart_sam driver to utilize new DT_INST macros as part of
this rework we also now get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from dts_fixup.h and soc_pinmap.h and associated
Kconfig symbols that are no longer needed due to getting all that
information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Reworked uart_sam driver to utilize new DT_INST macros as part of this
rework we also now get pin ctrl/mux configuration information from the
device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from dts_fixup.h and soc_pinmap.h and associated
Kconfig symbols that are no longer needed due to getting all that
information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a set of macros that will create a struct soc_gpio_pin
initialization based on data extracted from device tree. This should
allow replacing the static data in soc_pinmap.h with data coming from
devicetree instead.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert from using dts_fixup.h based macros to DT_INST macro. This lets
us remove the dependancy on dts_fixup.h for this driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We don't need to define DT_NUM_IRQ_PRIO_BITS or DT_NUM_MPU_REGIONS in
dts_fixup.h files anymore, so we can remove them.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
To remove the need to have DT_NUM_IRQ_PRIO_BITS defined in every
dts_fixup.h we can just handle the few variant cases in irq.h. This
allows us to remove DT_NUM_MPU_REGIONS from all the dts_fixup.h files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds the MCLK clock configuration symbol fix-up for the
GMAC peripheral.
The APB-agnostic clock configuration fix-up symbols map to the
SoC-specific APB, in order to accommodate different SoC variants with
the GMAC on different APBs.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Make use of DT_NODELABEL macros to get device instances
information to configure drivers I2C instances.
This allows to remove I2C related lines in fixup.h files
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Use compatible information to configure i2c stm32.
With this, driver version selection is done thanks to compatible
and it is not needed anymore to do this via Kconfig symbol
selection under soc/
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Replace CONFIG_ENTROPY_NAME with DT_CHOSEN_ZEPHYR_ENTROPY_LABEL. We now
set zephyr,entropy in the chosen node of the device tree to the entropy
device.
This allows us to remove CONFIG_ENTROPY_NAME from dts_fixup.h. Also
remove any other stale ENTROPY related defines in dts_fixup.h files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
z_power_soc_deep_sleep() is called with interrupt locked already
so restoring BASEPRI is pointless here, as it would only allow
exceptions afterwards. The situation is complicated by the fact
that kernel/idle.c:idle() only locks interrupt without unlocking
which means the BASEBRI at entry of z_power_soc_deep_sleep() is
already set to allow exceptions only but not lower priority
interrupts like timer. So when, e.g. timer, interrupt fires,
the SoC would come out of deep sleep but the waking interrupts
are never delivered since they are masked, and idle() will try
to sleep again. And now it gets into a loop of going into deep
sleep briefly and waking up immediately and it goes on and on.
The solution is not to restore BASEPRI and simply leave it at
zero. This is a workaround as a proper fix would involve
invasion changes to the PM subsystem.
Also, _sys_pm_power_state_exit_post_ops() is not being called
when deep sleep is involved, so PRIMASK needs to be reset
after coming out of deep sleep.
Fixes#23274
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Use the new devicetree API in a file which cross-checks dt reg base
addresses with values from the vendor HAL.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
When enabled, instead of erasing entire flash page at once, page will
be erased in defined time slices. Erasing single page stalls CPU
for significant time share (~80ms) and partial erase divides the
operation in to the shorter time periods, resuming CPU operation in
meantime and enabling better scheduling of time sensitive operations.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
To ease driver configuration, enable ENTROPY_STM32_RNG
only if device node matching driver compatible is enabled.
No more need to enable config symbol under soc/
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Convert stm32 entropy driver to configuration based on device tree.
Select HAS_DTS_ENTROPY symbols and configure CONFIG_ENTROPY_NAME
in fixup files.
Since rng node is not enabled (or available) on all boards, it could
happen that symbol ENTROPY_STM32_RNG is not enabled and hence
ENTROPY_HAS_DRIVER not selected which ends up with a symbol
ENTROPY_NAME defined throufg Kconfig selection. Thus, in fixup file,
CONFIG_ENTROPY_NAME is defined only if not already defined.
Additionally, update boards that used to configure entropy by default.
On these boards, enable rng device in device tree and remove Kconfig
related configuration (which should not be part of default
configuration).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Instead of using Kconfig options for setting the device name and IRQ
priority for the entropy_nrf5 driver, get these settings from the rng
node defined in DTS for a given SoC.
Provide also fixups for CONFIG_ENTROPY_NAME, until applications using
entropy drivers are converted to use DTS as well.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Convert driver to use DT_INST macros and remove related board per
instance Kconfig symbol usage.
Also update counter_basic_api test to use DT_INST and remove the
udoo_neo_full_m4.conf as its not longer needed since the per instance
Kconfig sybmols don't exist anymore.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use DT_INST macros and remove related board per
instance Kconfig symbol usage.
Additionally remove udoo_neo_full_m4.conf from gpio_basic_api test since
the Kconfig symbols don't need to be set anymore.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As prep for drivers being converted to utilize DT_INST and removal of
per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL
instead.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Make I2C and SPI drivers for nRF SoCs no longer dependent on Kconfig
options that enable instances (i.e. I2C_x and SPI_x). Now these drivers
enable hardware instances when corresponding nodes in devicetree are
enabled (have status "okay").
For I2C, SPI, and UART drivers, instead of using Kconfig dependencies
to prevent enabling of hardware instances that cannot be used together
(e.g. SPIM1 and TWIM1), a file that signals invalid configurations with
build assertions is added to compilation.
Also dependencies on HAS_HW_NRF_* options are removed from Kconfigs
of I2C, SPI, and UART drivers, as for hidden options that activate
proper type of driver such dependencies are not actually helpful.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Convert driver to utilize the new DT_INST macros completely and remove
associated Kconfig symbols that now come from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move to using DT_NODELABEL to get references to determine if specific
GPIO ports are enabled in the beetle SoC code.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Recent stm32 gpio driver changed removed the per port Kconfig symbols.
We had a type in flight issue in which the stm32l422xx got added and set
GPIO_STM32_PORTH. Just remove the Kconfig symbol as its not needed
anymore to fix build issues.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Use device node declaration instead.
Clean up GPIO_STM32_PORT* Kconfig symbols.
On some boards some gpio ports where disabled using Kconfig symbols.
Disable them now via device tree nodes in boards dts files.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add support for the STM32L422Xb SoC. Base stm32l422.dtsi on
stm32l412.dtsi to be able to add the crypto device later.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Add a k_timeout_t type, and use it everywhere that kernel API
functions were accepting a millisecond timeout argument. Instead of
forcing milliseconds everywhere (which are often not integrally
representable as system ticks), do the conversion to ticks at the
point where the timeout is created. This avoids an extra unit
conversion in some application code, and allows us to express the
timeout in units other than milliseconds to achieve greater precision.
The existing K_MSEC() et. al. macros now return initializers for a
k_timeout_t.
The K_NO_WAIT and K_FOREVER constants have now become k_timeout_t
values, which means they cannot be operated on as integers.
Applications which have their own APIs that need to inspect these
vs. user-provided timeouts can now use a K_TIMEOUT_EQ() predicate to
test for equality.
Timer drivers, which receive an integer tick count in ther
z_clock_set_timeout() functions, now use the integer-valued
K_TICKS_FOREVER constant instead of K_FOREVER.
For the initial release, to preserve source compatibility, a
CONFIG_LEGACY_TIMEOUT_API kconfig is provided. When true, the
k_timeout_t will remain a compatible 32 bit value that will work with
any legacy Zephyr application.
Some subsystems present timeout (or timeout-like) values to their own
users as APIs that would re-use the kernel's own constants and
conventions. These will require some minor design work to adapt to
the new scheme (in most cases just using k_timeout_t directly in their
own API), and they have not been changed in this patch, instead
selecting CONFIG_LEGACY_TIMEOUT_API via kconfig. These subsystems
include: CAN Bus, the Microbit display driver, I2S, LoRa modem
drivers, the UART Async API, Video hardware drivers, the console
subsystem, and the network buffer abstraction.
k_sleep() now takes a k_timeout_t argument, with a k_msleep() variant
provided that works identically to the original API.
Most of the changes here are just type/configuration management and
documentation, but there are logic changes in mempool, where a loop
that used a timeout numerically has been reworked using a new
z_timeout_end_calc() predicate. Also in queue.c, a (when POLL was
enabled) a similar loop was needlessly used to try to retry the
k_poll() call after a spurious failure. But k_poll() does not fail
spuriously, so the loop was removed.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Kernel timeouts have always been a 32 bit integer despite the
existence of generation macros, and existing code has been
inconsistent about using them. Upcoming commits are going to make the
timeout arguments opaque, so fix things up to be rigorously correct.
Changes include:
+ Adding a K_TIMEOUT_EQ() macro for code that needs to compare timeout
values for equality (e.g. with K_FOREVER or K_NO_WAIT).
+ Adding a k_msleep() synonym for k_sleep() which can continue to take
integral arguments as k_sleep() moves away to timeout arguments.
+ Pervasively using the K_MSEC(), K_SECONDS(), et. al. macros to
generate timeout arguments.
+ Removing the usage of K_NO_WAIT as the final argument to
K_THREAD_DEFINE(). This is just a count of milliseconds and we need
to use a zero.
This patch include no logic changes and should not affect generated
code at all.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Replace all occurences of BUILD_ASSERT_MSG() with BUILD_ASSERT()
as a result of merging BUILD_ASSERT() and BUILD_ASSERT_MSG().
Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
Fix typo where DT_REG_ADDR was used istead of DT_REG_SIZE in
linker script for i.MX RT socs and their ITCM and DTCM memories.
Signed-off-by: Arvid Rosén <arvid@softube.com>
Indicate that the NXP Kinetis KE1xF SoC contains a Low Power Timer
(LPTMR) and default to enabling the corresponding driver if
CONFIG_COUNTER is enabled.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Added device tree nodes and associated headers for
defined uarts on the stm32g0 and stm32g07x 8x parts.
Tested with uart on stm32g071rb disco board with usart3 going to stlink.
Using shell.
Signed-off-by: Kieran Levin <ktl@frame.work>
This commit renames the `cortex_r` directory under the AArch32 to
`cortex_a_r`, in preparation for the AArch32 Cortex-A support.
The rationale for this renaming is that the Cortex-A and Cortex-R share
the same base design and the difference between them, other than the
MPU vs. MMU, is minimal.
Since most of the architecture port code and configurations will be
shared between the Cortex-A and Cortex-R architectures, it is
advantageous to have them together in the same directory.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
When power management is enabled, SYS_PM_STATE_LOCK is necessary
in order to prevent the power policy from automatically entering
certain sleep states.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
The shared irq support isn't needed in this driver. We just need to
deal with the fact that some SoCs have only a single interrupt line and
some have three interrupts. We can just ifdef that based on
DT_NUM_IRQS.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This was a simple missing macro, that prevented flash_shell to build
for stm32f4 based boards (which is weird, CI should have caught that
much earlier)
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Convert the driver to use DT_INST_ defines, update all dependent dts,
soc and board files.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Rename the clock defines from k64 to K6X. This allows
inclusion of K66 series MCU's support without much
re-defines. Clock divider defaults to K64 series.
Signed-off-by: Parthiban Nallathambi <pn@denx.de>
Add entropy driver based on GECKO TRNG module along with device
tree support for EFM32PG and EFR32MG SOCs.
Signed-off-by: Pooja Karanjekar <pooja.karanjekar@lemonbeat.com>
This reverts commit 8739517107.
Pull Request #23437 was merged by mistake with an invalid manifest.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Replace all occurences of BUILD_ASSERT_MSG() with BUILD_ASSERT()
as a result of merging BUILD_ASSERT() and BUILD_ASSERT_MSG().
Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
This commit updates the `xilinx_zynqmp` SoC initialisation code to use
the CMSIS-Core(R) features.
In addition, it also defines the Core IP revision value for the SoC as
specified in the Zynq UltraScale+ Device Technical Reference Manual.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Convert usb_stm32 driver to use of DT_INST macros.
Since driver is compatible with 3 different dt compatibles and
compatible string is included in DT_INST macros, I've kept the
DT_USB_ compatible agnostic macros based on DT_INST ones, which
allowed to remove fixup definitions.
Use of DT_USB symbols is now limited to usb_dc_stm32.
Additionally, compatible "st,stm32-otgfs" is removed from list
of compatibles for usbotg_hs ips.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Convert driver to use DT_INST_ defines.
In the process, we've removed all UART/USART/LPUART code in
device instanciation code which had no impact.
Since all uart/usart/lpuart nodes declare compatibility with
st,stm32uart, DT_INST_X_ST_STM32_UART_FOO could be used.
Removed DT_UART fixup macros.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Convert driver to use DT_INST_ defines.
Removed DT_FLASH_DEV fixup macros, except DT_FLASH_DEV_NAME
used in applications.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Convert driver to use DT_INST_ defines.
Removed DT_RTC_0 fixup macros but keep DT_RTC_NAME_0 as it is
still in use across RTC users.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Erratum 19: SPU region size is 32 kB instead of 16 kB.
The config should be used for alignment for data that must follow SPU
region boundaries, and to enable runtime checks when configuring SPU
regions.
Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
The set of interrupt stacks is now expressed as an array. We
also define the idle threads and their associated stacks this
way. This allows for iteration in cases where we have multiple
CPUs.
There is now a centralized declaration in kernel_internal.h.
On uniprocessor systems, z_interrupt_stacks has one element
and can be used in the same way as _interrupt_stack.
The IRQ stack for CPU 0 is now set in init.c instead of in
arch code.
The extern definition of the main thread stack is now removed,
this doesn't need to be in a header.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Enable counter driver support for H7 series. Tested with H743ZI MCU
using samples/drivers/counter/alarm.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Change to code to use the automatically generated DT_INST_*
defines and remove the now unneeded configs and fixups.
Signed-off-by: Timo Teräs <timo.teras@iki.fi>
This commit updates the `qemu_cortex_a53` platform to use the
refactored AArch64 interrupt system.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit updates the `xilinx_zynqmp` platform to use the refactored
AArch32 interrupt system.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Add support for sleep states. Sleep state 1 corresponds to idle mode,
and Sleep state 2 corresponds to standby mode, as per the Technical
Reference Manual.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
This commit adds an option to configure the frequency
in Hz for the HFRCO clock source. The default value
for this option is 0 which skips the configuration of the HFRCO.
This feature is supported for efm32gg, efm32jg, efm32pg, efm32fg
and efm32mg SOCs currently.
Signed-off-by: Pooja Karanjekar <pooja.karanjekar@lemonbeat.com>
The 48MHz PLL on MEC1501 is shut off during deep sleep (i.e. heavy
sleep in datasheet). When coming out of deep sleep, this PLL needs
about 3ms to lock. Most peripherals are using this PLL as clock
source and timing would be off before PLL is locked. Example of
this is seen on serial console where garbage characters are sent
as the UART block is not pushing characters out at the configured
baud rate. This likely affects all other peripherals such as I2C
and eSPI. Luckily, there is a register to indicate whether the PLL
is ready. So spin on it when coming out of deep sleep.
Fixes#23207
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Convert driver to use DT_INST_ defines. The preferred defines for
drivers are DT_INST_. The driver mostly used DT_INST_ defines but
a few IRQ priority defines needed conversion.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use DT_INST_ defines. The preferred defines for
drivers are DT_INST_.
As part of this change we utilize the device tree for GIRQ info and
rename timer3 to 2 since we are doing this by instance number.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The max-value should just be an int and not an array. Change the type
to 'int' in the binding and fixup the driver to match.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use DT_INST_ defines. Replace dts_fixup.h use
for DT_RTC_0_NAME with DT_INST_0_NXP_KINETIS_RTC_LABEL to be
consistent. Also, remove the aliases that had been used for this
driver in various nxp_k*.dtsi.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use DT_INST_ defines and remove Kconfig per instance
enablement in favor of DT_INST_ define existing. Also, remove the
aliases that had been used for this driver in nxp_rt.dtsi.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Update the hal_nordic module revision, to apply the following changes:
nrfx_config: Fix translation of symbols for _S or _NS only peripherals
For peripherals with only one type of access available (either secure
or non-secure), the common symbol translation scheme cannot be used
as it leads to mapping to non-existing symbols (e.g. NRF_FICR_NS).
Instead, use fixed translations for these symbols (e.g. NRF_FICR to
NRF_FICR_S, only for secure images).
nrfx_config: Add missing _S/_NS symbol translations for nRF5340/nRF9160
Add translations of names with _S and _NS suffixes for peripheral
access symbols that are available for a given chip but were not used
so far in any nrfx HAL or driver, to make the lists of translations
complete and consistent.
This commit corrects also the translation of NRF_I2S symbol for nRF5340
whose name for this SoC contains also the index 0 (so it needs to be
handled similarly like NRF_PDM0 is).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Configure the LDO supply when initializing H7 (M7) SoC. I have
observed MCU hanging on LL_PWR_IsActiveFlag_VOS() wait loop when
doing a cold boot if LDO supply is not explicitely enabled.
According to the datasheet LDO should be enabled by default,
however HAL examples also configure LDO, so there may be a
reason to perform such step.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The driver for STM32's independent watchdog already exists and is
compatible with the stm32g0 SoC. Enable the independent watchdog
for the stm32g0 series for use with this driver.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
It is observed that after each test, weird characters appear on
console. This problem goes away if deep sleep is disabled.
The theory is that the CPU runs to deep sleep (_sys_suspend())
faster than UART can shift all the bits out. If we spin wait
for UART FIFO to clear, this is no longer an issue. This is
circumstantial evidence to the theory. So for now, put in
a workaround to spin wait for UART FIFO to clear before
going into deep sleep.
Relates to #22885
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit adds Device-Tree instances of the Flash controller
to the SAM3X, SAM4E and SAM4S series. The Flash-Controller
is used to get the unique device identifier.
Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
Include stm32XXxx_ll_utils.h in soc.h for every stm32 SoC,
if CONFIG_HWINFO_STM32 is selected.
Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
Add qemu-cortex-a53 memory regions with proper attributes
to translation tables. Minimal regions to execute "hello_world"
are added as of now, More granular memory regions should be
added later as per the requirement.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Same deal as in commit eddd98f811 ("kconfig: Replace some single-symbol
'if's with 'depends on'"), for the remaining cases outside defconfig
files. See that commit for an explanation.
Will do the defconfigs separately in case there are any complaints
there.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Same deal as in commit eddd98f ("kconfig: Replace some single-symbol
'if's with 'depends on'"), for all symbols defined within defconfig
files. See that commit for an explanation.
Maybe 'if's were used originally to mirror the 'if's in the main Kconfig
files, and then it got copied around by people assuming 'if' must work
differently from 'depends on'. It doesn't match in every spot at least.
Better to keep it simple and just consistently use 'depends on' when
it's a single symbol/choice I think. Helps reinforce that 'if' isn't
magic too.
Verified by printing all Kconfig menu nodes (symbols, choices, menus,
etc.) before and after the change and diffing (should show no
difference).
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Move PWR init code out of clock control driver and
put SMPS related function under SMPS condition as it
is not supported by all soc variants of the series.
Fixes#22363
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The DT_FLASH_DEV_NAME define used by the sample was set to a define
symbol that was never generated. Change it to use
DT_INST_0_ATMEL_SAM0_NVMCTRL_LABEL on the sam0 family of SoCs that
had this issue.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
All board defconfig files currently set the architecture in addition to
the board and the SoC, by setting e.g. CONFIG_ARM=y. This spams up
defconfig files.
CONFIG_<arch> symbols currently being set in configuration files also
means that they are configurable (can be changed in menuconfig and in
configuration files), even though changing the architecture won't work,
since other things get set from -DBOARD=<board>. Many boards also allow
changing the architecture symbols independently from the SoC symbols,
which doesn't make sense.
Get rid of all assignments to CONFIG_<arch> symbols and clean up the
relationships between symbols and the configuration interface, like
this:
1. Remove the choice with the CONFIG_<arch> symbols in arch/Kconfig and
turn the CONFIG_<arch> symbols into invisible
(promptless/nonconfigurable) symbols instead.
Getting rid of the choice allows the symbols to be 'select'ed (choice
symbols don't support 'select').
2. Select the right CONFIG_<arch> symbol from the SOC_SERIES_* symbols.
This makes sense since you know the architecture if you know the SoC.
Put the select on the SOC_* symbol instead for boards that don't have
a SOC_SERIES_*.
3. Remove all assignments to CONFIG_<arch> symbols. The assignments
would generate errors now, since the symbols are promptless.
The change was done by grepping for assignments to CONFIG_<arch>
symbols, finding the SOC_SERIES_* (or SOC_*) symbol being set in the
same defconfig file, and putting a 'select' on it instead.
See
https://github.com/ulfalizer/zephyr/commits/hide-arch-syms-unsquashed
for a split-up version of this commit, which will make it easier to see
how stuff was done. This needs to go in as one commit though.
This change is safer than it might seem re. outstanding PRs, because any
assignment to CONFIG_<arch> symbols generates an error now, making
outdated stuff easy to catch.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Add the common config structure as a prefix of the driver-specific
config structure and use the devicetree GPIO pin counts to initialize
it. Not all aliases appear to be present, but using instances breaks
because the ports used by different boards do not always start with
the first.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The current sam spi driver uses soc dependent name which duplicate
configuration to enable other platforms. This refactor current
definitions to a generic way to reuse symbols by multi soc definitions.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add option for keeping the watchdog timer of the NXP Kinetis KE1xF SoC
series enabled at boot with a configurable, initial timeout.
This removes the risk of failure from when z_arm_watchdog_init()
disables the watchdog timer until the application code configures a
timeout and re-enables the watchdog timer.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit adds the following:
- device tree bindings for Gecko watchdog driver
- EFM32PG SOC support for the watchdog driver
- EFM32PG board support for the watchdog driver
- DTS aliases for testing with default watchdog driver test
Signed-off-by: Oane Kingma <o.kingma@interay.com>
Enable the shared IRQ for the UART line and enable the remaining tasks
that depends on a separated declaration of the TX/RX/Err/... IRQs.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit adds the remaining gpio ports I, J and K to the device
tree and dts_fixup headers of the EFM32JG12B and EFM32PG12B SoCs.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
The Silicon Labs EFM32 Jade Gecko MCU includes:
* Cortex-M3 core at 40MHz
* up to 1024KB of flash and 256KB of RAM
* multiple low power peripherals
This is basically the same as the EFM32 Pearl Gecko, but with an ARM
Cortex-M3 core instead of a Cortex-M4F.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
Disable the early watchdog initialization for the NXP Kinetis series
if the application is to be chain-loaded by mcuboot.
The early watchdog initialization must only take place once and needs
to happen within a SoC specific number of CPU clock cycles after
reset.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Move CONFIG_WDOG_INIT for the NXP Kinetis series to the top-level
Kinetis Kconfig file and enable it where needed.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Move the NXP Kinetis KW4xZ watchdog initialization code to
z_arm_watchdog_init() and make it optional based on CONFIG_WDOG_INIT.
This brings the KW4xZ in line with the other NXP Kinetis series SoC
implementations.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Move the NXP Kinetis KL2x watchdog initialization code to
z_arm_watchdog_init() and make it optional based on
CONFIG_WDOG_INIT.
This brings the KL2x in line with the other NXP Kinetis series SoC
implementations.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The driver for STM32's independent watchdog already exists and is
compatible with the stm32l1 SoC. Enable the independent watchdog
for the stm32l1 series for use with this driver.
Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr>
Instead of having TI_CCFG_PRESENT as a symbol that's only defined in
soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.series and y when
SOC_SERIES_CC13X2_CC26X2 is enabled, turn it into a helper symbol that's
selected by SOC_SERIES_CC13X2_CC26X2.
This avoids having a symbol that's only defined in a Kconfig.defconfig
file, which is confusing. It also makes things a bit more generic, in
case other boards with CCFGs are added.
Also rename it to HAS_TI_CCFG to be consistent with other helper
symbols, and add a help text.
Flagged by scripts/kconfig/lint.py.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Added delay before starting low frequency clock for the first time to
ensure that anomaly conditions are not met. Delay is configurable and
might be disabled.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
This reverts commit 49bd19f3f2,
as the patch it contains is no longer needed after nrfx is updated
to version 2.1.0.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Update the hal_nordic module revision, to switch to nrfx 2.1.0.
Because the list of peripherals for nRF5340 has changed as follows:
- SPIM2 has been renamed to SPIM4
- SPIM2-3, SPIS2-3, TWIM2-3, TWIS2-3, and UARTE2-3 have been added
a couple of related corrections needed to be applied in dts and Kconfig
files, plus the spi_nrfx_spim driver has been extended with the support
for SPIM4.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Remove soc/arm/st_stm32/stm32YY/flash_registers.h files.
Change register accesses in stm32 flash drivers to use FLASH_TypeDef
from modules/hal/stm32/stm32cube/stm32YYxx/soc/stm32xxxxxx.h.
Fixes#16235
Signed-off-by: Sarvesh Patkar <psarvesh314@gmail.com>
when DMA IP is enabled on stm32 series,
the heap size must be configured to large value
because of dma channels configuration.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The build infrastructure should not be adding the drivers subdirectory
to the include path. Fix the legacy uses that depended on that
addition.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The build infrastructure should not be adding the drivers subdirectory
to the include path. Fix the legacy uses that depended on that
addition.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Same deal as in commit 677f1e6 ("config: Turn pointless/confusing
'menuconfig's into 'config's"), for a newly-introduced stuff.
Also clean up headers to be consistent with recent cleanups.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
In zephyr_linker_sources().
This is done since the point of the location is to place things at given
offsets. This can only be done consistenly if the linker code is placed
into the _first_ section.
All uses of TEXT_START are replaced with ROM_START.
ROM_START is only supported in some arches, as some arches have several
custom sections before text. These don't currently have ROM_START or
TEXT_START available, but that could be added with a bit of refactoring
in their linker script.
No SORT_KEYs are changed.
This also fixes an error introduced when TEXT_START was added, where
TEXT_SECTION_OFFSET was applied to riscv's common linker.ld instead of
to openisa_rv32m1's specific linker.ld.
Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
CPU_CORTEX_M_HAS_DWT depends on
!CPU_CORTEX_M0 && !CPU_CORTEX_M0PLUS
, but SOC_SERIES_PSOC62 unconditionally selects it, even for
SOC_PSOC6_M0. This forces CPU_CORTEX_M_HAS_DWT on on Cortex-M0.
Fix it by moving the selects for CPU capabilities to the more specific
SOC_PSOC6_{M0,M4} symbols. This seems more readable than adding a
condition to the 'select CPU_CORTEX_M_HAS_DWT'.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
nrf52811_pca10056 board should enable nRF 802.15.4 radio driver
automatically when 802.15.4 subsystem is enabled, as other Nordic
802.15.4-compliant boards do.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Enable the RTC counter present in the NXP K6x SoC if CONFIG_COUNTER is
enabled. Add the needed dts fixup for the RTC device.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
CPU_CORTEX_M_HAS_SYSTICK and CPU_CORTEX_M_HAS_VTOR do not need
to be explicitely selected in SoC/Boards definitions of
platforms implementing the Cortex-M mainline architecture; they
are already selected by ARMV7_M_ARM8_M_MAINLINE Kconfig symbol.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The Data Watchpoint and Trace (DWT) is an optional debug unit
for the Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+)
that provides watchpoints, data tracing and system profiling
capabilities. We select it for the ARM Cortex-M SoCs
- Beetle
- Musca A, Musca B
since it is present in these SoCs.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The Data Watchpoint and Trace (DWT) is an optional debug unit for the
Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides
watchpoints, data tracing and system profiling capabilities.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The SoC, driver, and board support for the CC2650 and CC2650 Sensortag
aren't currently supported and we are removing them as such. If anyone
is interesting in supporting this platform we can easily recovery it
from git.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
generated_dts_board.h is pretty redundant and confusing as a name. Call
it devicetree.h instead.
dts.h would be another option, but DTS stands for "devicetree source"
and is the source code format, so it's a bit confusing too.
The replacement was done by grepping for 'generated_dts_board' and
'GENERATED_DTS_BOARD'.
Two build diagram and input-output SVG files were updated as well, along
with misc. documentation.
hal_ti, mcuboot, and ci-tools updates are included too, in the west.yml
update.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Enable the bandgap buffer on the NXP Kinetis K6x SoC series Power
Management Controller (PMC) if the internal temperature sensor is in
use.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Added dts additions for stm32 nucleo f767zi board, also added
and modified soc addtions for thet board.
Updated dts reference file name.
Updated yaml to take out adc for now.
Signed-off-by: Roland Ma <rolandma@yahoo.com>
Refactors the mcux wdog driver to use generated device tree macros
directly. Removes now unused dts fixup macros from kinetis socs.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Refactors the mcux rtc driver to use generated device tree macros
directly. Removes now unused dts fixup macros from kinetis socs.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Refactors the mcux dspi driver to use generated device tree macros
directly. Removes now unused dts fixup macros from kinetis socs.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Refactors the mcux lpsci driver to use generated device tree macros
directly. Removes now unused dts fixup macros from i.mx rt and kinetis
socs.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Refactors the mcux uart driver to use generated device tree macros
directly. Removes now unused dts fixup macros from kinetis socs.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Refactors the mcux lpi2c driver to use generated device tree macros
directly. Removes now unused dts fixup macros from kinetis socs.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The counter_basic_api test was broken for i.mx rt boards when we
refactored the mcux gpt driver to use generated device tree macros in
commit b8ad9969ef.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Refactors the mcux gpt driver to use generated device tree macros
directly. Removes now unused dts fixup macros from i.mx rt socs.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Refactors the mcux igpio driver to use generated device tree macros
directly. Removes now unused dts fixup macros from i.mx rt socs.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Refactors the mcux lpuart driver to use generated device tree macros
directly. Removes now unused dts fixup macros from i.mx rt and kinetis
socs.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Refactors the mcux lpi2c driver to use generated device tree macros
directly. Removes now unused dts fixup macros from i.mx rt and kinetis
socs.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adding Kconfig settings to warn anyone trying to build for this
platform of its pending deprecation in 2.2.0.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
This commit adds support for the on-board flash MX25R8035F that is
directly connected to the efr32fg soc.
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
This commit adds support for the on-board flash MX25R8035F that is
directly connected to the efr32mg soc.
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
This commit relocates the exception vector table address range
configuration routine that was previously implemented as part of
Cortex-R architecture reset function to SoC platform-specific
initialisation routine.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The Xilinx ZynqMP SoC embeds both Cortex-R "RPU" and Cortex-A "APU"
cores.
Since the current Zephyr architecture cannot support AMP of Cortex-R
and Cortex-A within the same project, the RPU and APU should be
considered separate platforms and handled accordingly.
This commit re-purposes the SOC_XILINX_ZYNQMP symbol as a helper symbol
indicating that Xilinx ZynqMP SoC is used, and adds a new symbol,
SOC_XILINX_ZYNQMP_RPU, for specifying the actual build target platform.
When Cortex-A support is added in the future, SOC_XILINX_ZYNQMP_APU
symbol should be added and used to conditionally handle APU-specific
code.
For more details, refer to the issue #20217.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Rename the NXP FTM instances in the KE1xF SoC to PWM to match the
other SoCs/boards using the FlexTimer as PWM generator.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Make sure light sleep hook function is compile when needed
This solves linking error for shippable test that only enable
light sleep.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
This patch adds a temporary workaround for the incorrect initialization
of the SystemCoreClock global variable that is done for the application
core of nRF5340 (see system_nrf5340_application.c) and that results in
k_busy_wait() producing delays of twice the requested time.
The problem is that the call to SystemCoreClockUpdate() that is done
at the end of SystemInit() correctly sets the value of SystemCoreClock
to reflect the hardware state after reset (HFCLK128M divided by 2),
but then the SystemCoreClock variable is initialized (by z_data_copy()
called from z_arm_prep_c()) to the __SYSTEM_CLOCK value that is defined
as 128000000. This in turn results in nrfx_coredep_delay_us() (used by
k_busy_wait() by default for nRF SoCs) delaying for twice the requested
number of microseconds.
The temporary workaround is to call SystemCoreClockUpdate() at a later
stage of the system initialization, in its nRF53 specific part.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The RTC peripheral found in the SAMD5x/SAME5x MCUs is very
simmilar to the one found in existing sam0 devices with only
a few changes to register names and the clock source selection.
Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
Before introducing the code for ARM64 (AArch64) we need to relocate the
current ARM code to a new AArch32 sub-directory. For now we can assume
that no code is shared between ARM and ARM64.
There are no functional changes. The code is moved to the new location
and the file paths are fixed to reflect this change.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The current GIC configuration scheme is designed to support only one
specific type and version of GIC (i.e. GIC-400 that implements the
GICv2 interface).
This commit adds a set of GIC version configuration symbols that can
be selected by the SoC configuration to specify which version of GIC
interface is implemented in the SoC.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
nrf51 and nrf52 by default was enabling temperature sensor if sensor
API was enabled. It was causing code size increase even when
temperature sensor was not touched by anyone. Removed default enabling
of temperature sensor for both series.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
This patch enables SPI4 on the 96Boards STM32 Sensors Mezzanine.
SPI4 has been broken out to a Grove Connector on the board.
Changes:
- Updated board dts to enable spi4
- Updated board Kconfig
- Updated board documentation
- Update board pinmux
- Updated stm32f4 pinmux header file
- Updated stm32f401 dtsi
- Updated stm32f4 defconfig to enable PORTE GPIO
- Added board to spi_loopback test
Test: spi_loopback test passed
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
Setting EEPROM_STM32 with `default y` under `if SOC_FAMILY_STM32`
overrides `depends on SOC_SERIES_STM32L1X` in EEPROM_STM32
definition.
Then, if ever EEPROM is set in any file (as in
tests/drivers/build_all`), EEPROM_STM32 will be indeed set,
with potential issues on series where driver is not yet correctly
handled.
Fix this by removing EEPROM_STM32 definition in STM32 generic
file and set `default y` along with the `depends on` to keep
it effective.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Commit 94bed60abea53818c8cd723e233799a77c4b4e4b introduced separate
DT symbols for SPI and SPIM. Update dts_fixup.h for all nRF chips
to align with those changes.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
Commit a8a85c21cff7319e80af16688ea6076594fab7c8 introduced separate
DT symbols for TWI and TWIM. Update dts_fixup.h for all nRF chips
to align with those changes.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
Uses the generated device tree macros, DT_NXP_LPC_USART_USART_*, in the
mcux flexcomm driver and removes the now unused dts fixups from the
lpc54xxx and lpc55xxx socs.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Renames the lpc usart shim driver to more accurately reflect the
flexcomm hardware IP and to prepare for instantiating it on an SoC
outside the LPC family.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
When CONFIG_SYS_POWER_DEEP_SLEEP_STATES is not set, we have an unused
function that causes a build failure.
Enclose that function in the #ifdef.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Remove leading/trailing blank lines in .c, .h, .py, .rst, .yml, and
.yaml files.
Will avoid failures with the new CI test in
https://github.com/zephyrproject-rtos/ci-tools/pull/112, though it only
checks changed files.
Move the 'target-notes' target in boards/xtensa/odroid_go/doc/index.rst
to get rid of the trailing blank line there. It was probably misplaced.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Enables the high-speed spi instance 8 on the lpcxpresso55s69 board.
Configures pinmuxes and clocks, and updates board documentation
accordingly.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
As ISR stack size depends on application code, its best set
in the application's prj.conf file. Hence, remove it from
soc Kconfig files.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Add device tree fixups for the NXP LPI2C bus timeout property to the
NXP i.MX RT and Kineties KE1xF SoC series.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Created MEC1501 deep and light sleep example for MCHP MEC1501.
Modifications were made to SoC, board, timer, and hello world
sample program. Power management split into SoC power
implementing the interface and device power for device specific
logic.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
We remove the custom fixed MPU region definition from ST
STM32 SoC definitions, as the common fixed MPU
region definition is now used.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We remove the custom fixed MPU region definition from ARM
- Beetle
- Musca_a
- Musca_b1
- MPS2 (an385 and an521)
SoC definitions, as the common fixed MPU region definition
is now used.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We remove the custom fixed MPU region definition from Silicon
Labs exx32 SoC definitions, as the common fixed MPU region
definition is now used.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
For the NXP Kinetis SoCs with the NXP MPU regions, we keep
the confiruation of the fixed SoC MPU regions at each SoC
definition.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We remove the custom fixed MPU region definition from NXP IMX
RT, Kinetis, and LPC SoC definitions, as the common fixed MPU
region definition is now used.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We remove the custom fixed MPU region definition from Atmel
SAM SoC definition, as the common fixed MPU region definition
is now used.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We remove the custom fixed MPU region definition from Nordic
nRF SoC definition, as the common fixed MPU region definition
is now used.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We move the configuration of the fixed MPU regions for ARM
Cortex-M SoCs in a common place under soc/arm/common/cortex-m,
instead of having this configuration present in each ARM SoC or
SoC Series definition. The rationale behind this is that for all
SoCs the fixed MPU regions configured at SoC definition are only
used for enforcing default Flash and SRAM access policies, and
currently, this is common to all ARM SoCs with MPU support.
We also simplify the Flash and SRAM MPU region definition,
aiming at using a single MPU region index to program each
of them.
We still support the possibility for ARM SoCs to opt-out and,
instead, define their own custom fixed MPU regions at SoC
definition. We do it using a Kconfig option, introduced
explicitly for this purpose.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Bool symbols implicitly default to 'n'.
A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though.
Also replace some
config
prompt "foo"
bool/int
with the more common shorthand
config
bool/int "foo"
See the 'Style recommendations and shorthands' section in
https://docs.zephyrproject.org/latest/guides/kconfig/index.html.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
The type of SOC_ATMEL_SAME70_DISABLE_ERASE_PIN is bool, yet its default
is specified as an int value of 0.
This commit removes the implied `default 0`, which is equivalent to
`default n`.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This header contains encoding offsets for all the eSPI channels which
communicate data from/to the host.
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
Enable SWO debug output during system initialization and not as part of
GPIO driver initialization. After the modification the logger output
becomes available earlier during the boot process. Also, it's not
necessary anymore to build full GPIO driver only to enable SWO. This may
be critical when building small images.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
We need to fix the formato of the macros for nRF CACHE and NVMC
peripherals in soc.c, so the _S and _NS suffixes are skipped.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Since the nRF5340 DK contains the required DC/DC circuitry,
enable it by default while keeping it configurable. This
reduces power consumption in application core , network
core and high voltage use.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Add device tree elements for all gpio ports of the efr32mg12p including
the dts fixup entries.
Also remove gpio port e since this is not available in efr32mg12p socs.
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
SoC initialization had an incorrect comment regarding system clock.
Corrected from 48Mhz -> 96Mhz.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
This commit adds basic support for nRF52833 SoC.
Changes affect introducing:
- architecuture files (dtsi)
- configuration of nrfx drivers
- adaptation of inclusions based on chosen SoC
- configuration of NFCT_PINS_AS_GPIOS depends on HAS_HW_NRF_NFCT.
Signed-off-by: Emil Obalski <emil.obalski@nordicsemi.no>
This patch introduces the support of the Low Power Timer
for the STM32WBxx from STMicroelectronics.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Enables the arm v7m mpu on the efr32mg soc and the board
efr32mg_sltb004a.
Tested on hardware with samples/mpu/mpu_test and
tests/kernel/mem_protect
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
This patch introduces the support of the Low Power Timer
for the STM32L4xx from STMicroelectronics.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Calls to nrfx HAL functions in various nRF platform related source
files are complemented with pointers to relevant peripherals.
Additionally, TIMER HAL functions that got renamed in nrfx 2.0.0 are
updated in the qemu_cortex_m0 board supporting code.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Update the hal_nordic module revision to switch to nrfx 2.0.0.
Add Kconfig options that enable to use the newly introduced nrfx
drivers in Zephyr.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Promote the private z_arch_* namespace, which specifies
the interface between the core kernel and the
architecture code, to a new top-level namespace named
arch_*.
This allows our documentation generation to create
online documentation for this set of interfaces,
and this set of interfaces is worth treating in a
more formal way anyway.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
There is no imx ccm shim driver in drivers/clock_control. This config
was only used to conditionally compile nxp hal drivers, even though the
imx6/7 soc init always needs them.
Updates the nxp hal to unconditionally compile the ccm drivers and
removes the unnecessary config symbol.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This adds supoprt for the Atmel SAME53 SoC.
The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals
with the sam0 Cortex-M0+ and saml1x Cortex-M23 parts.
Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
This adds supoprt for the Atmel SAME51 SoC.
The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals
with the sam0 Cortex-M0+ and saml1x Cortex-M23 parts.
Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
This adds supoprt for the Atmel SAMD51 SoC.
The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals
with the sam0 Cortex-M0+ and saml1x Cortex-M23 parts.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
The SERCOMS on SAMD5x/SAME5x are connected to different MCLK
APBMASKs. There is no systematic way to tell whether a SERCOM
is connected to APBA, APBB, APBC or APBD, so rely on the
information from ASF instead of replicating it elsewhere.
This is needed for SPI, I2C and UART support on the SAMD5x/SAME5x
platform.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
This adds supoprt for the Atmel SAME54 SoC.
The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals
with the sam0 Cortex-M0+ and saml1x Cortex-M23 parts.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
This commit refactors kernel and arch headers to establish a boundary
between private and public interface headers.
The refactoring strategy used in this commit is detailed in the issue
This commit introduces the following major changes:
1. Establish a clear boundary between private and public headers by
removing "kernel/include" and "arch/*/include" from the global
include paths. Ideally, only kernel/ and arch/*/ source files should
reference the headers in these directories. If these headers must be
used by a component, these include paths shall be manually added to
the CMakeLists.txt file of the component. This is intended to
discourage applications from including private kernel and arch
headers either knowingly and unknowingly.
- kernel/include/ (PRIVATE)
This directory contains the private headers that provide private
kernel definitions which should not be visible outside the kernel
and arch source code. All public kernel definitions must be added
to an appropriate header located under include/.
- arch/*/include/ (PRIVATE)
This directory contains the private headers that provide private
architecture-specific definitions which should not be visible
outside the arch and kernel source code. All public architecture-
specific definitions must be added to an appropriate header located
under include/arch/*/.
- include/ AND include/sys/ (PUBLIC)
This directory contains the public headers that provide public
kernel definitions which can be referenced by both kernel and
application code.
- include/arch/*/ (PUBLIC)
This directory contains the public headers that provide public
architecture-specific definitions which can be referenced by both
kernel and application code.
2. Split arch_interface.h into "kernel-to-arch interface" and "public
arch interface" divisions.
- kernel/include/kernel_arch_interface.h
* provides private "kernel-to-arch interface" definition.
* includes arch/*/include/kernel_arch_func.h to ensure that the
interface function implementations are always available.
* includes sys/arch_interface.h so that public arch interface
definitions are automatically included when including this file.
- arch/*/include/kernel_arch_func.h
* provides architecture-specific "kernel-to-arch interface"
implementation.
* only the functions that will be used in kernel and arch source
files are defined here.
- include/sys/arch_interface.h
* provides "public arch interface" definition.
* includes include/arch/arch_inlines.h to ensure that the
architecture-specific public inline interface function
implementations are always available.
- include/arch/arch_inlines.h
* includes architecture-specific arch_inlines.h in
include/arch/*/arch_inline.h.
- include/arch/*/arch_inline.h
* provides architecture-specific "public arch interface" inline
function implementation.
* supersedes include/sys/arch_inline.h.
3. Refactor kernel and the existing architecture implementations.
- Remove circular dependency of kernel and arch headers. The
following general rules should be observed:
* Never include any private headers from public headers
* Never include kernel_internal.h in kernel_arch_data.h
* Always include kernel_arch_data.h from kernel_arch_func.h
* Never include kernel.h from kernel_struct.h either directly or
indirectly. Only add the kernel structures that must be referenced
from public arch headers in this file.
- Relocate syscall_handler.h to include/ so it can be used in the
public code. This is necessary because many user-mode public codes
reference the functions defined in this header.
- Relocate kernel_arch_thread.h to include/arch/*/thread.h. This is
necessary to provide architecture-specific thread definition for
'struct k_thread' in kernel.h.
- Remove any private header dependencies from public headers using
the following methods:
* If dependency is not required, simply omit
* If dependency is required,
- Relocate a portion of the required dependencies from the
private header to an appropriate public header OR
- Relocate the required private header to make it public.
This commit supersedes #20047, addresses #19666, and fixes#3056.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Replace CONFIG_WDT_0_NAME with DT_ALIAS_WATCHDOG_0_LABEL in samples and
test code. Now that all drivers are DT aware we don't ever set the
Kconfig option.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds driver support for DMA on f0/f1/f2/f3/f4/l0/l4
series stm32.
Notice due to some bugs, this is currently not working with f7.
There are two kinds of IP blocks are used across these stm32, one is the
one that has been used on F2/F4/F7 series, and the other one is the one
that has been used on F0/F1/F3/L0/L4 series.
Memory to memory transfer is only supported on the second DMA on
F2/F4 with 'st,mem2mem' to be declared in dts.
This driver depends on k_malloc to allocate memory for stream instances,
so CONFIG_HEAP_MEM_POOL_SIZE must be big enough to hold them.
Common parts of the driver are in dma_stm32.c and SoC related parts are
implemented in dma_stm32_v*.c.
This driver has been tested on multiple nucleo boards, including
NUCLEO_F091RC/F103RB/F207ZG/F302R8/F401RE/L073RZ/L476RG with the
loop_transfer and chan_blen_transfer test cases.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
This commit moves DMA parameters previously hard coded in the driver
to the dts.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
1) Add cryptographically secure random functions to provide
FIPS 140-2 compliant random functions.
2) Add name to random function choice selectors to ease
selection in SOC .defconfig files
3) Add bulk fill random functions.
Signed-off-by: David Leach <david.leach@nxp.com>
Introduce a Kconfig symbol that utilizes a dt function to determine if
we have STM32 CCM functionality being utilized. This removes the
dependance on parsing symbols from generated_dts_board.conf.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Use this short header style in all Kconfig files:
# <description>
# <copyright>
# <license>
...
Also change all <description>s from
# Kconfig[.extension] - Foo-related options
to just
# Foo-related options
It's clear enough that it's about Kconfig.
The <description> cleanup was done with this command, along with some
manual cleanup (big letter at the start, etc.)
git ls-files '*Kconfig*' | \
xargs sed -i -E '1 s/#\s*Kconfig[\w.-]*\s*-\s*/# /'
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Clean up space errors and use a consistent style throughout the Kconfig
files. This makes reading the Kconfig files more distraction-free, helps
with grepping, and encourages the same style getting copied around
everywhere (meaning another pass hopefully won't be needed).
Go for the most common style:
- Indent properties with a single tab, including for choices.
Properties on choices work exactly the same syntactically as
properties on symbols, so not sure how the no-indentation thing
happened.
- Indent help texts with a tab followed by two spaces
- Put a space between 'config' and the symbol name, not a tab. This
also helps when grepping for definitions.
- Do '# A comment' instead of '#A comment'
I tweaked Kconfiglib a bit to find most of the stuff.
Some help texts were reflowed to 79 columns with 'gq' in Vim as well,
though not all, because I was afraid I'd accidentally mess up
formatting.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Move the definition of INIT_ENET_PLL to soc/arm/nxp_imx/rt/Kconfig.soc,
which is where the other INIT_*_PLL symbols are defined, and consistenly
enable it with 'select' like for the other symbols, instead of via
Kconfig.defconfig.mimxrt{1052,1062,1064}.
Remove an old empty INIT_ENET_PLL definition from
soc/arm/nxp_imx/rt/Kconfig.defconfig.series, which was just there to
hack around a dependency on NET_L2_ETHERNET. If the symbol does not
depend on NET_L2_ETHERNET in all cases, it's better to not add the
dependency.
Also add a help text to hint what's going on there.
Found with a script (INIT_ENET_PLL was only defined in Kconfig.defconfig
files).
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
SOC_SERIES is already defined with a type in arch/Kconfig, which is
always included.
Trying to get rid of unnecessary "full" symbol definitions in
Kconfig.defconfig files, to make the organization clearer. It can also
help with finding unused symbols.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Put a common definition of the SOC_PART_NUMBER symbol in
soc/arm/Kconfig, to make it always available for ARM SoCs. Have the
other definitions extend the base definition, without repeating the
type.
Also put the help text on just the base definition. It will show up in
the generated documentation and when looking at the symbol information
at any of the definition locations in the menuconfig (after going into
show-all mode).
Trying to get rid of unnecessary "full" symbol definitions in
Kconfig.defconfig files, to make the organization clearer. It can also
help with finding unused symbols.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Add a common definition for NUM_IRQS in arch/arm/core/Kconfig and
arch/riscv/Kconfig. That way, the type doesn't have to be given for
NUM_IRQS in all the Kconfig.defconfig files.
Trying to get rid of unnecessary "full" symbol definitions in
Kconfig.defconfig files, to make the organization clearer. It can also
help with finding unused symbols.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Same deal as in commit 7fdb525754 ("kconfig: Use 'default' instead of
'def_bool' in Kconfig.defconfig files"), but I hacked Kconfiglib to also
find cases where the type is given separately as e.g.
config FOO
int
default 3
Motivation (from a note in
https://docs.zephyrproject.org/latest/guides/kconfig/index.html):
For a symbol defined in multiple locations (e.g., in a
Kconfig.defconfig file in Zephyr), it is best to only give the
symbol type for the "base" definition of the symbol, and to use
'default' (instead of 'def_<type>' value) for the remaining
definitions. That way, if the base definition of the symbol is
removed, the symbol ends up without a type, which generates a
warning that points to the other definitions. That makes the extra
definitions easier to discover and remove.
It's also nice if 'def_bool' and the like turn into a semi-reliable flag
that the symbol is only defined in Kconfig.defconfig files. That might
be a sign that things could be cleaned up.
Will do a separate pass later to remove some symbols only defined in
Kconfig.defconfig files.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Replace:
dt_chosen_reg_addr
dt_chosen_reg_size
dt_node_reg_addr
dt_node_reg_size
with:
dt_chosen_reg_addr_int
dt_chosen_reg_size_int
dt_chosen_reg_addr_hex
dt_chosen_reg_size_hex
dt_node_reg_addr_int
dt_node_reg_size_int
dt_node_reg_addr_hex
dt_node_reg_size_hex
So that we get the proper formatted string for the type of symbol.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that everything is DT based for I2C drivers we can rename the
CONFIG_I2C_[0..5]_NAME define to DT_I2C_[0..5]_NAME.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add binding for arm,mps2-fpgaio-gpio and update device tree and change
FPGA GPIO init code to utilize device tree defines.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Configures the default sdhc driver for the imx rt soc series so
applications don't have to configure it explicitly.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Unused after commit 4973787c10 ("pinmux: Remove the k64 pinmux driver").
Found with a script.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Move the selection of the IP clock source for the modules in the NXP
Kinetis KE1xF SoCs from being hardcoded in soc.c to being specified in
the device tree.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add missing definitions for the base addresses of the NXP LPUARTs to
the NXP KE1xF SoC DTS fixup.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
For nordic_nrf, this commit relocates HAS_CMSIS_CORE selection from
SoC Kconfig to the HAL module Kconfig, as done for other SoCs.
For nxp_kinetis, remove redundant HAS_CMSIS_CORE selection in SoC
Kconfig, as it is already selected by the HAL Kconfig.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit updates all references to HAS_CMSIS to use HAS_CMSIS_CORE
instead. With the changes introduced to allow multiple CMSIS variants
to be specified, the latter is semantically equivalent to the former.
For more details, see issue #19717.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
STM32L151XB-A SoC is almost similar to the STM32L151XB SoC except that
it has more RAM (32KiB). Hence add devicetree and Kconfig support.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Remove the inclusion of kernel_includes.h from soc.h and replace
it with including the board-specific auto-generated headers. This
aligns the soc.h header with the current policy not to include
kernel headers in soc.h.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We enable Memory Protection on stm32 nucleo_g071rb board,
since the respective SoC series implements the ARM MPU.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Remove the
# Omit prompt to signify a "hidden" option
comments that appear on some symbols. They seem to have been copy-pasted
at random, as there are lots of promptless symbols that don't have them
(that's confusing in itself, because it might give the idea that the
ones with comments are special in some way).
I suspect those comments wouldn't have helped me much if I didn't know
Kconfig either. There's a lot more Kconfig documentation now too, e.g.
https://docs.zephyrproject.org/latest/guides/kconfig/index.html.
Keep some comments that give more information than the symbol having no
prompt.
Also do some minor drive-by cleanup.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
STM32L1 uses the same spi controller as STM32F1 so we can just set the
right addresses and enable them. We also need to add the fixup names and
to correctly include the header for ST LL HAL.
Signed-off-by: Karl Palsson <karlp@etactica.com>
Move systick activation in soc/ as a Kconfig.defconfig file and
remove activation in boards _defconfig files.
This will allow to deactivate it in a more flexible way
with upcoming LPTIMER as tick source when power management
features are enabled.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
For LL header inclusion, use _STM32 Kconfig symbol
(related to the driver), rather than generic symbol,
that could theoretically use an alternate solution.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The patch adds initial support for STM32F030X4 SoC.
STM32F0 Cube package advises to use 'stm32f030x6' code
for both STM32F030x4 and STM32F030x6 SoC variants.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Add soc and dts files to support for most of the common peripherals
in the STM32G4 series. Add specific support for the STM32G431RB.
Signed-off-by: Richard Osterloh <richard.osterloh@gmail.com>
Add KConfig board support to match board jumper settings
Failing to update bank selection will affect GPIOs tied to VTR3
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
This patch re-namespaces global variables and functions
that are used only within the arch/arm/ code to be
prefixed with z_arm_.
Some instances of CamelCase have been corrected.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Add a set of build time assertions that checks if the peripheral base
addresses defined in dts nodes match the values provided by nrfx/MDK.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Enable CMSDK GPIO driver on v2m_musca_b1 SoC/Board. Add LEDs that are
on the board and init the pinmux for those LEDs to work.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This adds support for Kinestis K22
Co-authored-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Co-authored-by: Oliver Stäbler <oliver.staebler@bytesatwork.ch>
Co-authored-by: Tom Burdick <thomas.burdick@gmail.com>
Signed-off-by: Tom Burdick <thomas.burdick@gmail.com>
We shall not include core kernel headers in soc.h
header of ARM SoCs. We should try to only include
the vendor headers and auto-generated board header
from DTS. This commit implements this policy for
the SoCs, whose builds have shown to fail due to
header inclusion cycles.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This file contains redundant definitions of a bunch of nRF IRQ numbers
(not all, however) that only generates confusion, as enumeration values
provided by MDK can be used instead.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This change is done so that there is no need to additionaly include
<nrfx.h> before <soc/nrfx_coredep.h> (what might be a bit surprising)
and so that <nrfx_config.h> doesn't need to be include separately for
nRF SoCs requiring a special mapping of peripheral accessing symbols.
This commit removes also no longer needed inclusions and updates
the hal_nordic module with required minor correction of nrfx_glue.h.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Header files of nrfx HALs are not supposed to be included directly
but only with their names prepended with the hal/ directory (so that
an inclusion of an nrfx HAL header clearly differs from an inclusion
of an nrfx driver header).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
A commit that organizes the soc.h header of NXP SoCs:
- removing redundant inclusions of sys/util.h
- removing inclusions of device.h and kernel_includes.h
- including the auto-generated DTS board header
- including the fsl_common.h header
- fixing minor style issues
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We, now, have multiple nRF52x SoCs with 2.4GHz
Radio with LE Coded PHY Capabilities. Therefore,
we would like to have a Kconfig option and select
it in the corresponding SoCs. This allows us to
simplify several #ifdef blocks in the nRF Bluetooth
Controller that would, otherwise, require listing
all nRF SoCS with LE Coded PHY support.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Enable CMSDK GPIO driver on v2m_musca SoC/Board. Add LEDs that are on
the board and init the pinmux for those LEDs to work.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
A 16bits on/off based PWM, found on MEC1501.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add RTC timer driver for CC13X2/CC26X2, and use it instead of systick
as system clock. It is necessary to use this timer for power
management support, so that the system can exit from deep sleep upon
expiry of timeouts.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
No users of this driver after dropping quark platforms.
COUNTER_0_NAME was only defined by the QMSI driver and was defined but
not used in DTS fixup files of ateml_sam0 SoCs. Removing those leftover
defines as well.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
RT SOCs have several memory areas (OCRAMs, DTCM, ITCM, SDRAM, FLASH...)
but only two are selected for FLASH (code) and RAM (data).
It would be good to let the linker be aware about other regions, which
could then be used by drivers or application to create dedicated
sections and relocate memory. For example if we have code in ITCM and
data in DTCM, we still need a dma-able region/section for e.g.
video/camera buffers.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
There are 2 other timers that could be selected, let's just take the
first 32bits one. This should be sufficient to verify the driver.
Enabling the timer in relevant board's dts file as well.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Such basic timer is found on MEC150x for instance.
Since instances have dedicated data, let's define specifice instance
based on unique DT base address definition.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Refactors the kinetis flash configuration field so it can be shared
across all kinetis SoCs. Defaults are overridden for the k8x and ke1xf
series to preserve values used prior to this refactoring.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Kinetis SoCs have a 16-byte flash configuration field that must be
loaded at a specific address in flash. This field is not needed if we
are building an image to be chainloaded by MCUboot or a RAM-only image,
so we can exlude it in these cases and recover some wasted flash.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Convert use of dt_int_val/dt_hex_val to dt_node_reg_{addr,size}. As
we want to remove dt_int_val/dt_hex_val.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert how we get the various chosen properties like "zephyr,console"
to use the new kconfig functions like dt_chosen_to_label.
Because of how kconfig parses things we define a set of variables of the
form DT_CHOSEN_Z_<PROP> since comma's are parsed as field seperators in
macros.
This conversion allows us to remove code in gen_defines.py for the
following chosen properties:
zephyr,console
zephyr,shell-uart
zephyr,bt-uart
zephyr,uart-pipe
zephyr,bt-mon-uart
zephyr,uart-mcumgr
zephyr,bt-c2h-uart
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Configuration item custom busy wait is required for all MEC1501
series if its RTOS timer driver is enabled. We moved the selection
of the timer from board level to MEC1501 SoC level.
Frequency selection remains at the board level.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Enables the arm v7m mpu on the lpc54114 m4 core. Reuses the mpu
configuration from the i.mx rt, which has the same mpu.
Tested on hardware with tests/kernel/mem_protect
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The driver for STM32's independent watchdog already exists and is
compatible with the stm32wb SoC. Enable the independent watchdog
for the stm32wb series for use with this driver.
Signed-off-by: Robert Weber <robertweber95@gmail.com>
The KE1xF SoC family SIM unit differs from the other Kinetis family
SoCs. Add a unique compatiable and binding for it.
Fixes#18160
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Update the module revision so that the following commits become
effective:
* nrfx_config: Use common mappings of Kconfig options to nrfx macros
* nrfx_config: Unify the way of enabling instances in nrfx drivers
* nrfx_config: Add missing mappings of Kconfig option symbols
* CMakeLists: Add missing inclusions of driver implementation files
The above changes require a minor correction in the nrf91/soc.h file,
so it is also modified in this commit.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This patch adds HAS_SWO selections to all STM32 SoCs supporting Serial
Wire Output via the Trace Port Interface Unit (TPIU).
Signed-off-by: Markus Fuchs <markus.fuchs@de.sauter-bc.com>
This is required to get the watchdog test and sample working since the
required wdt device name macro is generic there.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
There are only 178 interrupt lines on CC3220SF. Hence we should not set
NUM_IRQS to a value exceeding that value. We are changing it to 178.
Fixes#18593
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Consistently place C++ use of extern "C" after all include directives,
within the negative branch of _ASMLANGUAGE if used.
Remove extern "C" support from files that don't declare objects or
functions.
Background from issue #17997:
Declarations that use C linkage should be placed within extern "C"
so the language linkage is correct when the header is included by
a C++ compiler.
Similarly #include directives should be outside the extern "C" to
ensure the language-specific default linkage is applied to any
declarations provided by the included header.
See: https://en.cppreference.com/w/cpp/language/language_linkage
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Remove extern "C" support from files that don't declare symbols subject
to language linkage effects.
Consistently place C++ use of extern "C" after all include directives,
within the negative branch of _ASMLANGUAGE if used.
Background from issue #17997:
Declarations that use C linkage should be placed within extern "C"
so the language linkage is correct when the header is included by
a C++ compiler.
Similarly #include directives should be outside the extern "C" to
ensure the language-specific default linkage is applied to any
declarations provided by the included header.
See: https://en.cppreference.com/w/cpp/language/language_linkage
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Move the tail include file outside the extern "C" block.
Background from issue #17997:
Declarations that use C linkage should be placed within extern "C"
so the language linkage is correct when the header is included by
a C++ compiler.
Similarly #include directives should be outside the extern "C" to
ensure the language-specific default linkage is applied to any
declarations provided by the included header.
See: https://en.cppreference.com/w/cpp/language/language_linkage
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Remove extern "C" support from files that don't declare symbols subject
to language linkage effects.
Background from issue #17997:
Declarations that use C linkage should be placed within extern "C"
so the language linkage is correct when the header is included by
a C++ compiler.
Similarly #include directives should be outside the extern "C" to
ensure the language-specific default linkage is applied to any
declarations provided by the included header.
See: https://en.cppreference.com/w/cpp/language/language_linkage
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
'timeout' needs to be a signed variable, so that the
check for less-than-zero is able to result to true (if
the timeout actually expires). Addresses the coverity
issue [Coverity CID :203493] reported in #18379.
Fixes#18379.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The HAL/SDK code for imx6sx utilizes floating point support in
CCM_ANALOG_GetPllFreq function which is utilized by drivers to determine
clock information. As such we should enable hardware FP support by
default so we don't get pure soft-float emulation and pull in a bunch of
extra code.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based
platform for Cortex-R based testing. This SoC only supports an
interrupt controller and serial port for limited testing.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
Use address based defines in the dts_fixup.h instead of DT_INST_ based
ones. The DT_INST_ will not get us the consistent mapping that is
needed (as we should assume the order of DT_INST_).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In nRF9160 the reset pin is a dedicated one, it cannot be configured
as a regular GPIO pin, so this option should not be presented to users
building for this SoC, to not generate confusion.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
In order to increase code coverage, we force building a Secure
Firmware image by default (i.e. with option
CONFIG_TRUSTED_EXECUTION_SECURE set), when building for
mps2_an521 board. CONFIG_TRUSTED_EXECUTION_SECURE enables
compiling-in all TrustZone-related code in the tree, that is,
all ARM-specific code inside #ifdef CONFIG_ARM_SECURE_FIRMWARE.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Use clock specified in the device tree for obtaining the source clock
frequency for the pwm_mcux_ftm driver instead of relying on having an
NXP Kinetis MCG clock available in all SoCs supporting FlexTimer (FTM)
modules.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Perform OTP override when selecting 32Khz internal oscillator
to ensure 32KHz is enabled.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
i.MX RT10XX processors have four eFlexPWM modules, each containing
four 2-channels PWM submodules.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Changes to MEC1501 HAL for eSPI changed loop constant used by SoC
code initializing the ECIA registers. Fixed by using HAL constants
that are invariant.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
pinmux: Add the relevant definition of the spi3 pin
dts: Fix a bug, spi3 does not have a label
soc: Supplement spi3 related definition
Signed-off-by: Findlay Feng <i@fengch.me>
Add a hidden Kconfig option indicating that a given SoC is equipped
with the IEEE 802.15.4 capable radio so that the corresponding driver
configuration can depend on it.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Because NXP MPU's regions are dynamically enabled/disabled, USB
device's access maybe restricted when switching out of a task.
Background DMA transfers to/from RAM may happen during MPU region
reconfiguration or core idling.
Enabled USB (Kinetis MPU Master 4) to always have access to RAM address
space.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
The SoC clock init code for USB was using a deprecated DTS define.
Switch to using the non-deprecated form.
Fixes: #17772
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a kernel timer driver for the MEC1501 32KHz RTOS timer.
This timer is a count down 32-bit counter clocked at a fixed
32768 Hz. It features one-shot, auto-reload, and halt count down
while the Cortex-M is halted by JTAG/SWD. This driver is based
on the new Intel local APIC driver. The driver was tuned for
accuracy at small sleep values. Added a work-around for RTOS
timer restart issue. RTOS timer driver requires board ticks per
second to be 32768 if tickless operation is configured.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
The uart_stellaris driver used system clock frequency
as a base for baudrate calculation. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The uart_msp432p4xx driver used system clock frequency
as a base for baudrate calculation. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The uart_pl011 driver used system clock frequency
as a base for baudrate calculation. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The log_backend_swo used system clock frequency
as a base for SWO clock calculation. This commit
corrects that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The SoC initialization code used timer clock frequency
as a system clock frequency. This commit corrects that by
obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The SoC initialization code used system clock frequency
as a CPU clock frequency. This commit corrects that by
obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The SoC initialization code used system clock frequency
as a CPU clock frequency. This commit corrects that by
obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The SoC initialization code used system clock frequency
as a CPU clock frequency. This commit corrects that by
obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The SoC initialization code used system clock frequency
as a CPU clock frequency. This commit corrects that by
obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The SoC initialization code used system clock frequency
as a CPU clock frequency. This commit corrects that by
obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The SoC initialization code used system clock frequency
as a CPU clock frequency. This commit corrects that by
obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The SoC initialization code used system clock frequency
as a CPU clock frequency. This commit corrects that by
obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The SoC initialization code used system clock frequency
as a CPU clock frequency. This commit corrects that by
obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The SoC initialization code used system clock frequency
as a CPU clock frequency. This commit corrects that by
obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The i2c_cc32xx driver used system clock frequency
as a base for I2C clock frequency calculation.
This commit corrects that by obtaining the needed value from DTS.
Please note, that for I2C devices the clock-frequency property
specifies SCK frequency, instead of frequency of the clock driving
peripheral. To solve that problem, a new property was added.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
Have the SoC dtsi files for microchip mark the devices (uart & i2c) as
disabled by default and let the board dts files enable which one's they
need/use (which is what's happening already).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Because NXP MPU's regions are dynamically enabled/disabled, ENET
device's access maybe restricted when switching out of a task.
Background DMA transfers from RAM to MAC/PHY may happen during MPU
region reconfiguration or core idling.
Enabled ENET (Kinetis MPU Master 3) to always have access to RAM address
space.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
This patch populates "clocks" property in stm32 usb nodes
for clock related usb configuration code of each dtsi files
Signed-off-by: Francois Ramu <francois.ramu@st.com>
uint8_array values are now generated as structure initializers. Update
the code accordingly. The implementation assumes that existing
devicetree source does not provide the correct OUI so preserves the
in-driver override of the value provided by devicetree and its setting
for random/unique addresses.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Implementation of pinmux of usdhc depends on board design.
Usdhc driver could change pinmux according to SD mode, SoC
should provide API for this. Board pinmux should register
its pinmux function to SoC.
Signed-off-by: Jun Yang <jun.yang@nxp.com>
Add flash support for STM32G0X SoC series.
Signed-off-by: Philippe Retornaz <philippe@shapescale.com
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This patch adds support for the STM32G071xx
from STMicroelectronics.
Signed-off-by: Philippe Retornaz <philippe@shapescale.com>
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Protect gpio_configure function in dual core context.
This operation is not needed for other fuctions of the api:
* init
* read
* write
Protecting gpio_configure also protects access to
interrupt_controller IP.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add support for C-M4 core on STM32H7 series.
It is enabled in Dual core context with 2 alternatives boot methods:
* Boot CM4 CM7: Both core boot at reset, then CM4 enters Stop mode.
CM7 performs system configuration then finally wakes up CM4
* Boot CM7, CM4 Gated: Only CM7 boots at reset. Once done with
system configuration it triggers (requires option byte update)
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Provide basic clock control driver for STM32H7.
Bus clock activation is done through CM7 and CM4 common registers
so we don't have to care to the CPU Id before accessing.
Accesses are not protected for now. Only possible configuration
is system clock source set to HSE driven PLL.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
As with the STM32 boards, these had an existing default for tick rate
that is now lower than the 10 kHz default. They're SysTick devices
that can handle the higher rate just fine. Use that.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The nRF timer runs at only 32 kHz, so there's little reason to try to
divide it to get a synthesized tick rate. Just use the raw clock as
the tick rate, which provides maximal precision and very
singnificantly simplifies the generated code for the ISR.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
UART related defines in STM32F7 files where filled with
references to USART.
Instances 4, 5, 7 and 8 of SoC serial port are actually UARTs.
So rename define's accordingly. Otherwise it couldn't build.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The IPC peripheral is missing from the list of
supported HW for nRF9160, so this commit adds
that.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The AN521 is a Soft Macro Model implementation of the SSE-200 subsystem
with SIE-200 and CMSDK components targeting the MPS2+ board. The
SSE-200 subsystem implements two Cortex-M33 cores.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
move misc/util.h to sys/util.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
move misc/slist.h to sys/slist.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
move misc/__assert.h to sys/__assert.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
move uart.h to drivers/uart.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
move sys_io.h to sys/sys_io.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
move power.h to power/power.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Enable the MCUX SCG clock controller driver by default for the NXP
Kinetis KE1xF SoC series. Move the generic CLKOUT configuration from
SoC to the clock controller driver.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Allow individual specification of the time quanta used for the CAN bus
propagation segment and phase segment 1.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Definition of obsolete FLASH_PAGE_SIZE Kconfig symbol was
remaining in STM32F3 soc files.
Clean these.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
stm32mp1 was adding a STM32 specific Core selection Kconfig
symbol while zephyr generic CPU_CORTEX_M4 could be used for the
same purpose.
Remove STM32 specific symbol and use generic one.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Change code from using now deprecated DT_<COMPAT>_<INSTANCE>_<PROP>
defines to using DT_INST_<INSTANCE>_<COMPAT>_<PROP>.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Sample was not compiling for nordic boards because RTC_0
instance was not enabled by default and RTC_0 device is using
different DT define.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
This commit adds counter driver based on RTCC module for SiLabs Gecko
SoCs.
Tested with SLWSTK6061A / BRD4250B wireless starter kit.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
These events aren't errors at all, but rather part of normal operation.
They shouldn't trigger error messages, especially given that the console
gets absolutely flooded with them if power management is activated.
Signed-off-by: Benjamin Lindqvist <benjamin.lindqvist@endian.se>
stm32wb55rg is a dual core SoC (M4/M0) with a radio/protocol stack
running on M0 core. M0 FW starts at flash address 0x80CB000.
So flash size available to zephyr is 812K instead of 1M.
Configure package size to reflect this (flash size is now 812K)
and update MPU setting to exclude M0 FW. From MPU point of view,
we set flash size to 512K since we should chose a size being a power
of 2.
If we consider there will be 2 images partitions in a FOTA scheme,
512 K is beyond image-0 and hence is sufficient to cover application
image.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32WB HCI driver requires definition of 2 RAM regions to support
use of 3 shared memory sections: MAPPING_TABLE, MB_MEM1 and MB_MEM2.
In linker.ld, under conditions of HCI driver to be enabled,
define SRAM1 and SRAM2 based on input defined in stm32wb linker.
Then define the 3 sections MAPPING_TABLE, MB_MEM1 and MB_MEM
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Several customer configuration (CCFG) settings are useful for
development and deployment. This commit adds support for setting CCFG
values via Kconfig. It follows TI's recommendation of setting CCFG
values and then including the TI provided CCFG. This commit includes
support for enabling the ROM bootloader and additional settings can be
added as needed.
Signed-off-by: Brett Witherspoon <spoonb@cdspooner.com>
soc_register.h is available in most of stm32 series.
It is sometime empty or contains includes to flash_registers.h,
which is included directly with direct reference in flash driver.
soc_register.h is also included in stm32 clock drivers, but this
driver do not use direct reference to any register anymore.
Clean up these files.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
tests/drivers/i2c/i2c_api wants to have CONFIG_I2C_0_NAME defined.
Add it to dts_fixup.h as was done for Watchdog and & timer.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
This adds support for the basic timer counter (TC) found on SAM0
series parts. This driver only supports running the counter
in 32 bit wide mode. Since this mode explicitly slaves the odd
counters to the even ones, only instances of the even ones are
defined.
Tested with tests/drivers/counter/counter_basic_api on SAMD21.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
Define pinmux base addresses from gpio bases. Pinmux
and gpio functionality are located in the same PCR register
for each pin.
Introduce pinmux Kconfig switches for the SOC.
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
This commit enforces platform-specific initialization
for nRF SoC family. The specific platform initialization
hook is invoked directly after reset and calls the nRFx
SystemInit() function.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add support for the Low Power Inter-Integrated Circuit (LPI2C)
controllers found in the NXP Kinetis KE1xF SoC series.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add option for enabling the Code Cache present on the NXP Kinetis
KE1xF SoC series and enable it by default.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Unlike Cortex-M3 and Cortex-M4, in Cortex-M7 the number of
MPU regions may vary based on the implementation. This commit
adds a DTS node for the ARM MPU peripheral in the device tree
of Cortex-M7 SoCs and updates the fixup files, so we may extract
the number of MPU regions at build time. SoCs:
- nxp_rt
- same70
- stm32f7
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds a DTS node for the ARM MPU peripheral in the
device tree of ARMv8-M SoCs (for the secure and the non-secure
DTS descriptions) and updates the fixup files. SoCs:
- nrf9160
- musca_a
- musca_b1
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
In kernel_arch_init() we initialize the ARM core (interrupt
setup, fault init, etc.) so we can also move z_clearfaults()
in the same function and skip invoking it in the SoC init
functions.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Sample walk through:
1. CPU 0 will wake up CPU 1 after initialization
2. CPU 1 will send to CPU 0 an interrupt over MHU0
3. CPU 0 return the same to CPU 1 when received MHU0 interrupt
4. Test done when CPU 1 received MHU0 interrupt
The wake up second core and private core ID are soc specific.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
The CONFIG_CLOCK_CONTROL and CONFIG_NRF_RTC_TIMER were
unconditionally selected when enabling any nRF SoC. But since
timers can be disabled in the kernel, depend instead on
CONFIG_SYS_CLOCK_EXISTS, which is only defined when kernel
timer support is included.
Note that ideally we would enable CONFIG_NRF_RTC_TIMER only, and
that would select CONFIG_CLOCK_CONTROL (on which the RTC timer
depends) but there is a circular Kconfig dependency that prevents
us from doing so.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Add support for NXP MCUX LPUART devices with separate IRQ lines for
transmit and receive status interrupts (e.g. the Kinetis KE1xF SoC
series).
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit adds basic support for nrf52811 in the arch SoC, dts
and nrfx folders.
The nRF52811 is a Bluetooth 5.1 Direction Finding SoC with comprehensive
protocol support.
The nRF52811 SoC is capable of the latest features of Bluetooth 5.1,
the most prominent being Direction Finding.
The radio in the nRF52811 SoC has comprehensive protocol capabilities,
including Bluetooth 5.1 Directing Finding, all Bluetooth 5 features,
802.15.4, Thread, Zigbee, ANT and 2.4 GHz proprietary.
It has 4 dBm TX power and has been optimized to offer the best RX
sensitivity of all SoCs in the nRF52 series.
Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
add usbd1 definition to rt dts file,
set EHCI controller config default value in rt1050 default config file,
add EHCI controller driver MACROs to dts_fixup.h,
initialize EHCI clock in rt soc.c
add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
Hex firmware file is convenient in some scenarios, like
generating signed firmware with `west sign`. So, enable
generating hex file.
Signed-off-by: Jun Li <jun.r.li@intel.com>
Macros and enums are included for supporting pin configuration
settings.
Entries to the dts_fixup were also included in order
to configure port level settings.
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
This commit adds driver support for ADC1 on all 8 supported series of
stm32 with resolution and conversion time selection and calibration.
Currently DMA is not supported for all series, and without it, zephyr
won't be able to catch up ADC's end of conversion interrupt, so this
version of the driver supports one channel conversion only. Users want
multi-channel conversion should use multiple sequences in their app
code.
This driver uses LL lib rather than HAL because the current HAL lib for
ADC will call HAL_DMA_* functions rather than using zephyr's common DMA
interface, so that way the driver will break the consistency of the
code.
This driver has been tested on multiple nucleo boards including
NUCLEO_F091RC/F103RB/F207ZG/F302R8/F401RE/F746ZG/L073RZ/L476RG and all
passed the test cases in tests/drivers/adc/adc_api. If the external ADC
line is floating, it may fail the tests since ADC may get 0V and the
test cases think 0 is failing. Connect it to any voltage source between
0-3.3V will help passing the test cases.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
All series of stm32 have at least one ADC instance and this commit adds
one ADC node to the root dts file of each soc, and also adds fixing up
mappings to them.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
The revision A and B of the chip are very close, so most of the code
will work if the wrong revision is selected. To avoid that, check that
the selected HAL and the chip CIDR match. Otherwise emit a warning
in the logs.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This patch adds support for the revision B of the SAM E70 SoC. It adds
all the rev B part numbers, and when users pick-up one of those part
numbers, the revision B HAL is used instead.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This adds interrupt support to the SAM0 GPIO driver. This is heavily
inspired by @nzmichaelh work in #5715. The primary difference
from that implementation is that here the External Interrupt
Controller (EIC) is separated out into an interrupt controller driver
that is less tightly coupled to the GPIO API. Instead it implements
more of a conversion from the EIC's own odd multiplexing to a more
traditional port and pin mask IRQ-like callback. Unfortunately,
through the EIC on the SAMD2x are relatively well behaved
in terms of pin to EIC line mappings, other chips that share the
peripheral interface are not. So the EIC driver implements a
per-line lookup to the pin and port pair using definitions extracted
from the ASF headers.
The EIC driver still makes some assumptions about how it will be used:
mostly it assumes exactly one callback per port. This should be fine
as the only intended user is the GPIO driver itself.
This has been tested with some simple programs and with
tests/drivers/gpio/gpio_basic_api on a SAMD21 breakout and an
adafruit_trinket_m0 board.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
This reverts commit bd24b31139.
While the test case failure described in #14186 is associated with the
cycle-based busy-wait implementation, that test is fragile, and fails
less frequently once the incongruence between ticks-per-second and the
32 KiHz RTC clock are resolved. It also assumes that the system clock
is more stable than the infrastructure underlying the the busy-wait
implementation, which is not necessarily true.
The gross inaccuracies in the standard busy-wait on Nordic described in
issue #11626 justify restoring the custom solution.
As this applies to all Nordic devices, move the setting to the top-level
Kconfig.defconfig.
See: https://github.com/zephyrproject-rtos/zephyr/issues/11626#issuecomment-487243369
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The default system clock on all Nordic devices is based on a 32 KiHz
(2^15 Hz) timer. Scheduling ticks requires that deadlines be specified
with a timer counter that aligns to a system clock. With the Zephyr
default 100 clocks-per-sec configuration this results in 100 ticks every
32700 ticks of the cycle timer. This reveals two problems:
* The uptime clock misrepresents elapsed time because it runs 0.208%
(68/32768) faster than the best available clock;
* Calculation of timer counter compare values often requires an integer
division and multiply operation to produce a value that's a multiple
of clock-ticks-per-second.
Integer division on the Cortex-M1 nRF51 is done in software with a
(value-dependent) algorithm with a non-constant runtime that can be
significant. This can produce missed Bluetooth deadlines as discussed
in upstream #14577 and others.
By changing the default divisor to one that evenly divides the 2^15
clock rate the time interrupts are disabled to manage timers is
significantly reduced, as is the error between uptime and real time. Do
this at the top level, moving SYS_CLOCK_HW_CYCLES_PER_SEC there as well
since the two parameters are related.
Note that the central_hr configuration described in upstream #13610 does
not distinguish latency due to timer management from other
irq_block/spinlock regions, and the maximum observed latency will still
exceed the nominal 10 us allowed maximum. However this does occur
much less frequently than changing the timer deadline which can happen
multiple times per tick.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Add initial support for the TI CC13x2 / CC26x2 series with the CC2652R
and CC1352R SoCs. The UART and GPIO peripherals are supported. Drivers
use the driverlib HAL from the TI CC13x2 / CC26x2 SDK.
Signed-off-by: Brett Witherspoon <spoonb@cdspooner.com>
Add support for stm32mp1 basic UART API with Zephyr.
UART Console and UART shell are also supported.
Async UART API and USART support is to be done.
Signed-off-by: Yaël Boutreux <yael.boutreux@st.com>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Move SERCOM peripherals to use the raw defines generated from DTS
parsing. This adds aliases to the DTS so that the SERCOM number
can still be used for clocking and pinmux.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
This adds support for the async API for SAM0 SERCOM SPI using
DMA to drive the device. This implementation does the reload
for both transmit and receive in the receive DMA handler.
Doing this simplifies the implementation but means that the
transmit drains completely, resulting in the SPI clock pausing
between buffers while both are reloaded in the receive handler.
Tested with tests/drivers/spi/spi_loopback and several simple
programs monitored with a logic analyzer.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
Initial support for Microchip MEC1501 series is added to the tree.
Additional support for UART is also included. This SoC supports
two operational modes for interrupts (Direct and Aggregated). For
this commit, the direct capable interrupt are configured in direct
mode.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add a Kconfig option to enable DMA for SPI with SOC_NRF52832 as long as
it being disabled due to Product Anomaly Notice (PAN) 58 is explicitly
overridden. This allows the SPIM driver to be enabled for the nRF52832
SoC for situations where PAN 58 is not a problem.
Signed-off-by: Andrew Fernandes <andrew@fernandes.org>
The init routines are the same for SAMD20, SAMD21 and SAMR21, so
move them into common/ to not have three copies of the same code.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
The Atmel SAMD21 (and therefore also the SAMR21) comes with the same
RTC peripheral as the Atmel SAMD20.
Enable it in dts_fixup.h and enable it in the dts for samr21_xpro.
Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
Adds Atmel SAMR21 soc which is based on SAMD21, but with a AT86RF233
radio connected internally via SPI.
The AT86RF233 is not yet supprted by Zephyr at this point.
This code is very much copy & paste from atmel_sam0/samd21
Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
This commit renames the symbol CPU_HAS_SYSTICK to
CPU_CORTEX_M_HAS_SYSTICK, to look similar to all
other CPU_CORTEX_M_HAS_ options, and moves the
K-config symbol definition from arm/core/Kconfig to
arm/core/cortex_m/Kconfig.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
ARM SysTick timer is implemented by default in ARMv7-M
and Mainline ARMv8-M processors, so we include the
corresponding Kconfig symbol in arch/arm/core/cortex-M/Kconfig
and remove the selections from the Cortex-M SOCs.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
CPU_CORTEX_M does not need to be selected by Kconfig
symbols that already select a CORTEX_M variant.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add USART1 and LPUART1 nodes on stm32wb series.
Only these 2 ones are available for now on this series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add GPIO support to stm32wb series.
Only ABCDE and H ports are available for now on this series.
Accordingly, update series dtsi file.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add support to stm32wb series in stm32 clock_control driver.
Ip is similar to stm32l4 one but AHB bus presacler is renamed
to "CPU1" and CPU2 and AHB4 prescalers should be defined.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add the initial SoC support for the STM32MP1 family. The code was
tested on STM32MP157c, but should work on any STM32MP1XX currently
available.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Force soc.h to include the headers generated automatically
by DTS. In addition, force arm_mpu_regions.c to include
misc/slist.h for ARRAY_SIZE() macro. arm_mpu_regions.c
does not need to include soc.h (it is included indirectly
via arm_mpu.h)
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Same deal as in commit 4638652214 ("Kconfig: Use 'default' instead of
'def_bool' in Kconfig.defconfig files"), fixing new stuff that got
introduced since then.
Some symbols, like ALTERA_AVALON_PIO, are only defined in
Kconfig.defconfig files, and so need the def_bool.
Motivation (from the note at the end of
guides/kconfig/index.html#common-shorthands):
For a symbol defined in multiple locations (e.g., in a Kconfig.defconfig
file in Zephyr), it is best to only give the symbol type for the "base"
definition of the symbol, and to use 'default' (instead of 'def_<type>'
value) for the remaining definitions. That way, if the base definition
of the symbol is removed, the symbol ends up without a type, which
generates a warning that points to the other definitions. That makes the
extra definitions easier to discover and remove.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This commit adds CAN support for nucleo F746zg.
Furtermore CAN was added in stm32f7.dtsi and pinmuc_stm32f7.h
CAN_RX: PD0, CAN_TX: PD1
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
Missing quotes are accepted in some places for compatibility with the C
tools, e.g.
source no/quotes/Kconfig
menu Title
It looks broken though. Fix the two places in Zephyr that skip the
quotes. A style warning will be added.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Allows to enable initial RTS/CTS hardware flow control
in the dts.
Co-authored-by: Benoit Leforestier <benoit.leforestier@gmail.com>
Signed-off-by: Georgij Cernysiov <g.cernysiov@elco-automation.de>
The SYSCFG_CFGR1_PA11_PA12_RMP define is present even on packages where
the remap isn't strictly required. This commit makes the remap optional
based on a DT property.
Also fixes syntax error caused by a missing );.
Signed-off-by: Josef Gajdusek <atx@atx.name>
Update the files which contain no license information with the
'Apache-2.0' SPDX license identifier. Many source files in the tree are
missing licensing information, which makes it harder for compliance
tools to determine the correct license.
By default all files without license information are under the default
license of Zephyr, which is Apache version 2.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This reverts commit d4b4b99272 as it
introduced unwanted side effect: It moved the k_busy_wait() to other
clock that the one driving system timer and k_cycle_get_32(). As result,
delays created using these interfaces not matched each other.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
Not all i.mx rt socs have the same number of irqs, so move the default
configuration from the soc series level to the individual socs. The
rt1020 hardware reference manual (IMXRT1020RM Rev.1 12/2018) incorrectly
documents 160 irqs (#142-159 reserved), but the soc actually has 142
irqs.
Fixes tests/kernel/gen_isr_table for the mimxrt1020_evk board.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add SYS_POWER_ prefix to HAS_STATE_SLEEP_, HAS_STATE_DEEP_SLEEP_
options to align them with names of power states they control.
Following is a detailed list of string replacements used:
s/HAS_STATE_SLEEP_(\d)/HAS_SYS_POWER_STATE_SLEEP_$1/
s/HAS_STATE_DEEP_SLEEP_(\d)/HAS_SYS_POWER_STATE_DEEP_SLEEP_$1/
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This commit cleans up names of system power management functions by
assuring that:
- all functions start with 'sys_pm_' prefix
- API functions which should not be exposed to the user start with '_'
- name of the function hints at its purpose
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
There exists SoCs, e.g. STM32L4, where one of the low power modes
reduces CPU frequency and supply voltage but does not stop the CPU. Such
power modes are currently not supported by Zephyr.
To facilitate adding support for such class of power modes in the future
and to ensure the naming convention makes it clear that the currently
supported power modes stop the CPU this commit renames Low Power States
to Slep States and updates the documentation.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Plain 'source' is globbing. 'gsource' is a leftover from an older
design, and works as a synonym for 'source'.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
On STM32F3 devices, a trick was required for normal use of registers.
This was actually an issue in flash registers defintions which should
be defined as volatile.
Fix this and additionaly, fix definition for STM32F1 which was also
lacking the volatile instruction.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The iMX RT1060 and RT1064 have additional dedicated 512KB on-chip ram.
This OCRAM2 is mapped at 0x20200000, formerly OCRAM1 (flexram) mapping
which is moved to 0x20280000 in order to guarentee global OCRAM memory
continuity regardless OCRAM1 size configuration (256KB by default).
In default configuration, this gives 768KB (512+256) on-chip ram:
0x20200000 to 0x202BFFFF.
OCRAM2: 0x20200000 - 0x2027FFFF
OCRAM1(FlexRam): 0x2028FFFF - 0x202BFFFF
Add this memory region as a single node in the rt1060 device tree.
Note: MPU expects power of two memory region, in case of 768KB, let
the MPU configure 1MB instead.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
On stm32f4 series, uart4 is not an usart, so generated with
'st,stm32-usart' compatible and hence generated defined should be
prefixed with DT_ST_STM32_UART_ rather than DT_ST_STM32_USART.
Fixes#14542
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The clang ARM assembler is a bit stricter than GNU as, make a few
changes so things build with both
Signed-off-by: Peter Smith <peter.smith@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Maybe this is some "just in case" thing that got copied around. There's
no need to have a blank line at the beginning or end of Kconfig files.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Redefining the config will not let another (out-of-source) driver be
chosen instead of the default. The driver is practically forced by the
soc settings. This commit moves default settings from soc/arm/nordic_nrf
into the drivers themselves.
Signed-off-by: Thomas Stenersen <thomas.stenersen@nordicsemi.no>
Update reserved function names starting with one underscore, replacing
them as follows:
'_k_' with 'z_'
'_K_' with 'Z_'
'_handler_' with 'z_handl_'
'_Cstart' with 'z_cstart'
'_Swap' with 'z_swap'
This renaming is done on both global and those static function names
in kernel/include and include/. Other static function names in kernel/
are renamed by removing the leading underscore. Other function names
not starting with any prefix listed above are renamed starting with
a 'z_' or 'Z_' prefix.
Function names starting with two or three leading underscores are not
automatcally renamed since these names will collide with the variants
with two or three leading underscores.
Various generator scripts have also been updated as well as perf,
linker and usb files. These are
drivers/serial/uart_handlers.c
include/linker/kobject-text.ld
kernel/include/syscall_handler.h
scripts/gen_kobject_list.py
scripts/gen_syscall_header.py
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
The Kconfig.defconfig.efr32* files added redundant dependencies on
SOC_EFM32* that are already added in the Kconfig.defconfig.series files
that source them.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Adds a new config HAS_MCUX_FTFX to conditionalize the mcux flash driver
on socs that support it. Selects HAS_MCUX_FTFX on all kinetis socs
except kw40z, because even though this soc has the relevant hardware,
its CMSIS header file is not compatible with the mcux flash driver in
ext/.
This change also prevents enabling the mcux flash driver on lpc and imx
rt boards.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
There are some implicit rules in STM32 family Kconfig.defconfig
fragments organizations.
Add comments to explicit these rules.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
GPIO port H is available on all SoCs of L4 series.
Move Kconfig GPIO_STM32_PORTH symbol deifnition to series Kconfig
fragment Kconfig.defconfig.series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This value always comes from DTS. No Kconfig symbol named
NS16550_REG_SHIFT ever existed.
Might've been missed in commit 603f068690 ("uart/ns16550: Use DT_ prefix
for remaining device configs").
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
nRF52810 Flash and SRAM sizes do not have power-of-two values.
This commit reduces the amount of MPU regions reserved at boot
time to enforce basic permissions in Flash and SRAM memory. It
does this by selecting the next power-of-two size for the Flash
and SRAM regions, respectively. In this way we can cover the
entire Flash and SRAM space each with a single MPU region, thus,
save two MPU regions to be used by the kernel/application.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Some more were added since the cleanup pass in June 2018. See e.g.
commit 2d50da70a1 ("drivers: ipm: Kconfig: Remove redundant 'default n'
properties") for a motivation. It also avoids people wondering whether
or not they need to put in 'default n'.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Previous rename from CONFIG_* to DT_* left a few remaining
CONFIG_*. So rename them manually now.
Fix#13753
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
In the recent MDK brought by nrfx 1.6.2, these legacy peripherals have
been revealed as available also in nRF52810. This patch allows their
use in Zephyr drivers.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The i.MX RT1064 evk has one ethernet (10/100M) connector via KSZ8081RNB
phy. Enable related dts nodes and config flags
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
iMXRT1064 has 4MB on-chip Flash memory (flexspi2) mapped to 0x70000000.
Add it as configurable code location for MIMXRT1064-EVK board.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
CPU_LPS_n name used to indicate a low power state is cryptic and
incorrect. The low power states act on the whole SoC and not exclusively
on the CPU. This patch renames CPU_LPS_n states to LOW_POWER_n. Also
HAS_ pattern for Kconfig options is used in favor of a non standard
_SUPPORTED. Naming of deep sleep states was adjusted accordingly.
Following is a detailed list of string replacements used:
s/SYS_POWER_STATE_CPU_LPS_(\d)_SUPPORTED/HAS_STATE_LOW_POWER_$1/
s/SYS_POWER_STATE_CPU_LPS_(\d)/SYS_POWER_STATE_LOW_POWER_$1/
s/SYS_POWER_STATE_DEEP_SLEEP_(\d)_SUPPORTED/HAS_STATE_DEEP_SLEEP_$1/
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This commit removes dependency on SYS_POWER_LOW_POWER_STATES_SUPPORTED,
SYS_POWER_DEEP_SLEEP_STATES_SUPPORTED Kconfig options. Power management
SYS_POWER_LOW_POWER_STATES, SYS_POWER_DEEP_SLEEP_STATES options depend
now directly on specific power states supported by the given SoC. This
simplifies maintenance of SoC Kconfig files.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Follow the pattern we have for other peripherals in that if the driver
class (CAN) is enabled than enable the driver for that class
(CAN_STM32). Also have the STM32 CAN driver depend on being on a STM32
SoC.
Remove setting of CONFIG_CAN_STM32 in any .conf files as it will get set
of CONFIG_CAN is set/enabled.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds sys_set_power_state() function with support for EM1
Sleep, EM2 Deep Sleep, EM3 Stop power modes on Silabs SoCs.
Tested on efr32_slwstk6061a board.
Note: No support for efm32hg, efm32wg series at this point due to the
missing possibility of placing function code in RAM, required by errata
in SiLabs library code.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
'soc' logger module may be used by any SoC related code located in soc/.
An implementation file requiring logger services should include
LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
to use the 'soc' logger instance.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
We should be selecting CPU_HAS_ARM_MPU at this level and not
CPU_HAS_MPU. Change the cases of CPU_HAS_MPU to CPU_HAS_ARM_MPU.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit removes "select SYS_POWER_*_SUPPORTED" entries from
Kconfig on SoCs which are not implementing sys_set_power_state()
method used to control power mode.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
Some of power states used numerical suffix while otthers not.
This commit adds proper suffix to all power state names.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
f
This commit simplifies OS <-> Application interface controlling power
management. In the previous approach application-based PM required
overriding sys_suspend() and sys_resume() functions. As these functions
actually implemented power state change, in such case application
basically had to provide own implementation of all PM-related stuff,
which was not portable and hard to maintain.
This commit changes this scheme: The sys_suspend() and sys_resume()
are now system functions while the application could either use
built-in power management policies or provide its own. All details
of power mode switching are now handled by the OS.
Also, this commit cleans up the Kconfig options related to system-level
power management grouping them under common CONFIG_SYS_PM_ prefix.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
A common driver is shared between stm32 chips, which was not the case
for stm32f3 series. As a consequence stm32f3 was not maintained
equally and was missing features such as flash layout or dts based
configuration.
Besides, drivers had some flows such as wrong bus clock and
missing HSI clock activation which lead to issues on boards not
using HSI as main clock.
As a consequence this commit moves stm32f3 series flash driver to
common stm32 flash drivers.
Fixes#4197
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Refactor the imx rt code/data location config defaults such that we
default to on-chip memories at the soc level and override to external
memories at the board level. This means that we frequently override soc
defaults for evk boards, but it removes the assumption that all imx rt
boards (particularly non-evk boards) will have the same external
memories as evk boards.
The end result is that imx rt evk boards still have the same defaults as
before, but the way we get there is different.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The imx rt dts fixup was missing gpio 2,3,4 instances. This caused a
build error in the gpio driver when an application enabled:
CONFIG_GPIO_MCUX_IGPIO_2=y
CONFIG_GPIO_MCUX_IGPIO_3=y
CONFIG_GPIO_MCUX_IGPIO_4=y
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The imx rt family of socs has several options for linking code and data
into internal or external memories, and up until now we have handled
these options at the board level. This has resulted in several Kconfig
symbols being defined in multiple places and triggering warnings in
documentation builds:
warning: the default selection CODE_ITCM (defined at boards/arm/mimxrt1050_evk/Kconfig:13, boards/arm/mimxrt1060_evk/Kconfig:13) of <choice> (defined at boards/arm/mimxrt1050_evk/Kconfig:9) is not contained in the choice
warning: the choice symbol CODE_ITCM (defined at boards/arm/mimxrt1050_evk/Kconfig:13, boards/arm/mimxrt1060_evk/Kconfig:13) is defined with a prompt outside the choice
warning: the choice symbol CODE_HYPERFLASH (defined at boards/arm/mimxrt1050_evk/Kconfig:16, boards/arm/mimxrt1060_evk/Kconfig:16) is defined with a prompt outside the choice
warning: the choice symbol CODE_QSPI (defined at boards/arm/mimxrt1050_evk/Kconfig:19, boards/arm/mimxrt1060_evk/Kconfig:19) is defined with a prompt outside the choice
warning: the choice symbol CODE_ITCM (defined at boards/arm/mimxrt1050_evk/Kconfig:13, boards/arm/mimxrt1060_evk/Kconfig:13) is defined with a prompt outside the choice
warning: the choice symbol CODE_HYPERFLASH (defined at boards/arm/mimxrt1050_evk/Kconfig:16, boards/arm/mimxrt1060_evk/Kconfig:16) is defined with a prompt outside the choice
warning: the choice symbol CODE_QSPI (defined at boards/arm/mimxrt1050_evk/Kconfig:19, boards/arm/mimxrt1060_evk/Kconfig:19) is defined with a prompt outside the choice
The number of warnings increased as we added more imx rt boards. Fix the
warnings by moving code and data location configs from the board level
to the soc level.
The default memories for all imx rt boards are unchanged. The
mimxrt10{20,50,60}_evk boards still default to hyperflash/qspi for code
and sdram for data. The mimxrt1064_evk board still defaults to ITCM for
code and DTCM for data because jlink does not yet support programming
internal flash.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
soc.h references Kconfig symbols which aren't defined. Define the
specific SoC versions that are referenced in soc.h
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In soc.h reference to CONFIG_SOC_PART_NUMBER_SAM4S18B should have been
CONFIG_SOC_PART_NUMBER_SAM4S8.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit changes the names of SYS_POWER_DEEP_SLEEP* Kconfig
options in order to match SYS_POWER_LOW_POWER_STATE* naming
scheme.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The SYS_POWER_LOW_POWER_STATE_SUPPORTED and SYS_POWER_LOW_POWER_STATE
suggests one low power state but these options control multiple
low power state. This commit uses plural in the names to indicate
that.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
Initial support for Microchip MEC1701 series is incorporated to the
tree. Additional support for UART is also included. This SOC supports
two operation modes for interrupts (Direct and Aggregated). For this
commit, the interrupts are configured in direct mode.
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
The eth mcux driver has been using non DT_ prefixed defines for DT
generated defines. Switch to use DT_ prefixed ones as we want to
deprecated the non DT_ prefixed defines.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The soc nxp_imx RDC code has been using non DT_ prefixed defines for DT
generated defines. Switch to use DT_ prefixed ones as we want to
deprecated the non DT_ prefixed defines.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Select CPU_HAS_FPU_DOUBLE_PRECISION in SAM E70 and NXP I.MX RT
series of MCUs to signify double-precision floating-point unit.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
SoC family STM32F769XI supports both double and single precision
floating-point unit. This commit enables double-precision by
default in this SoC.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit introduces a Kconfig option for ARM SoCs, to signify
that the SoC implements a double-precision floating point unit.
The option is utilized in cmake/fpu-for-gcc-m-cpu to select the
appropriate GCC compile option flag for FPU.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This patch adds basic support for the PWM devices available on the Atmel
SAM family. Beside enabling the driver, everything is selected through
the device tree, including enabling the PWM0 and PWM1 devices. Thus
CONFIG_PWM_0 and CONFIG_PWM_1 are ignored.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Provides a STM32 RTC driver using new counter API.
Driver does not support wrap related functions (set, get, ..)
Fixes#11373
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The CMSDK Timer can be used as a timer or as a counter.
The unified interface proposed in #8340 unifies counter.h and rtc.h to
provide a common interface.
This patch modifies the timer implementation of the single timer to
make it compliant with the new proposed interface.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add EPIT (Enhanced Periodic Interrupt Timer) peripheral support
for i.MX6SoloX soc.
Origin: Original
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Removing duplicates in selects for config SOC_NRF52832 and
SOC_NRF52840. Duplicates were unexpected merge artifacts.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Enables the mcux elcdif shim driver and clocks on imx rt socs when the
display driver interface is enabled.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
In case of !XIP, set defaults for CONFIG_FLASH_SIZE and
CONFIG_FLASH_BASE_ADDRESS in Kconfig.
Fixes: #13113
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Now that the SAM Ethernet driver can work when the cached is enabled, it
is possible to unconditionally enable the data cache on the SAM E70 SoC.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Each platform is now specifying list of supported power states
as a Kconfig options. Some of the specified states could be
disabled in runtime. As result there is no need for the removed
interface.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
Currently each SoC has to define own list of power states.
However all these definitions have to be the same, as common power
management code uses them.
This commit replaces per-soc power state list by global definition.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
Use the new DT_<COMPAT>_<INSTANCE>_<PROP> defines to instantiate
devices. This commit adds also ability to define individual pin
locations on SoC series that support the feature. Definitions of GPIO
pins assigned to a given location have been moved from soc_pinmap.h file
to board DTS file.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Use the new DT_<COMPAT>_<INSTANCE>_<PROP> defines to instantiate
devices. This commit adds also ability to define individual pin
locations on SoC series that support the feature. Definitions of GPIO
pins assigned to a given location have been moved from soc_pinmap.h file
to board DTS file.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This commit ports power management code from nRF52 to the nRF51 SoC,
enabling usage of Zephyr Power Management policies on this platform.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
This commit updates the power management code for nRF52 SoC
series after recent changes in Zephyr power management subsystem.
Changes:
- Removed LPS modes, as they are not supported by HW.
(previous implemntation used CONSTLAT and LOWPWR settings
in NRF_POWER to implement low power modes, however these
knobs should be used only when application needs ultra low
CPU wake-up time).
- Reworked code in order to allow adding custom power levels
on the application level and provide better integration
with power management subsystem.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
exti driver implementation does not fit all SoCs because
some EXTI ip does not match stm32_exti register map provided.
Instead of providing exti register map for all SoCs, use LL API
which abstracts IP variations and enable uniform use of the drivers
on all STM32SoCs.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Use the new DT_<COMPAT>_<INSTANCE>_<PROP> defines to instantiate
devices. This commit adds also ability to define individual pin
locations on SoC series that support the feature. Definitions of GPIO
pins assigned to a given location have been moved from soc_pinmap.h file
to board DTS file.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Now that a hw-flow-control DTS binding has been added for MCUX uart,
let's check for the DT_ define and enable support in the MCUX HAL
layer.
Signed-off-by: Michael Scott <mike@foundries.io>
Add sam0_rtc_driver that implements system timer API on top of the RTC
and can be used as a replacement for the default systick timer.
Signed-off-by: Martin Benda <martin.benda@omsquare.com>
Adds a new config HAS_MCUX_ENET to constrain which socs can enable the
mcux ethernet driver. This will prevent users from enabling the driver
on socs like kl25z or kw41z which do not have ethernet mac hardware.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
In soc.h of nRF9160 SoC we need to explicitly include
nrfx_config_nrf9160.h to have the standard peripheral
base address macro mappings in Zephyr builds for nRF9160
SoC. (We need to do this spefically for nRF9160, as those
macros are not present in the nRF9160 MDK header).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Adds STM32 L452 soc with L452xC variant. L452 has 160 KB SRAM;
therefore, mpu mem config has been extended; IRQ number is based on
'stm32l452xx.h'.
Signed-off-by: Georgij Cernysiov <g.cernysiov@elco-automation.de>
Enables the mcux ethernet driver and pin muxes on the mimxrt1020_evk
board, the same way it is done on the mimxrt1050_evk board. Updates the
board documentation and yaml supported list accordingly.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The ENET PLL should be enabled if the SoC is the MIMXRT1021 (it used by
the ARM core) or if the ENET device is enabled.
The 500MHz clock should be enabled if the SoC is the MIMXRT1021.
The ENET clock should be enabled if the ENET device is enabled.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Kconfig currently emits a warning when building for a MIMXRT1021 SoC:
warning: INIT_ENET_PLL (defined at
soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1052:66) has direct
dependencies NET_L2_ETHERNET && SOC_MIMXRT1052 && SOC_SERIES_IMX_RT
with value n, but is currently being y-selected by the following
symbols:
- SOC_MIMXRT1021 (defined at soc/arm/nxp_imx/rt/Kconfig.soc:12),
with value y, direct dependencies <choice> (value: y), and select
condition <choice> (value: y)
This is due to the fact the ENET PLL is the one used by the ARM core on
the MIMXRT1021 so it is always enabled, while it is declared protected
by NET_L2_ETHERNET and SOC_SERIES_IMX_RT.
Fix that by declaring the symbol in Kconfig.defconfig.series.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Remove redundant inclusion of nrf.h (included by nrfx.h).
Group the logging/log.h inclusion together with the other
inclusions in this file (make inclusions' list look as in
nrf9160/soc.c).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Remove the locally-defined macros which define the base
addresses for XICR, Peripheral space and PPB. The macros
are not used.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Enables the mcux lpi2c shim driver and clocks on all imx rt socs when
the i2c driver interface is enabled.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds dts fixups for lpuart instance 2, which will be used for the
arduino_serial connection on the mimxrt1020_evk board.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Clean up a left over from GPIO driver factorization.
Definition of GPIO_REG_SIZE and GPIO_PORTS_BASE do not need anymore
to be spread accross SoCs.
Put these definitions directly in STM32 pinmux driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit introduces a new Kconfig symbol to signify
that a CPU implements the Nordic-specific security
attribution unit. The symbol is meant to be selected
by Nordic SoCs that implement the System Protection
Unit (SPU) peripheral.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds the nRF9160 fixup and the source files
for SOC and MPU boot configuration.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit introduces the Kconfig file structure for nrf9160
SoC in the Zephyr tree.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Support musca board as a variant, it is a Cortex-M33 based SoC.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
Signed-off-by: Minos Galanakis <minos.galanakis@arm.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
SAMD2x series have available the Optional Vector Table Offset Register
(VTOR). If this option is not selected, SCB->VTOR is not configured
properly and the application hangs if it's located in an offset
different than 0.
Removed select CPU_CORTEX_M from SAMD20, as it's already selected by
select CPU_CORTEX_M0PLUS
Signed-off-by: Miguel A. Borrego <jimjim17@gmail.com>
This commit renames the CLOCK_CONTROL_NRF5 Kconfig symbol to
CLOCK_CONTROL_NRF. The change is required to aleviates confusion
when selecting the symbol in nRF9160 SOC definition.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
In the wake of 9cbe468a470fe6a103557d4352d37604a632b2fe we need
to update the nomenclature of DT_FLASH_DEV_NAME macros.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The CIAA and QFAB variants of the nRF52832 were missing in Kconfig,
although present in Device Tree. Add the relevant Kconfig entries in
order to be able to select them.
Fixes#12417
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Add support for the TRNG device contained in the i.MX RT SoCs. It uses
the existing MCUX driver, and mostly consists in adding the Kconfig and
DTS entries.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The original implementation of gpio functions access registers
directly. Using LL library can add a set of unifying access
functions for all series of stm32 for avoiding accessing low level
code, and improve readability.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
All series STM32 have mostly the same GPIO architecture
and can share the same code for GPIO manipulation.
Functions of the external interrupt line control are also the same.
This patch extracts common code from them and put them into the 'common'
folder.
Functions of control GPIO of these series scattered in
soc/arm/st_stm32/stm32xx/ folders contain these functions:
stm32_gpio_flags_to_conf(), stm32_gpio_configure(), stm32_gpio_set(),
stm32_gpio_get, stm32_gpio_enable_int().
This patch merges them into the gpio_stm32.c file.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
Adds support for the device configuration data (DCD), which provides a
sequence of commands to the imx rt boot ROM to initialize components
such as an SDRAM.
It is now possible to use the external SDRAM instead of the internal
DTCM on the mimxrt1020_evk, mimxrt1050_evk, and mimxrt1060_evk. Note,
however, that the default board configurations still link data into
internal DTCM, therefore you must use a device tree overlay to override
"zephyr,sram = &sdram0"
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Moves the default TEXT_SECTION_OFFSET from the board level to the soc
level for the imx rt series. This offset is used to reserve space for
the imx boot header for external xip flash images.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds support for the boot data, image vector table, and FlexSPI NOR
config structures used by the imx rt boot ROM to boot an application
from an external xip flash device.
It is now possible to build and flash a bootable zephyr image to the
external xip flash on the mimxrt1020_evk, mimxrt1050_evk, and
mimxrt1060_evk boards via the 'ninja flash' build target and jlink
runner. Note, however, that the default board configurations still link
code into internal ITCM, therefore you must set CONFIG_CODE_HYPERFLASH=y
or CONFIG_CODE_QSPI=y explicitly to override the default. You must also
set CONFIG_NXP_IMX_RT_BOOT_HEADER=y to build the boot header into the
image.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit configures ETM/TPIU clock upon startup in case SWO logger
backend is enabled on Atmel SAM E70 SoC.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
By default, after reset SWO signal is not connected to GPIO pin.
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
By default, after reset SWO signal is not connected to GPIO pin. This
commit adds required initialization code to enable support for SWO
logger. Not all SoC series support the feature.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This commit adds Serial Wire Output (SWO) logger backend. SWO is an
extension of Serial Wire Debug (SWD) port developed by ARM.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
On STM32L4, 14 pins (Port G[15:2]), require external power supply.
Activate this at port G init when PWR_CR2_IOSV is defined.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Zephyr gecko drivers depend on libraries provided by the vendor. The
same libraries may also be used directly by the application code or
RAIL library. To facilitate the latter use case scenario this commit
adds Kconfig options to independently enable compilation of vendor
HAL library modules.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
* Add DTS support for gpio controller driver
Signed-off-by: Ashokkumar B <ashokkumar@zilogic.com>
Signed-off-by: Subash G <subash@zilogic.com>
Signed-off-by: Vishnu K <vishnu@zilogic.com>
Signed-off-by: Vaishnavi D <vaishnavi.d@zilogic.com>
By adding 'aliases' node in SoC .dtsi file it is possible to generate
DT_ defines which specify a logical name rather than relay on module
location on APB bus. E.g. DT_SILABS_GECKO_USART_40010000_LABEL becomes
DT_SILABS_GECKO_USART_USART_0_LABEL. Thus it is possible to remove
dts_fixup.h defines.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Fixes an ethernet build error introduced with MCUXpresso SDK 2.5.0,
caused by a slight change in the ethernet pll configuration structure.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add uart5 nodes to stm32f1 series dts.
Provide matching dts_fixup add-on.
Signed-off-by: Chen Han <qq1433255094@outlook.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Updates the MCUXpresso SDK to version 2.5.0 for applicable SoCs.
Wireless (KW*) and legacy (KL25) SoCs were not included in this
MCUXpresso SDK release and are therefore not updated here.
New in this release is SoC-level and board-level support for external
xip flash in the i.MX RT family.
For RT1050, we are now using the MCUXpresso SDK for the EVKB version of
the board, which correponds to an upgrade from A0 to A1 silicon.
However, we don't yet have Kconfigs in place to support A1 silicon part
numbers, and therefore add a simple cmake hack to convert A0 part
numbers to A1 part numbers.
The SDK flash driver interface also changed slightly in this release,
and thus the zephyr flash shim driver is updated accordingly.
Origin: MCUXpresso SDK
License: BSD 3-Clause
URL: mcux.nxp.com
Purpose: Provide device header files and bare metal peripheral drivers
for Kinetis, LPC, and i.MX SoCs.
Maintained-by: External
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add support for Low Speed External 32.768 kHz oscillator (LSE ).
Add support for MSI PLL-Mode offering an automatic calibration feature
in combination with the LSE. This allows the MSI to reach an accurate
+/-0,25% clock perfectly suitable for USB full-speed clock.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
SPI devices almost always require chip selects, which are configured
through GPIOs. Make the GPIO infrastructure available by default when
SPI is enabled.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
In the wake of introducing nRF9160 .dtsi header, we are
adding several HAS_HW_NRF_xxxx Kconfig symbols, for the
peripherals present in nrf9160 SoC.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Make the following nRF peripheral drivers:
- ADC
- GPIO
- I2C
- SPI
- UART
- USB_DEVICE
enabled by default so that users do not need to explicitly enable them
in their applications after choosing an nRF SoC as the build target.
Kconfig options enabling these drivers depend on both a given hardware
feature (e.g. I2C) and an nRF family SoC selected, so effectively they
will be automatically enabled only when it is adequate (and in most
cases these drivers are the only option for a given hardware feature
on nRF SoCs).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Implementations of both flavors of serial drivers for Nordic SoCs
are no longer dependent on the gpio driver. Remove the dependency
from Kconfig.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Added board definitions for nucleo_f756zg. Features include gpio,
pinmux, uart (ST Zio, ST-Link and Arduino Uno v3 interfaces).
Added basic documentation and some soc definitions for the
stm32 f756XX soc.
Signed-off-by: AJ Palmer <ajpcode@hotmail.com>
The early boot watchdog init for kinetis was incorrectly disabling and
reenabling interrupts to preserve timing during the unlock sequence.
However, interrupts are already disabled before this routine executes
and the kernel is not yet ready to enable them when this routine exits.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This patch adds a flash driver for the STM32F7x series, inspired from
the STM32F4x one. It has been tested on the STM32F723, but should also
work on other SoCs of the family.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This patch cleans up the code in the recently added dts_fixup.h,
restoring the original alignment of the file.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
The dts.fixup for v2m_beetle contains a wrong setting for the IRQ fixup
for the Dual Timer IRQ.
This patch fixes the symbol included in the generated header.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This commit simplifies Kconfig options related to handling SoC series,
part numbers. This is a first step required to add remaining part
numbers to the existing configuration.
This change is possible since all SiLabs SoCs within a single series
have a very uniform structure.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
