Commit graph

2589 commits

Author SHA1 Message Date
Mulin Chao
66dc1482e7 driver: scfg: npcx: replace scfg offset macros with inline functions.
This CL replaces offset macros of scfg 'multi-registers' such as DEVALTn
and LV_GPIO_CTLn with internal inline functions for better readability.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2021-07-26 19:26:52 -04:00
Scott Worley
6b3749d2ff Microchip: MEC172x Add aggregated interrupt driver
Add driver implementation and header files for a MEC172x
aggregated interrupt driver. Enable the parent(ECIA) node
to have the driver initialize interrupt hardware for use.
Enable child nodes for those GIRQs used for aggregation.
Refer to chip documention for the list of GIRQs restricted
to aggregation and those which support direct mode.
Add chip level device tree node for MEC172x EC interrupt
aggregator parent and GIRQ children. Each child node contains
a list of sources representing the source bit position in the
GIRQ registers.
Add DT bindings for ECIA and GIRQ nodes.
Add build file(s) and configuration items for the MEC172x ECIA
aggregated interrupt driver. Add and enable the MEC172x interrupt
driver on the MEC172x evaluation board(EVB). Enable parent node to
initialize ECIA hardware. Child nodes are left disabled until a
future driver needs them.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2021-07-26 12:24:52 -04:00
Flavio Ceolin
d45a0e1919 pm: Fix weak linkage symbols
Define SoC hooks as weak symbols so this way applications can
overwritten them defining strong symbols.

The problem is that currently SoCs are defining these interfaces as
strong symbol inhibiting the possibility of applications bring their
own implementation.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2021-07-26 04:31:54 -04:00
Yuval Peress
eadca02251 espi: npcx: Add missing includes to header
Add the missing includes to make the header more portable. It currently
requires other headers to be included before it.

Signed-off-by: Yuval Peress <peress@chromium.org>
2021-07-23 16:26:44 -04:00
Scott Worley
d3f6b54f8e Microchip: MEC172x clock control driver
Implement a clock control driver for Microchip MEC172x handling
configuring the 32 KHz input sources for the PLL and peripheral-32k
clock domains. MEC172x differs from MEC152x. MEC152x had one 32K source
for both PLL and peripherals. MEC172x allows the two domains to use
independent 32 KHz sources. Device tree updated to provide addresses
of hardware used by the driver.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2021-07-21 17:46:07 -04:00
David Leach
590a53f662 dts: rt600: Add TRNG support
Add RT6xx TRNG support to enable the entropy driver.

Signed-off-by: David Leach <david.leach@nxp.com>
2021-07-21 17:32:09 -04:00
Flavio Ceolin
65e4add74e soc: cc13x2: Use residency policy
cc13x2_cc26x2 had its own power policy that was implementing the same
logic available in the default residency policy. Also, this policy was
unnecessarily setting up a timeout to wakeup the system. This is not
necessary, the power subsystem takes care of this.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2021-07-21 17:54:40 +03:00
Alexandre Bourdiol
17d978803b soc: arm: stm32wb power: implement HSEM for power management
Implementation of hardware semaphore algorithm of STM32 AN5289
to enter and exit low power

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2021-07-21 05:37:48 -04:00
Scott Worley
7872cdec76 Microchip: MEC172x add header set 8
Add MEC172x chip specific headers for Port 80h debug
capture, quad SPI, and VBAT registers. Update due to
merges.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2021-07-20 20:05:12 -04:00
Scott Worley
f465cc2cba Microchip: MEC172x Add header set 7
Add MEC172x chip specific header set 7: GPIO and I2C.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2021-07-20 20:05:12 -04:00
Scott Worley
a9871a89b2 Microchip: MEC172x add header set 6
Add MEC172x chip specific headers (eSPI).
Update due to previous header PR merges.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2021-07-20 23:18:17 +03:00
Crist Xu
04ab2400e6 driver: adc: an adc driver for rt1170
reuse the lpc's lpadc driver for rt1170, modify the dts and add
some macro to shield some code of LPC series. Also add the
board support inside the tests/drivers/adc/adc_api/src/test_adc.c,
and a dts node:zephyr,user inside
samples/drivers/adc/boards/mimxrt1170_evk_cm7.overlay

Signed-off-by: Crist Xu <crist.xu@nxp.com>
2021-07-20 13:15:58 -05:00
Scott Worley
55f4c269c1 Microchip: MEC172x Add header set 5
Add Microchip MEC172x header set 5 chip specific
peripheral headers. Update with recent merged code.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2021-07-20 16:54:12 +03:00
Scott Worley
3f3bfe9859 Microchip: MEC172x Add header set 4
Add last common set of headers.
Update for previous merge.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2021-07-20 10:05:43 +03:00
Scott Worley
3c39dd0811 Microchip: MEC172x Add header set 3
Add third set of MEC172x common headers.
Update for merged board.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2021-07-20 10:05:27 +03:00
Scott Worley
71ba3136ea Microchip: MEC172x add header set 2
Add second group of common headers for MEC172x.
Update with merged MEC172x changes.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2021-07-20 10:05:10 +03:00
Scott Worley
d4e382ee05 Microchip: MEC172x Add first set of headers
Consensus was reached to locate Microchip MEC172x header files
in the zephyr MEC172x SoC folders. These are the first set of
headers specific to MEC172x and common to the MEC family. Hardware
register structures will be located in peripheral specific headers.
Update based on latest merge of MEC172x related files.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2021-07-20 10:04:53 +03:00
Even Falch-Larsen
b8820da4e6 soc: stm32: stm32l051
Adding support for the stm32l051 devices.

Signed-off-by: Even Falch-Larsen <even.falch.larsen@nomono.co>
Co-authored-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-07-19 15:04:08 -05:00
Scott Worley
5b5396f7b6 Microchip: MEC172x add board and update for minimal build
Added minimal device tree and board files to build Microchip
MEC172x. SOC layer stripped down to allow build for checking
compilation only.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2021-07-19 21:07:31 +03:00
Bernhard Krämer
e138b443b1 soc: arm: nxp_imx: rt: add new part number
MIMXRT1062DVJ6A

Signed-off-by: Bernhard Krämer <bdkrae@gmail.com>
2021-07-19 12:15:42 -05:00
Piotr Mienkowski
cdb6bfff1e soc: same70, samv71: free TRACESWO pin when unused
Pin PB5 is part of ARM Cortex-M debug interface and by default
configured to output TDO/TRACESWO signal. Disable TDO/TRACESWO
function on PB5 pin when LOG_BACKEND_SWO is not enabled. This
ultimately frees the pin to be used by standard SoC peripherals.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2021-07-17 08:09:08 -04:00
Wealian Liao
3964ae1895 soc: npcx: Improve npcx header Kconfig
This commit includes the following:
1. Add symbol for choice option. So we can override the default value
   by an earlier definition.
2. NPCX9 doesn't support 33MHz SPI clock in the header. So disable the
   option for NPCX9.
3. NPCX9 support 512K flash. Change default to 512k for NPCX9.

Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
2021-07-16 18:59:12 -04:00
Mahesh Mahadevan
db162bb05d counter: Add counter support for rt600
Add counter support using the RTC for RT600

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2021-07-16 18:56:15 -04:00
Carlo Caione
f4db14f349 dts: Introduce DT_STRING_TOKEN and DT_STRING_UPPER_TOKEN
To be able to get a tokenize DT string without the quotes. Deprecate
also DT_ENUM_TOKEN and DT_ENUM_UPPER_TOKEN.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-07-15 18:12:51 -05:00
Alexandre Bourdiol
cd881e0562 soc: arm: stm32l1: set voltage scaling to range1
Default Voltage scaling range selection (range2)
doesn't allow to configure Max frequency
switch to range1 to match any frequency

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2021-07-15 10:13:27 +03:00
Alexandre Bourdiol
3103fc8c38 soc: arm: stm32l0: set voltage scaling to range1
Default Voltage scaling range selection (range2)
doesn't allow to configure Max frequency
switch to range1 to match any frequency

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2021-07-15 10:13:27 +03:00
Henrik Brix Andersen
316cb25db4 soc: arm: nxp: kinetis: ke1xf: add support for power management
Add power management support (runtime-idle and suspend-to-idle)
support for the NXP Kinetis KE1xf SoC series.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-14 22:54:34 +03:00
Henrik Brix Andersen
7436432f2e soc: arm: nxp: kinetis: ke1xf: enable lptmr as timer
Enable the NXP Kinetis Low Power Timer (LPTMR) OS timer driver when
power management is enabled as the Arm SysTick timer cannot wake up the
KE1xF from deep sleep.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-14 22:54:34 +03:00
Henrik Brix Andersen
937c2c8dfd soc: arm: nxp: kinetis: ke1xf: keep the sirc running in low-power mode
Keep the Slow Internal Reference Clock (SIRC) running in low-power
mode.

This allows peripherals that needs to remain operative in low-power
mode to use the SIRC as clock source.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-14 22:54:34 +03:00
Henrik Brix Andersen
5fcb13aea3 soc: arm: nxp: kinetis: ke1xf: determine hw clock cycles/sec from dts
Determine the default CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC from devicetree
when using the Arm SysTick hardware timer.

When the NXP KE1xF SoC series is using the Arm SysTick as hardware
timer, the cycles/second will always be equal to the CPU core clock
frequency.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-14 22:54:34 +03:00
Maureen Helm
ae056a7300 soc: boards: Enable Segger RTT/SystemView on mimxrt1170_evk_cm7
Adds a devicetree chosen node to the mimxrt1170_evk_cm7 board to link
Segger RTT and SystemView sections in DTCM by default. Enables the AHB
clock while the CM7 is sleeping to allow debug access to the TCM.

Note that automatic RTT control block detection may not search the DTCM
address region, therefore you may need to manually set the RTT control
block address or search range in the Segger host tools (SystemView or
RTT Viewer). For example,

$ JLinkRTTViewer -ra 0x20000000

Tested with:
  - samples/subsys/shell/shell_module/
  - samples/subsys/tracing/

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2021-07-14 13:22:24 -04:00
Gerson Fernando Budke
0ff3616bdf drivers: usb: device: Rename usb_dc_sam to usb_dc_sam_usbhs
The SoC driver name is 'USB High-Speed Interface (USBHS)'. This rename
from usb_dc_sam to usb_dc_sam_usbhs allowing add others SoC drivers
like 'USB Device Port (UDP)' that is found at SAM4S/E variations.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2021-07-14 07:23:38 -04:00
Thomas Stranger
63478aba48 soc/arm: add support for stm32g0 socs with (hw aes and) rng support
This commit introduces g041, g061, g081, and g0c1 socs in kconfig.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
2021-07-13 09:37:48 -04:00
Thomas Stranger
e804f5a5c6 soc/arm: add support for additonal stm32wl socs
This commit adds support for stm32wle4xx, stm32wle5xx single core socs,
as well as stm32wl54 dual core soc.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
2021-07-13 09:37:29 -04:00
Maureen Helm
fbaaca188b soc: boards: Disable i.MX RT6xx boot header in chainloaded applications
The bootloader itself contains the i.MX RT6xx boot header, so we don't
need to duplicate it when building chainloaded applications.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2021-07-13 09:35:38 -04:00
Maureen Helm
0082a1a6e5 soc: boards: arm: Refactor i.MX RT600 zephyr,flash usage
Refactors the i.MX RT600 SoC series to be more consistent with the i.MX
RT10xx SoC series by choosing a child node (external flash device) of
the FlexSPI bus for zephyr,flash.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2021-07-13 09:35:38 -04:00
Crist Xu
5b44d5f721 driver: flexcan: flexcan support for the rt1170
add the flexcan3 support for the rt1170

Signed-off-by: Crist Xu <crist.xu@nxp.com>
2021-07-12 16:05:34 -05:00
Jun Lin
1974ea97a4 driver: clock: npcx: add a option to generate LFCLK via XTSOC
This commit adds a new Kconfig option CLOCK_CONTROL_NPCX_EXTERNAL_SRC.
With this option enabled, the internal 32.768 KHz clock (LFCLK) is
generated by the on-chip Crystal Oscillator (XTOSC). Otherwise, the
LFCLK is generated by the Low-Frequency Clock Generator (LFCG).

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2021-07-12 23:34:42 +03:00
Wealian Liao
bbd5b259e5 soc: npcx: Add soc log register
NPCX power.c use LOG_MODULE_DECLARE(soc), but NPCX chip doesn't
register soc log module. This CL register soc log in soc.c to fix NPCX
build error for power management & log system.

Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
2021-07-12 22:49:18 +03:00
Henrik Brix Andersen
493c909a33 soc: arm: nxp: kinetis: kwx: indicate presence of RCM
Indicate presenence of the Reset Control Module on the NXP KWx SoC
series.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-08 09:33:32 -05:00
Henrik Brix Andersen
d16d34b152 soc: arm: nxp: kinetis: kv5x: indicate presence of RCM
Indicate presenence of the Reset Control Module on the NXP KV5x SoC
series.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-08 09:33:32 -05:00
Henrik Brix Andersen
6b811443d4 soc: arm: nxp: kinetis: kl2x: indicate presence of RCM
Indicate presenence of the Reset Control Module on the NXP KL2x SoC
series.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-08 09:33:32 -05:00
Henrik Brix Andersen
01f62a08f3 soc: arm: nxp: kinetis: k8x: indicate presence of RCM
Indicate presenence of the Reset Control Module on the NXP K8x SoC
series.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-08 09:33:32 -05:00
Henrik Brix Andersen
f6a84125b6 soc: arm: nxp: kinetis: k2x: indicate presence of RCM
Indicate presenence of the Reset Control Module on the NXP K2x SoC
series.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-08 09:33:32 -05:00
Henrik Brix Andersen
3d20888359 soc: arm: nxp: kinetis: ke1xf: indicate presence of RCM
Indicate presenence of the Reset Control Module on the NXP KE1xF SoC
series.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-08 09:33:32 -05:00
Henrik Brix Andersen
e22ce47c4f soc: arm: nxp: kinetis: k6x: indicate presence of RCM
Indicate presenence of the Reset Control Module on the NXP K6x SoC
series.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-08 09:33:32 -05:00
Crist Xu
c21bfdca9c driver: gpt: the gpt driver for the rt1170
reuse the gpt driver for the rt10xx, and add the related code

Signed-off-by: Crist Xu <crist.xu@nxp.com>
2021-07-07 20:59:42 -04:00
Maureen Helm
b2b38903a7 soc: arm: nxp_imx: Link Segger RTT/SystemView sections in DTCM if chosen
Configures Segger RTT and SystemView data linker sections to DTCM by
default on i.MX RT SoCs if there is a zephyr,dtcm chosen node in
devicetree. This fixes a build warning in
samples/subsys/shell/shell_module for the mimxrt1170_evk_cm7 and
mimxrt1170_evk_cm4 platforms, which don't currently have a zephyr,dtcm
chosen node.

Note that there are runtime issues with Segger RTT and SystemView on
this board that need further debug, but submitting this patch now to
address nightly CI failures.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2021-07-07 14:30:14 -04:00
Pavlo Hamov
6a1416d0c2 soc: arm: cc32xx: Override Reboot implementation
Support cold, hot reboots. Cold will reboot all periherals

Signed-off-by: Pavlo Hamov <pasha.gamov@gmail.com>
2021-07-06 15:22:39 -05:00
Fabio Baltieri
2fc87f961b soc: stm32wl: add power management support
This adds power management support for the STM32WL series.

Suspend-to-idle is mapped to the three stop states (wake up from any
EXTI, including LPTIM), and soft-off can trigger either standby or
shutdown (wake up in reset).

Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
2021-07-06 09:51:22 -04:00