Commit graph

2589 commits

Author SHA1 Message Date
Liam Clark
6b8b9e058b soc: arm: st_stm32: add support for STM32L431XC
Add support for the STM32L431XC SoC.

Signed-off-by: Liam Clark <liam.james.clark@gmail.com>
2022-10-06 22:37:40 +00:00
Gerard Marull-Paretas
40a6f08d3c soc: arm: nxp_lpc: do not select PINMUX
The platform has support for pinctrl, but it is selecting both pinmux
and pinctrl. Legacy applications requiring pinmux should enable it
manually.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-10-06 05:24:15 -05:00
TOKITA Hiroshi
db6d8c92ff modules: Add IRC configurations
Add options about Internal RC(IRC) oscillator.

- GD32_HAS_IRC_32K/40K indicates IRC types.
- GD32_LOW_SPEED_IRC_FREQUENCY is the numeric value of frequency

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2022-10-03 18:07:16 +02:00
Andriy Gelman
072a428f78 drivers: flash: Add xmc4xxx flash drivers
Add xmc4xxx flash drivers.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-10-03 13:56:49 +02:00
Joakim Andersson
63e45c8c7b soc: nordic_nrf: Allow building with TF-M without platform partition
Allow building for nRF non-secure and TF-M enabled without having the
platform partition enabled.
In this configuration the soc_secure functions have no valid
implementation, leave it as a compilation error if the application
includes the functions.

Add missing dependency on soc_secure functions being available for
SOC_HFXO_CAP_INTERNAL configuration.

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2022-10-03 10:17:45 +02:00
Joakim Andersson
c08964afd5 soc: nrf5340: Produce a Kconfig error when GPIO cannot be forwarded
Make Kconfig produce an error when GPIOs cannot be forwarded in the
current configuration instead of silently excluding the forwarding.

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2022-10-03 10:17:45 +02:00
Jun Lin
a55c9f8ce7 driver: kscan: npcx: add driver support for kscan
Add keyboard scan driver support.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2022-10-03 10:14:51 +02:00
Thad House
f11e5b77f6 rpi_pico: Mark RTT as supported by RP2XXX Chip
RTT is supported by the RP2XXX series of chips, so it should be marked
as such

Signed-off-by: Thad House <thadhouse1@gmail.com>
2022-10-03 10:12:17 +02:00
Peter Marheine
5eb75b81f7 arm: rename default RAM region from 'SRAM' to 'RAM'
It's useful for RAMABLE_REGION to have a uniform name when
CODE_DATA_RELOCATION is supported, because otherwise the build system
needs to be aware of how the region name differs between architectures.
Since architectures tend to prefer one of 'SRAM' or 'RAM' for that
region, prefer to use 'RAM' as the more general term.

Signed-off-by: Peter Marheine <pmarheine@chromium.org>
2022-10-03 10:09:53 +02:00
Jay Vasanth
64eeef9d57 soc: arm: microchip: update mec1501 soc header
update mec1501 soc.h to include soc_dt.h for pinctrl
related macros

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-09-21 18:05:32 +00:00
Emilio Benavente
2f149fb653 soc: arm: nxp: lpc55xxx: Added FlexPWM to the SOC Kconfig
Added MCUX_PWM Kconfig dependency;
Added missing pin function definition needed for PWM;
Enabled submodule clocks for FlexPWM

Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
2022-09-19 10:10:32 +00:00
Mahesh Mahadevan
46eaa81ac0 dts: rt1010: Fix RT1010 IP base addresses
Fix the Base addresses for the IP blocks that are
located at a different address on RT1010

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-09-16 14:50:06 -05:00
Daniel Leung
164a1aa95e soc: arm/nxp/imx/rt6xx: add bits to support I3C controller
This adds a few bits to the RT6xx SoC code to support the I3C
bus interface on RT600 series.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-09-09 17:42:33 -04:00
Andriy Gelman
538477f8b8 soc: arm: infineon: 4xxx: Fix UART comms during sleep
In normal operation the clock for peripheral devices is derived from
the PLL clock.
During sleep, the xmc4xxx can switch its system clock source (f_sys)
from the PLL clock to an f_ofi clock. Switching to the f_ofi clock
is the default behaviour which breaks UART comms.

Use the PLL clock source during sleep instead to fix the issue.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-09-09 16:30:36 -04:00
Andriy Gelman
5feae0eafc drivers: pinctrl: Add pinctrl driver for xmc4xxx
Add pinctrl driver for infineon xmc4xxx devices.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-09-09 16:28:41 -04:00
Mahesh Mahadevan
7f86411ed1 soc: mxrt: Add a compile time define for USB driver
Define DATA_SECTION_IS_CACHEABLE=1, this is used by
the SDK USB driver

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-09-09 09:44:46 -05:00
Mahesh Mahadevan
9619b02f9b soc: nxp: Add define needed by the SDK USB driver
1. Add USB_STACK_USE_DEDICATED_RAM=1 define that is
   used by the SDK USB driver
2. Delete unused "config USB_DEDICATED_MEMORY"

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-09-09 09:44:46 -05:00
Mahesh Mahadevan
9966181510 drivers: usb: mcux: Restructure driver for SDK updates
1. Move the defines from usb_dc_mcux.h to usb_device_config.h
   and fsl_os_abstraction.h. These headers are used by
   the SDK USB driver. usb_dc_mcux.h header file is not longer
   needed and hence deleted.
2. Delete the Zephyr implementation of the usb_device_struct
   driver and use the one implemented inside the SDK USB
   driver. This requires updating the references to
   usb_device_struct inside the USB driver
3. Move defines and structures used by the driver
   out of the header file that is included by the SDK and
   into the MCUX USB driver.
4. Use end point defines provided by Zephyr instead of adding
   them locally.
5. Add a Kconfig to set the thread stack size
6. Move code to enable interrupts back to usb_attach function.
   Interrupts should be enabled after the init is successful,
   else we see errors of the ISR getting called before the
   init is complete causing Faults
6. Update west.yml to update the NXP HAL to get the updated
   SDK USB driver.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-09-09 09:44:46 -05:00
Kumar Gala
318c12d17c timer: remove Kconfig.defconfig* setting of timer drivers
Now that timer drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-09-09 09:58:48 +00:00
Daniel DeGrasse
04773864a8 drivers: sdhc: add SD host controller driver for LPC SDIF
add SD host controller driver for LPC SDIF IP block, using NXP SDIF
HAL driver.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-09-08 10:06:28 +02:00
Nils Larsen
1d7ff08c82 dts: rt11xx: add enet1g peripheral and set up clock
The enet1g peripheral was missing in device tree for nxp rt11xx.
With this commit, the peripheral can be operated like the enet peripheral
with the eth_mcux (kinetis-ethernet) driver at 10/100 Mbit (no gigabit).

Signed-off-by: Nils Larsen <nils.larsen@posteo.de>
2022-09-07 16:50:08 -05:00
Antonio Tessarolo
a0c4dd71e1 soc/imx: imx6sx and imx7 fix pinmux mask (second fix)
According to RM, there are 2 pins that need a 3 bit mask for daisy chain,
changed it accordingly.
(E.g. IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT for imx6sx)

Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
2022-09-07 16:33:44 -05:00
Daniel DeGrasse
95994ca0fb soc: arm: nxp_kinetis: Fix flash MPU configuration for k6x
Fix NXP MPU configuration for k6x flash region. The previous flash MPU
setting was based around the assumption that the user was executing from
the flash region at 0x0000_0000–0x07FF_FFFF, which may not be case if the
user selects to execute from SRAM, such as running from sram_l

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-09-07 16:05:18 -05:00
Gerard Marull-Paretas
22e64fddfd drivers: pwm: gd32: use clock control API
Use the clock control API to enable/get rate of timer clocks.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-09-06 09:57:25 +02:00
Gerard Marull-Paretas
ca39f657b1 soc: arm,riscv: gigadevice: always enable CLOCK_CONTROL
Clock controller will be used by all drivers, so enable it by default.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-09-06 09:57:25 +02:00
Gerard Marull-Paretas
4aa31b4526 drivers: clock_control: gd32: initial support
This patch adds a clock control driver for GD32 platforms. It is
important to note that the driver is only able to handle peripheral
clocks, but not "system clocks" (e.g. PLL settings, SYS_CK, etc.).  On
some similar platforms (STM32) this task is embedded in the same clock
driver, performed at init time but with no options to do any
manipulation at runtime via the API calls. The clock control API as-is
is really orthogonal to "system clocks", and it is arguably a bad idea
to embed system clock init code in a clock control driver. It can be
done at SoC level still using Devicetree as a source of hardware
description/initial configuration.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-09-06 09:57:25 +02:00
Andrzej Kaczmarek
24821826ac soc: renesas_smartbond: Make SoC family Kconfig not selectable
Remove description from SOC_FAMILY_SMARTBOND so it's not directly
selectable. Also fix related board configuration.

Fixes #49916

Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
2022-09-05 14:50:30 +00:00
Gerard Marull-Paretas
79e6b0e0f6 includes: prefer <zephyr/kernel.h> over <zephyr/zephyr.h>
As of today <zephyr/zephyr.h> is 100% equivalent to <zephyr/kernel.h>.
This patch proposes to then include <zephyr/kernel.h> instead of
<zephyr/zephyr.h> since it is more clear that you are including the
Kernel APIs and (probably) nothing else. <zephyr/zephyr.h> sounds like a
catch-all header that may be confusing. Most applications need to
include a bunch of other things to compile, e.g. driver headers or
subsystem headers like BT, logging, etc.

The idea of a catch-all header in Zephyr is probably not feasible
anyway. Reason is that Zephyr is not a library, like it could be for
example `libpython`. Zephyr provides many utilities nowadays: a kernel,
drivers, subsystems, etc and things will likely grow. A catch-all header
would be massive, difficult to keep up-to-date. It is also likely that
an application will only build a small subset. Note that subsystem-level
headers may use a catch-all approach to make things easier, though.

NOTE: This patch is **NOT** removing the header, just removing its usage
in-tree. I'd advocate for its deprecation (add a #warning on it), but I
understand many people will have concerns.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-09-05 16:31:47 +02:00
Erwan Gouriou
f818b0478d drivers/timer: stm32: Enable lptim driver based on dt status
Similarly to other drivers, use auto generated DT_HAS_<COMPAT> Kconfig
symbol to control use of STM32 lptim driver.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-09-02 10:41:59 +00:00
Vijay Hiremath
f262b795b8 eSPI: npcx: Enable platform specific Virtual Wire GPIOs
Added code to enable platform specific Virtual Wire GPIOs. With this
change, able to send the USB-C overcurrent Virtual Wire event to
Meterolake SOC.

Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
2022-09-02 10:36:24 +00:00
Antonio Tessarolo
d552338637 soc/imx: imx6sx and imx7 fix pinmux mask
According to RM the daisy chain mask should include both bit 0 and 1, not
only bit 0.
Updated bitmask accordingly

Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
2022-09-01 12:19:00 -05:00
Marcin Niestroj
356960bcb5 ARM: nxp_imx: rt10xx: add XTAL and RTC_XTAL DT clocks
There are two external clocks driving i.MX RT 10xx SoCs: XTAL and
RTC_XTAL. Add "fixed-clock" DT nodes for each. Update also "nxp,imx-ccm"
binding, so that CCM (Clock Control Module) peripheral consumes those
clocks by "xtal" and "rtc-xtal" names.

Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2022-09-01 08:11:50 -05:00
Thomas Stranger
a41606ec52 soc: arch: stm32g0: fix strobe init for g070 an g0b0
The STM32G070 and STM32G0B0 Socs don't have USB power delivery support
but the PINs PD0, PD2, PB15, PA8 pins of these still have the same
pull down on boot configuration options as the SOCs with UCPD support.

This commit skips the check if such a peripheral is enabled,
therefore the configuration will always be applied on these SOCs
and the compile error is resolved.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
2022-09-01 10:28:48 +02:00
Erwan Gouriou
7d9b7d2934 soc: stm32u5: Request header-size 1024 when using imgtool
On STM32U5 series, when an image is build with mcuboot,
image starts at offset 0x400 instead of default 0x200.

This should be taken into account when calling imgtool by using
dedicated option to set header-size value.


Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-09-01 10:28:33 +02:00
Kumar Gala
3712e44fe0 intc: remove Kconfig.defconfig* setting of interrupt controller drivers
Now that interrupt controller drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-09-01 10:25:36 +02:00
Marcin Niestroj
611326b667 ARM: nxp_imx: rt10xx: remove unused LPUART peripheral header include
This allows to disable UART peripheral driver and still be able to build
correctly (header is not visible when LPUART driver is not enabled).

Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2022-09-01 10:25:13 +02:00
Marcin Niestroj
b47e6cc8ce ARM: nxp_imx: rt10xx: get systick freq from 'sysclk' DT nodelabel
So far systick frequency was duplicated in 'sysclk' DT nodelabel's
'clock-frequency' property and in per SoC SYS_CLOCK_HW_CYCLES_PER_SEC
default value. Set the latter based on DT configuration.

Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2022-09-01 10:24:55 +02:00
Andrzej Kaczmarek
f19252567c drivers: pinctrl: Add driver for smartbond
This adds pinctrl driver for Renesas SmartBond(tm) MCU family.

Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
2022-08-31 20:32:03 +02:00
Andrzej Kaczmarek
69cddb1a29 soc: Add Renesas SmartBond(tm) DA1469x series SoC
This adds initial support for Renesas SmartBond(tm) DA1469x series SoC.

Initailly only DA14699 is explicitly supported, however this code should
also run on other SoCs in this series since all of them support the same
core features available initially.

Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
2022-08-31 20:32:03 +02:00
Nils Larsen
a3bae01e74 drivers: sdhc: add clock init for USDHC2-block of NXP i.MX-processors
The missing init is added analog to existing init of USDHC1 block.

Signed-off-by: Nils Larsen <nils.larsen@posteo.de>
2022-08-31 13:21:17 -05:00
Mahesh Mahadevan
ce0b24b95a soc: nxp: Remove the no cache linker script
This has been moved to the NXP HAL layer so that all
SDK NonCacheable symbols get placed in the nocache
region
Also pull in the HAL changes associated with this
change.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-08-31 12:16:30 -05:00
Adam Wojasinski
a04a451a9f soc: arm: nordic_nrf: Replace deprecated nrfx API
This commit replaces API that became deprecated with the release
of nrfx2.9 - see CHANGELOG in zephyrproject-rtos:hal_nordic repository

Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
2022-08-31 10:43:14 +02:00
Kumar Gala
4f2cbdb41a crypto: remove Kconfig.defconfig* setting of crypto drivers
Now that crypto drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-30 10:43:12 +00:00
Gerard Marull-Paretas
014d831d80 soc: arm/riscv: gigadevice: enable reset controller by default
Similar to pinctrl, almost all device drivers will depend on the reset
controller being available, so default the driver class to y at SoC
level.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-08-29 10:30:49 +02:00
TOKITA Hiroshi
702d079007 soc: arm: gigadevice: Add support for GD32F407 soc
Add initial support for GD32F407 soc

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2022-08-29 10:27:15 +02:00
Kumar Gala
8d9f9d50f4 dma: remove Kconfig.defconfig* setting of DMA drivers
Now that DMA drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-26 14:27:23 +00:00
Kumar Gala
04adb949d1 soc: xilinx: zynq7000: move to using DT_STRING_UPPER_TOKEN_BY_IDX macro
Replaced hand coded use with DT_STRING_UPPER_TOKEN_BY_IDX.  We should have
introduced the APIs when this was needed since the token values in
devicetree_generated.h should only be accessed via an API macro.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-25 15:00:24 -07:00
Kumar Gala
1314d73104 I2S: remove Kconfig.defconfig* setting of I2S drivers
Now that I2S drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-25 15:03:11 -05:00
Yves Vandervennet
6b66d7f266 flash: nxp: enabling lpc55s36's FMC
This commit enables the SoC's flash memory controller.

 - added lpc55s36 specific code in the NXP MCUX driver
   to take advantage of the SoC's check-before-read
   capability
 - enabled the FMC node in the SoC's dtsi (iap)
 - added the flash controller chosen node to the board's dts

Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
2022-08-25 10:24:41 -05:00
Kumar Gala
3f8ba07b90 usb_device: remove Kconfig.defconfig* setting of usb device drivers
Now that usb device drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-25 08:05:54 -05:00