Commit graph

2589 commits

Author SHA1 Message Date
Guillaume Gautier
645d91b028 soc: arm: st_stm32: common: Increase the value of HW semaphore retry
When running the blinky example on STM32H747, with the BOOT_CM4 bit set
to 0, the M4 core goes into panic.
Increasing the value of the hardware semaphore retry prevents this.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2023-02-03 02:22:22 +09:00
Francois Ramu
0262d33478 soc: arm: stm32f3 enable Debug Module during SLEEP mode
This patch allows successive reflashing operation on stm32f3
boards by Enabling the Debug Module during SLEEP mode.
This will especially makes reflahing and debugging possible
with pyocd runner on west commands.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-02-02 10:35:17 +00:00
Almin Iriskic
0dcd6925d3 soc: stm32: fix rtt on stm32u5 series by enabling GPDMA1 clock
On some STM32 MCUs SEGGER RTT is only working with realtime updates
when DMA is clocked. The STM32U5 series uses a new DMA controller
module called GPDMA.

Refs: #34324
Fixes: #54316

Signed-off-by: Almin Iriskic <almin.iriskic@student.tugraz.at>
2023-02-02 02:43:21 +09:00
Stancu Florin
9f6d8c1c23 soc: cc13xx_cc26xx: add Kconfig option for custom radio hwattrs
Useful for implementing board-specific antenna switching using the RF
event callback.

Signed-off-by: Stancu Florin <niflostancu@gmail.com>
2023-01-27 17:44:38 +09:00
Stancu Florin
65039bf287 soc: cc13xx_cc26xx: add P chip variants to Kconfig
Add SOC_CC1352P and SOC_CC2652P chip types to SoC's Kconfig
(with integrated high power amplifiers).

Also requires modifications to HAL TI's family conditions.

Signed-off-by: Stancu Florin <niflostancu@gmail.com>
2023-01-27 17:44:38 +09:00
Stancu Florin
200a0db01a soc: cc13xx_cc26xx: config option to enable boost mode
New KConfig option to set `CCFG_FORCE_VDDR_HH` inside CC13xx/CC26xx
customer configuration file, making it it possible to use 14dBm
TX power (instead of the default 13 dBm limitation).

Signed-off-by: Stancu Florin <niflostancu@gmail.com>
2023-01-27 17:44:38 +09:00
Jamie McCrae
ec7044437e treewide: Disable automatic argparse argument shortening
Disables allowing the python argparse library from automatically
shortening command line arguments, this prevents issues whereby
a new command is added and code that wrongly uses the shortened
command of an existing argument which is the same as the new
command being added will silently change script behaviour.

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2023-01-26 20:12:36 +09:00
Alberto Escolar Piedras
8a5273525e nrf52_bsim: Convert from a nRF52832 to a nRF52833
The nRF HW models have been updated to correspond to a 52833 instead
of a 52832. Let's follow them.

The motivation for the change is to enable proper BIS encryption support
(for BT LE Audio ISO).

Changes:

* Point in manifest to latest HW models

* SOC_COMPATIBLE_NRF52832 has been removed, and SOC_COMPATIBLE_NRF52833
added in its place (with no uses at this point)

* Where SOC_COMPATIBLE_NRF52832 was used to set encryption like for a 52832
(to avoid using the MAXPACKETLENGHT), we set the condition to just
SOC_NRF52832.
Note: The MAXPACKETLENGHT register exists in the new simulated nrf52833,
thought it does nothing.

* In the BLE ctrl LLL radio HAL, all macros are renamed accordingly
(timings are NOT changed).

* Board dts definition now refers to the 52833 soc definition. New 52833
features set as not supported by now.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-01-26 09:29:18 +01:00
Jeppe Odgaard
9fb47e43a8 dts: arm: add xbar and qdec nodes and update soc
Add three xbar nodes and four qdec nodes in the rt10xx devicetree include.
Add xbara to rt1052 in Kconfig.soc

Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
2023-01-24 10:21:39 -06:00
Manuel Arguelles
4a3c630f7b boards: s32z270dc2_r52: enable Ethernet support
Introduce DT nodes for NETC complex and enable its usage for
s32z270dc2_r52 boards. Using PSI0 as default networking interface and
Switch Port0 as it's the only port available on this board.

Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
2023-01-24 14:37:20 +01:00
Filip Kokosinski
4b198e2009 soc: arm :efr32bg22: depend on DT_HAS_*_ENABLED for SPI selection
This commit modifies the defconfig for efr32bg22 SoC so that Gecko SPI
selection depends on the DT_HAS_*_ENABLED define.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2023-01-17 15:37:27 -06:00
Daniel DeGrasse
47271ce8be treewide: update usage of zephyr_code_relocate
Update usage of zephyr_code_relocate to follow new API. The old method
of relocating a file was the following directive:

zephyr_code_relocate(file location)

The new API for zephyr_code_relocate uses the following directive:

zephyr_code_relocate(FILES file LOCATION location)

update in tree usage to follow this model. Also, update the NXP HAL SHA,
as NXP's HAL uses this macro as well.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-01-17 18:08:37 +01:00
Declan Snyder
19bd9a3618 boards: arm: Renamed NXP usdhc in imxrt5xx
The names of these peripherals in the device tree
did not match the Reference Manual for the RT500.

Also fixed a typo in a comment referring to USDHC which should have been
about USB.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-01-14 09:22:22 +01:00
Declan Snyder
36b6dec832 boards: arm: mimxrt595_evk: Plumbs RT595 USDHC
- Adds the pin controls and ushdc settings in device tree
- Attaches clock to USDHC in soc.c
- Adds binding for mmc

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-01-14 09:22:22 +01:00
Pawel Czarnecki
750e6c946e soc: arm: efr32bg22: include soc_gpio.h
Include header required in Gecko I2C driver

Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
2023-01-13 10:23:55 -06:00
Pawel Czarnecki
371e893314 soc: arm: efr32bg22: defconfig: remove I2C_GECKO default n
Don't disable I2C by default

Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
2023-01-13 10:23:55 -06:00
YuLong Yao
2086acfa0e soc: gd32a50x: introduce gd32a50x soc series
soc: gd32a50x: introduce gd32a50x soc series

Signed-off-by: YuLong Yao <feilongphone@gmail.com>
2023-01-12 21:45:38 +01:00
Mateusz Sierszulski
b36a31fd7a drivers: entropy: Add Gecko trng driver for EFR32BG22
This commit enables entropy driver on EFR32BG22 SoC.

Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
2023-01-12 15:22:11 +00:00
Andrzej Głąbek
c50108113d soc: nrf53: Fix extraction of the XOSC32MTRIM.SLOPE bitfield
The value in this bitfield is provided in the two's complement form,
so it requires special handling. Previously, it was read as just an
unsigned value and this could result in a wrongly computed CAPVALUE.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2023-01-12 13:30:58 +01:00
Mulin Chao
b1214ead19 driver: i2c: npcx: simplify smb bank registers with union
For NPCX SMB/I2C SMB modules in FIFO mode, the registers include:

* Common registers, offset 0x00-0x0f, accessible regardless of the value
  of BNK_SEL
* Bank 0 registers, offset 0x10-0x1e, accessible if BNK_SEL is set to 0
* Bank 1 registers, offset 0x10-0x1e, accessible if BNK_SEL
is set to 1

In the current driver, it uses two structures, `smb_reg` and
`smb_fifo_reg`, to access `Common + Bank 0` and `Common + Bank 1`
registers. But It might be easy to misunderstand that they are two
different modules.

This CL tries to simplify this by the following steps:

1. Use `union` to combine `Bank 0/1` registers in the same structure.
2. Remove `smb_fifo_reg`. We needn't use two structures to present
   SMB registers.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-01-11 09:40:36 +01:00
Michał Barnaś
3ae105e76b ec_host_cmd: add NPCX SHI peripheral for the host commands
This commit adds the support for host commands being transported
by the Serial Host Interface on the NPCX SoC.

Signed-off-by: Michał Barnaś <mb@semihalf.com>
2023-01-11 09:38:45 +01:00
Mahesh Mahadevan
0eb3c15715 soc: nxp: Add Power Management support for RT5xx
1. Support Sleep, Deep Sleep and Deep Power down modes
2. Enable the MEMC FlexSPI driver when using device power
   management so we can reconfigure the FlexSPI pins to
   save power. The MEMC FlexSPI driver is enabled when we
   enable the Flash subsystem, however we would like to
   reconfigure the FlexSPI pins even when the Flash driver
   is disabled, hence MEMC is selected when PM_DEVICE
   is turned on.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2023-01-04 11:03:42 -06:00
Manuel Arguelles
a7743a49aa drivers: pinctrl: rename S32 to NXP S32
Following updates previously done for other drivers, rename all
occurrences of S32 to NXP S32 to avoid ambiguity.

Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
2023-01-04 16:51:38 +01:00
Daniel DeGrasse
1af8f2700b soc: arm: add support for FlexSPI1 clock configuration for NXP RT5xx
Add support for configuring FlexSPI1 clock speed to RT5xx soc
initialization, so that memory present on FlexSPI1 can be accessed.
Note that FlexSPI1 is referred to as FlexSPI2 in the dts files for this
SOC.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-01-04 10:35:25 +01:00
Cyril Fougeray
56ee74615c soc: arm: stm32g4: PM support
Add power management support for STM32G4 series.
Supported modes include STOP0 and STOP1.

Signed-off-by: Cyril Fougeray <cyril.fougeray@worldcoin.org>
2023-01-03 11:00:58 +01:00
Jay Vasanth
3583421134 soc: microchip_mec: Replace test clock out Kconfig with DT entry
Remove the test clock out Kconfig from SoC level. Instead use
device tree PINCTRL entry with updated clock control driver.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-12-28 10:43:03 +01:00
Jay Vasanth
c7e0d727d7 drivers: clock: Microchip XEC clock driver add MEC15xx support
Add support for Microchip MEC15xx to the XEC clock control driver.
MEC15xx 32KHz clock support uses the same 32KHz source for both the
PLL and peripherals. MEC152x does not include the PCR clock monitor
present in MEC172x.  MEC15xx and MEC172x support internal silicon
oscillator, parallel and single ended crystal inputs, and the
32KHZ_PIN input. MEC152x supports fall back to internal silicon
OSC when VTR and 32KHZ_PIN are turned off. Therefore in MEC152x the
internal silicon oscillator can only be disabled if using an external
32KHz which is always on. For MEC152x the driver will only use the
PLL source clock device tree value.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-12-28 10:43:03 +01:00
Jay Vasanth
ed52729a4b drivers: clock: Microchip MEC172x clock control driver support all modes
Fix Microchip XEC clock control driver single-ended XTAL2 pin
initialization. Add support for external 32KHZ_IN pin as a
clock source including PINTRL to switch the GPIO to 32KHZ_IN
function. Add device tree option to disable internal silicon
oscillator if it is not required by the configuration. Add
device tree tuning options based on crystal and board layout.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-12-28 10:43:03 +01:00
HaiLong Yang
e6b600e0c3 soc: arm: gigadevice: add gd32l23x series
The Cortex-M23 on GD32L23x implement the System Timer, but not
contain FPU.

Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
2022-12-28 10:37:52 +01:00
Reto Schneider
cb7791baf1 soc: nrf52: Kconfig option for nRF52840 anomaly 198
Enabling by default (if SPI3 used) because it affects all revisions
since "Engineering B", including the most recent one as of today
(revision 3).

Size changes when enabled:
 - -Og: flash +160 bytes (+0.02%), RAM +8 bytes (+0.01%)
 - -Os: flash +144 bytes (+0.02%), no change to RAM usage

Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
2022-12-27 15:32:22 +01:00
Andriy Gelman
ed105761fa soc: arm: infineon_xmc: 4xxx: Disable unalign trap on reset
The unaligned trap bit is set by default, contrary to the xmc
reference manual. This PR unsets the bit in the initialization.
It can still be set later via the CONFIG_TRAP_UNALIGNED_ACCESS
option.

Note that the same approach is used in xmc4500 reference software
init code (see SystemCoreSetup() in infineon hal module).

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-12-23 14:57:17 +01:00
Emilio Benavente
2c58952416 soc: arm: nxp_imx: replaced CODE_LOCATION and added FLEXSPI_XIP to soc
Cleaning up the instances of CODE_LOCATION used in the soc
clock_init and replaced them with the Kconfig
FLASH_MCUX_FLEXSPI_XIP due to the correlation with
the flexspi clocks and the XIP feature of Flexspi.

Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
2022-12-22 11:07:08 +01:00
Emilio Benavente
39762716d4 boards: arm: rtxxx: moving the instances FLASH_MCUX_FLEXSPI_XIP
This Kconfig is moved to the soc level since it determines
the flexspi clock initialization for XIP.

Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
2022-12-22 11:07:08 +01:00
Lukasz Mazur
f7ab9a8c52 pinctrl_stm32: GPIO output info in Z_PINCTRL_STM32_PINCFG_INIT
Added information about pin output direction into
Z_PINCTRL_STM32_PINCFG_INIT if output_low or output_high is provided.
GPIO output flag is set in configuration struct and this will end up
being loaded into MODE register. Because of that it is no longer
required for pinctrl_configure_pins() to set MODE register value for
GPIO input/output.
Fixes #53141.

Signed-off-by: Lukasz Mazur <lukasz.mazur@hidglobal.com>
2022-12-22 11:00:45 +01:00
Erwan Gouriou
66d4c64966 all: Fix "#if IS_ENABLED(CONFIG_FOO)" occurrences
Clean up occurrences of "#if IS_ENABLED(CONFIG_FOO)" an replace
with classical "#if defined(CONFIG_FOO)".

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-12-21 10:09:23 +01:00
Filip Kokosinski
509e101a91 soc: silabs_exx32: Add support for SiLabs EFR32BG22 SoC
This commit adds support for Silicon Labs EFR32BG22 SoC.

Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2022-12-20 22:50:19 +01:00
Pawel Czarnecki
e8d3673c13 soc: arm: silabs: remove soc_gpio_configure wrapper
It would be better to use GPIO_PinModeSet() functions directly
in the drivers.

Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
2022-12-20 22:50:19 +01:00
Andriy Gelman
2d3493bff0 drivers: adc: Add ADC xmc4xxx drivers
The ADC module has four conversion groups, each one is set up as a zephyr
device. The start-up calibration is initiated globally for all groups
and it is run in each device init function. The ADC module supports post
calibration per group. Post calibration is run automatically after each
group acquires the samples.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-12-20 14:17:23 +01:00
Andriy Gelman
f197fe0684 soc: arm: infineon_xmc: Set include headers via xmc_device.h
xmc_device.h sets which XMC4xxx.h file to include and also sets
other defines such as GLOCK_GATING_SUPPORTED.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-12-20 14:17:23 +01:00
Nils Larsen
ca6d02147d nxp_imx: fix base address of Flexspi2
The base address is 0x400d0000 not 0x4000d000

Signed-off-by: Nils Larsen <nils.larsen@posteo.de>
2022-12-16 15:37:55 +01:00
Daniel DeGrasse
4be1fb81ce soc: arm: nxp: switch imxrt boards to use systick timer unless CONFIG_PM=y
Switch all imxrt boards to use the systick timer by default, and only
enable the GPT timer when using low power modes. This is desirable
because the systick has a higher resolution, but the GPT can run
while the core clock is gated, making it useful for low power modes.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-12-16 09:31:48 +01:00
Andriy Gelman
727e589448 drivers: interrupt_controller: Add XMC4XXX ERU driver
In Infineon XMC4XXX SoCs, gpio interrupts are triggered via an
Event Request Unit (ERU) module. A subset of the gpios are
connected to the ERU. The ERU monitors edge triggers and creates
a SR.

This driver configures the ERU for a target port/pin combination
for rising/falling edge events. Note that the ERU module does
not generate SR based on the gpio level. Internally the ERU
tracks the *status* of an event. The status is set on a positive
edge and unset on a negative edge (or vice-versa depending on
the configuration). The value of the status is used to implement
a level triggered interrupt; The ISR checks the status flag and
calls the callback function if the status is set.

The ERU configurations for supported port/pin combinations are
stored in a devicetree file dts/arm/infineon/xmc4xxx_x_x-intc.dtsi.
The configurations are stored in the opaque array
uint16 port_line_mapping[].

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-12-12 10:51:29 +01:00
Duong Vu Nam
a8a72c581e soc: arm: refactor MPU region for NXP S32Z/E
Currently, memory from  __rodata_region_end to __kernel_ram_start (or
_app_smem_start if config userspace) was uncovered by programable MPU
region. But to config static MPU region (nocache region is on ths
region), the programable MPU region need confg full patition.

Signed-off-by: Duong Vu Nam <duong.vunam@nxp.com>
2022-12-12 10:39:31 +01:00
Duong Vu Nam
7fc20ec0bc Soc: arm: enable I/D-caches at NXP S32Z/E SoC
Enable cache to increase retrieval performance.

Signed-off-by: Duong Vu Nam <duong.vunam@nxp.com>
2022-12-12 10:39:31 +01:00
TOKITA Hiroshi
edc115b1b7 soc: gd32f4xx: correct typo
RCU_CFG1_TIMERSEK_MSK -> RCU_CFG1_TIMERSEL_MSK

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2022-12-12 10:08:12 +01:00
Filip Brozovic
3453a3b247 drivers: pinctrl: add numicro pinctrl driver
This commit adds a pinctrl driver for the Nuvoton NuMicro family
of processors.

Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
2022-12-08 18:46:33 +01:00
Jose Alberto Meza
5d34891ae0 soc: arm: microchip: mec172x: Correct PECI base address
Use correct device tree entry

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2022-12-07 09:45:25 -06:00
Daniel DeGrasse
6bcdcc3795 dts: nxp_imx: Add zephyr,memory-region attribute to memory regions
Add zephyr,memory-region compatible and attribute to SOC memory regions,
so that sections will be generated and MPU attributes can be applied.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-12-05 19:54:37 +01:00
Daniel DeGrasse
66f35b286c soc: nxp_imx: Add code to wait for second core boot in RT11xx
Use the messaging unit to ensure that the RT11xx dual core mode will
wait for the second core to boot successfully during early init

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-12-05 19:54:37 +01:00
Daniel DeGrasse
5992ae2a3d soc: rt11xx: Enabled multicore support with second image
RT11xx features CM4 core, which must be booted from CM7 core. Add
support for loading an image for the CM4 to RAM, and booting the CM4 core
from this image. Each image is built independently using sysbuild, and the
M4 image build produces built collateral with load address information the
M7 image can use to load it to RAM

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-12-05 19:54:37 +01:00