- Adds the pin controls and ushdc settings in device tree
- Attaches clock to USDHC in soc.c
- Adds binding for mmc
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The value in this bitfield is provided in the two's complement form,
so it requires special handling. Previously, it was read as just an
unsigned value and this could result in a wrongly computed CAPVALUE.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
For NPCX SMB/I2C SMB modules in FIFO mode, the registers include:
* Common registers, offset 0x00-0x0f, accessible regardless of the value
of BNK_SEL
* Bank 0 registers, offset 0x10-0x1e, accessible if BNK_SEL is set to 0
* Bank 1 registers, offset 0x10-0x1e, accessible if BNK_SEL
is set to 1
In the current driver, it uses two structures, `smb_reg` and
`smb_fifo_reg`, to access `Common + Bank 0` and `Common + Bank 1`
registers. But It might be easy to misunderstand that they are two
different modules.
This CL tries to simplify this by the following steps:
1. Use `union` to combine `Bank 0/1` registers in the same structure.
2. Remove `smb_fifo_reg`. We needn't use two structures to present
SMB registers.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit adds the support for host commands being transported
by the Serial Host Interface on the NPCX SoC.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
1. Support Sleep, Deep Sleep and Deep Power down modes
2. Enable the MEMC FlexSPI driver when using device power
management so we can reconfigure the FlexSPI pins to
save power. The MEMC FlexSPI driver is enabled when we
enable the Flash subsystem, however we would like to
reconfigure the FlexSPI pins even when the Flash driver
is disabled, hence MEMC is selected when PM_DEVICE
is turned on.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Following updates previously done for other drivers, rename all
occurrences of S32 to NXP S32 to avoid ambiguity.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Add support for configuring FlexSPI1 clock speed to RT5xx soc
initialization, so that memory present on FlexSPI1 can be accessed.
Note that FlexSPI1 is referred to as FlexSPI2 in the dts files for this
SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Remove the test clock out Kconfig from SoC level. Instead use
device tree PINCTRL entry with updated clock control driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add support for Microchip MEC15xx to the XEC clock control driver.
MEC15xx 32KHz clock support uses the same 32KHz source for both the
PLL and peripherals. MEC152x does not include the PCR clock monitor
present in MEC172x. MEC15xx and MEC172x support internal silicon
oscillator, parallel and single ended crystal inputs, and the
32KHZ_PIN input. MEC152x supports fall back to internal silicon
OSC when VTR and 32KHZ_PIN are turned off. Therefore in MEC152x the
internal silicon oscillator can only be disabled if using an external
32KHz which is always on. For MEC152x the driver will only use the
PLL source clock device tree value.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Fix Microchip XEC clock control driver single-ended XTAL2 pin
initialization. Add support for external 32KHZ_IN pin as a
clock source including PINTRL to switch the GPIO to 32KHZ_IN
function. Add device tree option to disable internal silicon
oscillator if it is not required by the configuration. Add
device tree tuning options based on crystal and board layout.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Enabling by default (if SPI3 used) because it affects all revisions
since "Engineering B", including the most recent one as of today
(revision 3).
Size changes when enabled:
- -Og: flash +160 bytes (+0.02%), RAM +8 bytes (+0.01%)
- -Os: flash +144 bytes (+0.02%), no change to RAM usage
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
The unaligned trap bit is set by default, contrary to the xmc
reference manual. This PR unsets the bit in the initialization.
It can still be set later via the CONFIG_TRAP_UNALIGNED_ACCESS
option.
Note that the same approach is used in xmc4500 reference software
init code (see SystemCoreSetup() in infineon hal module).
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Cleaning up the instances of CODE_LOCATION used in the soc
clock_init and replaced them with the Kconfig
FLASH_MCUX_FLEXSPI_XIP due to the correlation with
the flexspi clocks and the XIP feature of Flexspi.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
This Kconfig is moved to the soc level since it determines
the flexspi clock initialization for XIP.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Added information about pin output direction into
Z_PINCTRL_STM32_PINCFG_INIT if output_low or output_high is provided.
GPIO output flag is set in configuration struct and this will end up
being loaded into MODE register. Because of that it is no longer
required for pinctrl_configure_pins() to set MODE register value for
GPIO input/output.
Fixes#53141.
Signed-off-by: Lukasz Mazur <lukasz.mazur@hidglobal.com>
Clean up occurrences of "#if IS_ENABLED(CONFIG_FOO)" an replace
with classical "#if defined(CONFIG_FOO)".
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit adds support for Silicon Labs EFR32BG22 SoC.
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The ADC module has four conversion groups, each one is set up as a zephyr
device. The start-up calibration is initiated globally for all groups
and it is run in each device init function. The ADC module supports post
calibration per group. Post calibration is run automatically after each
group acquires the samples.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
xmc_device.h sets which XMC4xxx.h file to include and also sets
other defines such as GLOCK_GATING_SUPPORTED.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Switch all imxrt boards to use the systick timer by default, and only
enable the GPT timer when using low power modes. This is desirable
because the systick has a higher resolution, but the GPT can run
while the core clock is gated, making it useful for low power modes.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
In Infineon XMC4XXX SoCs, gpio interrupts are triggered via an
Event Request Unit (ERU) module. A subset of the gpios are
connected to the ERU. The ERU monitors edge triggers and creates
a SR.
This driver configures the ERU for a target port/pin combination
for rising/falling edge events. Note that the ERU module does
not generate SR based on the gpio level. Internally the ERU
tracks the *status* of an event. The status is set on a positive
edge and unset on a negative edge (or vice-versa depending on
the configuration). The value of the status is used to implement
a level triggered interrupt; The ISR checks the status flag and
calls the callback function if the status is set.
The ERU configurations for supported port/pin combinations are
stored in a devicetree file dts/arm/infineon/xmc4xxx_x_x-intc.dtsi.
The configurations are stored in the opaque array
uint16 port_line_mapping[].
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Currently, memory from __rodata_region_end to __kernel_ram_start (or
_app_smem_start if config userspace) was uncovered by programable MPU
region. But to config static MPU region (nocache region is on ths
region), the programable MPU region need confg full patition.
Signed-off-by: Duong Vu Nam <duong.vunam@nxp.com>
Add zephyr,memory-region compatible and attribute to SOC memory regions,
so that sections will be generated and MPU attributes can be applied.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use the messaging unit to ensure that the RT11xx dual core mode will
wait for the second core to boot successfully during early init
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
RT11xx features CM4 core, which must be booted from CM7 core. Add
support for loading an image for the CM4 to RAM, and booting the CM4 core
from this image. Each image is built independently using sysbuild, and the
M4 image build produces built collateral with load address information the
M7 image can use to load it to RAM
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Allow linking code into OCRAM region when building for RT1xxx SOCs. This
can be used on the RT11xx dual core SOCs as a shared memory region, when
the M7 core needs to load code into a region accessible to the M4 core.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Expand ifdef by adding new Kconfig option UDC_KINETIS as
preparation for USBFSOTG UDC driver.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
The cache operations must be quick, optimized and possibly inlined. The
current API is clunky, functions are not inlined and passing parameters
around that are basically always known at compile time.
In this patch we rework the cache functions to allow us to get rid of
useless parameters and make inlining easier.
In particular this changeset is doing three things:
1. `CONFIG_HAS_ARCH_CACHE` is now `CONFIG_ARCH_CACHE` and
`CONFIG_HAS_EXTERNAL_CACHE` is now `CONFIG_EXTERNAL_CACHE`
2. The cache API has been reworked.
3. Comments are added.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add a hidden Kconfig option to select the index of the target RTU
(Real-Time Unit) subsystem. This index can be used by peripheral
drivers, for example, to know the peripheral instance index since the
HAL is index-based.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Microchip XEC GPIO pins support inverting the output of
alternate pin functions. This feature may be useful for
those peripherals that do not implement output inversion
in the peripheral. GPIO control register pad input and
parallel input register values are not affected by the
function output invert feature. GPIO interrupt detection
of an output is inverted if the invert polarity is enabled.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Added a missing SDK function POWER_PowerInit
to the clock_init function of the soc in lpc55S36.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
EXTRA_IMGTOOL_ARGS is used to set additional options by the user.
Any user change will overwrite this option, which
is unintuitive.
Also option ROM_START_OFFSET will be overwritten which is also unintuitive.
Replace hardcoded config option MCUBOOT_EXTRA_IMGTOOL_ARGS
with proper config ROM_START_OFFSET.
Signed-off-by: Maciej Zagrabski <mzi@trackunit.com>
HAL for NXP S32 is updated to a newer version, hence some headers and
macro definitions must be updated accordingly.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Update rt5xx base address calculation to use the zephyr,chosen flash node
to determine flash base address. Note that due to the external flash
controller, the flexSPI base address must be used when the flash device
is on the flexSPI bus.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update rt6xx base address calculation to use the zephyr,chosen flash node
to determine flash base address. Note that due to the external flash
controller, the flexSPI base address must be used when the flash device
is on the flexSPI bus.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Updated the clock_init function to the latest sdk
and added a safe initialization for the flash setup
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Added a selecion on rt6xx that allows the loading of
the safe flash clock initialization to be inside SRAM
if the user code is being executed from flash.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Call CMSIS SystemInit at early platform boot, to ensure that registers
are configured correctly on RT10xx series.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update lpc54114 support to use LMA address offset instead of linking
secondary core image into primary core memory. This will allow support
with sysbuild to be enabled. Additionally, use partitions to select where
the secondary core image will be located in flash
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use LMA adjustment building dual core image with LPC55s69. The load
address adjustment allows the second core image to be flashed onto the chip
by the debugger, into the secure region of the LPC flash.
Additionally, remove the build dependency that was enforced by the SOC.
This requirement to build the secondary core image first can be enforced
by the project itself, instead of the core.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Move regs configuration from previous pinmux.c to soc layer.
This involves the debug interface, configuring the GPIO bank power
and the test clock out pin.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Only include fsl_flexspi_nor_boot when a boot header is present,
as this is the only case where the boot header data will be required.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The icmsg backend for ipc_service has a limitation of supporting only
on endpoint. This limitation is acceptable for many IPC instances.
However, some require to use multiple endpoints sharing a single
instance. To preserve the simple and the most efficient single-instance
backend, a separated backend is introduced implementing a wrapper
around icmsg core which adds multiple endpoints support.
There are two multi-endpoint ipc_service icmsg backends: one in the
initiator role, and the other one in the follower role. In a IPC
configuration one end of communication must be in the follower role
while the other one is in the initiator. The initiator initiates
an endpoint discovery handshake to establish enpoint identifiers for
requested endpoint names. The follower responds to requests sent by
the initiator.
Signed-off-by: Hubert Miś <hubert.mis@nordicsemi.no>
The `mps2_an521_remote` and `mps2_an521_ns` targets have the same
memory layout for code and ram, meaning that you can't use TF-M
(`mps2_an521_ns`) and the second core (`mps2_an521_remote`) at the
same time.
This commit updates the memory map of the `_ns` build targets as
follows:
- Reduces the code memory region from 1 MB to 512 KB, maintaining the
existing base memory address of `0x0010 0000`
- Maintains the existing 512 KB ram memory at `0x2810 0000`
It updates the `_remote` target as follows:
- Reserves 468 KB code memory at address `0x0038 B000`
- Reserves 512 KB ram memory at address `0x2818 0000`
This ensures that the code region for the `_remote` target doesn't
overlap with the code region used by the single flash image layout
defined upstream in TF-M, which the `_ns` target is based upon.
Signed-off-by: Kevin Townsend <kevin.townsend@linaro.org>
Adds Atmel SAMC20 and SAMC21 soc. C series is based on Cortex-M0+.
C21 contains CAN interface.
The init routines are same for SAMC20 and SAMC21. They use one
clock OSC48M without configuration.
The code is inspirated from atmel_sam0/samd21.
Signed-off-by: Kamil Serwus <kserwus@gmail.com>
Some SAM0 contains revisions with separated includes for example
SAMC21 and SAMC21N.
Signed-off-by: Kamil Serwus <kserwus@gmail.com>
Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
Those dividers were configured in Kconfig so far. Add 'arm-podf',
'ahb-podf' and 'ipg-podf' "fixed-factor-clock" compatible DT child nodes
under 'ccm' (Clock Control Module) and use configured 'clock-div' values
instead of Kconfig equivalents.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
STM32WB Controller supports application to initiate the "PHY Update
Procedure" (BT_USER_PHY_UPDATE) while it doesn't support it to be
automatically triggered on connection establishment (BT_AUTO_PHY_UPDATE).
Default BT_USER_PHY_UPDATE to true, which automatically defaults
BT_AUTO_PHY_UPDATE to false.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Now that IPM drivers are enabled based on devicetree we can
remove any cases of them getting enabled by Kconfig, *defconfig*,
and *.conf files.
We need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Microchip MEC172x has a modified eSPI SAF hardware implementation.
Hardware changes include multiple clock dividers for each SPI
flash device and data transfer using QMSPI local DMA.
espi reset interrupt is made a higer priority in MEC172x devicetree
because espi reset event resets all espi hardware and we don't
to want to service any other espi interrupt blocks when espi reset
occurs.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x eSPI SAF has significant hardware changes
requiring a new SAF configuration structure. In preparation
for the MEC172x we move the current SAF header out of common
to the MEC1501 subfolder, remove an unused and empty common
header and remove includes of the moved headers from MEC172x.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x QMSPI expanded its clock divider register
field from 8 to 16 bits. QMSPI source clock is on the fast
peripheral domain therefore get the frequency from the clock
control driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
eSPI PUT_IOWR_SHORT protocol can send 1/2/4 bytes of data in a single
transaction. This allows the host to send max 32-bits Port80 code
at one time. This CL sets bits OFS0_SEL~OFS3_SEL in the DPAR1 register
to let the EC hardware put the full Port80 code to DP80BUF FIFO.
It also groups the N-byte code into a single 32-bits variable when
necessary by analyzing the offset field in the DP80BUF register.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Allows applications to use other frequencies than 60 MHz.
For example 48 MHz for USB communication with usbserial driver.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
Continue to phase out MP_NUM_CPUS, change Kconfig to be
MP_MAX_NUM_CPUS and make MP_MAX_NUM_CPUS the main Kconfig symbol.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Include the correct header file. This was uncovered due to
a recent change where zephyr/kernel.h include was removed
from init.h
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Introduce support for Pinctrl driver on NXP S32Z/E SoC's.
The NXP S32 pin controller is a singleton node responsible for
controlling the pin function selection and pin properties, based on the
pin node group approach. The pinmux configuration is encoded in a
32-bit value.
Each S32 SoC implementing Pinctrl must create a `pinctrl_soc.h` header
which define SoC-specific macros to initialize the pinctrl structure.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
This patch introduces support for NXP S32 devices, specifically for
S32Z27 from S32Z/E family.
NXP S32Z27 processors are composed of two Real-Time Units (RTU)
containing each four ARM Cortex-R52 cores with flexible split/lock
configuration, and dedicated internal SRAM.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
sys/util.h is not needed by soc.h, and was causing troubles with
redefinitions of ARRAY_SIZE (from HAL) in CI.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some files make use of NMI API (NMI_INIT()) without including the
appropriate headers.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some files make use of CMSIS APIs/definitions without explicitely
including CMSIS headers.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The sys* ops like sys_clear_bit are indirectly included via arch CPU
header. Other stuff like find_msb_set end up included via this header as
well.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
add common mec_gpio.h to allow access to common gpio_regs
structure for both mec15xx and mec17xx, used in pinctrl driver
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
The platform has support for pinctrl, but it is selecting both pinmux
and pinctrl. Legacy applications requiring pinmux should enable it
manually.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add options about Internal RC(IRC) oscillator.
- GD32_HAS_IRC_32K/40K indicates IRC types.
- GD32_LOW_SPEED_IRC_FREQUENCY is the numeric value of frequency
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Allow building for nRF non-secure and TF-M enabled without having the
platform partition enabled.
In this configuration the soc_secure functions have no valid
implementation, leave it as a compilation error if the application
includes the functions.
Add missing dependency on soc_secure functions being available for
SOC_HFXO_CAP_INTERNAL configuration.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Make Kconfig produce an error when GPIOs cannot be forwarded in the
current configuration instead of silently excluding the forwarding.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
It's useful for RAMABLE_REGION to have a uniform name when
CODE_DATA_RELOCATION is supported, because otherwise the build system
needs to be aware of how the region name differs between architectures.
Since architectures tend to prefer one of 'SRAM' or 'RAM' for that
region, prefer to use 'RAM' as the more general term.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
In normal operation the clock for peripheral devices is derived from
the PLL clock.
During sleep, the xmc4xxx can switch its system clock source (f_sys)
from the PLL clock to an f_ofi clock. Switching to the f_ofi clock
is the default behaviour which breaks UART comms.
Use the PLL clock source during sleep instead to fix the issue.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
1. Add USB_STACK_USE_DEDICATED_RAM=1 define that is
used by the SDK USB driver
2. Delete unused "config USB_DEDICATED_MEMORY"
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Move the defines from usb_dc_mcux.h to usb_device_config.h
and fsl_os_abstraction.h. These headers are used by
the SDK USB driver. usb_dc_mcux.h header file is not longer
needed and hence deleted.
2. Delete the Zephyr implementation of the usb_device_struct
driver and use the one implemented inside the SDK USB
driver. This requires updating the references to
usb_device_struct inside the USB driver
3. Move defines and structures used by the driver
out of the header file that is included by the SDK and
into the MCUX USB driver.
4. Use end point defines provided by Zephyr instead of adding
them locally.
5. Add a Kconfig to set the thread stack size
6. Move code to enable interrupts back to usb_attach function.
Interrupts should be enabled after the init is successful,
else we see errors of the ISR getting called before the
init is complete causing Faults
6. Update west.yml to update the NXP HAL to get the updated
SDK USB driver.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Now that timer drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
The enet1g peripheral was missing in device tree for nxp rt11xx.
With this commit, the peripheral can be operated like the enet peripheral
with the eth_mcux (kinetis-ethernet) driver at 10/100 Mbit (no gigabit).
Signed-off-by: Nils Larsen <nils.larsen@posteo.de>
According to RM, there are 2 pins that need a 3 bit mask for daisy chain,
changed it accordingly.
(E.g. IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT for imx6sx)
Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
Fix NXP MPU configuration for k6x flash region. The previous flash MPU
setting was based around the assumption that the user was executing from
the flash region at 0x0000_0000–0x07FF_FFFF, which may not be case if the
user selects to execute from SRAM, such as running from sram_l
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This patch adds a clock control driver for GD32 platforms. It is
important to note that the driver is only able to handle peripheral
clocks, but not "system clocks" (e.g. PLL settings, SYS_CK, etc.). On
some similar platforms (STM32) this task is embedded in the same clock
driver, performed at init time but with no options to do any
manipulation at runtime via the API calls. The clock control API as-is
is really orthogonal to "system clocks", and it is arguably a bad idea
to embed system clock init code in a clock control driver. It can be
done at SoC level still using Devicetree as a source of hardware
description/initial configuration.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Remove description from SOC_FAMILY_SMARTBOND so it's not directly
selectable. Also fix related board configuration.
Fixes#49916
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
As of today <zephyr/zephyr.h> is 100% equivalent to <zephyr/kernel.h>.
This patch proposes to then include <zephyr/kernel.h> instead of
<zephyr/zephyr.h> since it is more clear that you are including the
Kernel APIs and (probably) nothing else. <zephyr/zephyr.h> sounds like a
catch-all header that may be confusing. Most applications need to
include a bunch of other things to compile, e.g. driver headers or
subsystem headers like BT, logging, etc.
The idea of a catch-all header in Zephyr is probably not feasible
anyway. Reason is that Zephyr is not a library, like it could be for
example `libpython`. Zephyr provides many utilities nowadays: a kernel,
drivers, subsystems, etc and things will likely grow. A catch-all header
would be massive, difficult to keep up-to-date. It is also likely that
an application will only build a small subset. Note that subsystem-level
headers may use a catch-all approach to make things easier, though.
NOTE: This patch is **NOT** removing the header, just removing its usage
in-tree. I'd advocate for its deprecation (add a #warning on it), but I
understand many people will have concerns.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Similarly to other drivers, use auto generated DT_HAS_<COMPAT> Kconfig
symbol to control use of STM32 lptim driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Added code to enable platform specific Virtual Wire GPIOs. With this
change, able to send the USB-C overcurrent Virtual Wire event to
Meterolake SOC.
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
According to RM the daisy chain mask should include both bit 0 and 1, not
only bit 0.
Updated bitmask accordingly
Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
There are two external clocks driving i.MX RT 10xx SoCs: XTAL and
RTC_XTAL. Add "fixed-clock" DT nodes for each. Update also "nxp,imx-ccm"
binding, so that CCM (Clock Control Module) peripheral consumes those
clocks by "xtal" and "rtc-xtal" names.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
The STM32G070 and STM32G0B0 Socs don't have USB power delivery support
but the PINs PD0, PD2, PB15, PA8 pins of these still have the same
pull down on boot configuration options as the SOCs with UCPD support.
This commit skips the check if such a peripheral is enabled,
therefore the configuration will always be applied on these SOCs
and the compile error is resolved.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
On STM32U5 series, when an image is build with mcuboot,
image starts at offset 0x400 instead of default 0x200.
This should be taken into account when calling imgtool by using
dedicated option to set header-size value.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Now that interrupt controller drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
This allows to disable UART peripheral driver and still be able to build
correctly (header is not visible when LPUART driver is not enabled).
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
So far systick frequency was duplicated in 'sysclk' DT nodelabel's
'clock-frequency' property and in per SoC SYS_CLOCK_HW_CYCLES_PER_SEC
default value. Set the latter based on DT configuration.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
This adds initial support for Renesas SmartBond(tm) DA1469x series SoC.
Initailly only DA14699 is explicitly supported, however this code should
also run on other SoCs in this series since all of them support the same
core features available initially.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
This has been moved to the NXP HAL layer so that all
SDK NonCacheable symbols get placed in the nocache
region
Also pull in the HAL changes associated with this
change.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit replaces API that became deprecated with the release
of nrfx2.9 - see CHANGELOG in zephyrproject-rtos:hal_nordic repository
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
Now that crypto drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
Similar to pinctrl, almost all device drivers will depend on the reset
controller being available, so default the driver class to y at SoC
level.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Now that DMA drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
Replaced hand coded use with DT_STRING_UPPER_TOKEN_BY_IDX. We should have
introduced the APIs when this was needed since the token values in
devicetree_generated.h should only be accessed via an API macro.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that I2S drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
This commit enables the SoC's flash memory controller.
- added lpc55s36 specific code in the NXP MCUX driver
to take advantage of the SoC's check-before-read
capability
- enabled the FMC node in the SoC's dtsi (iap)
- added the flash controller chosen node to the board's dts
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Now that usb device drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
Set the default value for SYS_CLOCK_HW_CYCLES_PER_SEC based on DT cpu0
clock-frequency property.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Set the default value for SYS_CLOCK_HW_CYCLES_PER_SEC based on DT cpu0
clock-frequency property.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
USB SRAM region was accidentally deleted by an earlier
commit. Rename the memory region used by USB to USB_SRAM instead
of SRAM4. SRAM4 was the wrong name for this region.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
It includes the definition for the DMA peripheral of this type,
present on stm32U5 devices.
A particular DMA_STM32U5 config is selected for that purpose.
The driver is derived from the existing dma_stm32.c
The GPDMA is counting channels (0-15) ; stream offset is 0.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The low power mode logic for i.MX RT1064 indirectly includes the HAL
definitions, but this is fragile and depends on specific Kconfig options.
This fixes build issues if for example CONFIG_ARM_MPU is not set.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Attached the correct clock frequency for
FlexComm15 which connects to the PMIC_I2C peripheral
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Many device pointers are initialized at compile and never changed. This
means that the device pointer can be constified (immutable).
Automated using:
```
perl -i -pe 's/const struct device \*(?!const)(.*)= DEVICE/const struct
device *const $1= DEVICE/g' **/*.c
```
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Remove the static MMU entries for each available Xilinx PS UART
instance. Those are no longer required now that the PS UART
driver uses the DEVICE_MMIO API for register space mapping.
Signed-off-by: Immo Birnbaum <immo.birnbaum@weidmueller.com>
Increase the default user-allocable number of RTC channels to meet
the nrf_802154 driver requirements.
Signed-off-by: Adam Zelik <adam.zelik@nordicsemi.no>
1. Update soc.c file to add USB clock setup
2. Add a linker file to move USB transfer
buffer and controller buffers to USB RAM
3. Update Kconfig's to add USB support
4. Add zephyr_udc0 nodelabel
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The names of these peripherals in the device tree
did not match the Reference Manual for the RT600.
Added alias for usdhc0 to be able to use SDHC test.
Also fixed a typo in a comment referring to USDHC which should have been
about USB.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Now that peci drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that ethernet drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
Currently the USB-C PD dead battery support is disabled very early in
the boot process, in order to give access to CC1 and CC2 pins to the
application. However this breaks dead battery support as this instructs
the PD source to stop delivering power.
This commit changes the behavour to keep the internal pull-up in dead
battery pins enable if the UCPD driver is enabled, and the corresponding
UCPD peripheral is also enabled. The code is a bit complex as it aims to
support possible G0 devices with a single UCPD controller (as opposed to
the current one), and also because I haven't found any simple way to
match the UCPD peripheral with the bits in the SYSCFG_CFGR1 register (I
used the same trick with the base address as in the driver).
Given I have not been able to get that working with macros, the check is
done at "runtime", however GCC is smart enough to optimize the code. The
generated code is identical if none of the UCPD peripheral is enabled.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
add the MMU page table entries for all instances of the Xilinx AXI GPIO
controller IP core. Other than any Zynq-7000 peripheral supported so far,
the existance of 1..n instances of the IP core within the FPGA part of the
SoC is optional. Therefore, other than addressing instances of supported
peripherals using their DT node label as has always been the case so far,
the data for the MMU page table is added using the DT_FOREACH_STATUS_OKAY
macro.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
The use of the RT11xx CAAM requires
cache write-through mode,
otherwise some tests give a compiler warning.
Add to the soc CMake to do this
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Now that sdhc drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
The macro INPUTMUX_PINTSEL_COUNT is name INPUTMUX_PINT_SEL_COUNT
on certain SoC's in the SDK.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
There are several test cases that create fake ethernet devices and
expect the fake device to be the only ethernet device enabled. Some
tests handle this be explicitly disabling actual ethernet drivers,
but this doesn't scale well.
Change drivers/ethernet/Kconfig to utilze a menuconfig option that
wraps all the drivers. This allows us for those test cases that
don't want any actual ethernet drivers to disable them with a
simple CONFIG_ETH_DRIVER=n.
Note, the fake ethernet devices utilize CONFIG_ETH_INIT_PRIORITY so
we have it outside of the 'if ETH_DRIVER' block.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that counter drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
Remove NET_CONFIG_IEEE802154_DEV_NAME in favor of DT based choice using
zephyr,ieee802154.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Have the kscan device enabled in devicetree will now get the driver
enabled by default when CONFIG_KSCAN=y is set. So we can remove
driver enabling Kconfig values in various Kconfig.defconfig files.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that entropy drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
Have the display enabled in devicetree will now get the driver
enabled by default when CONFIG_DISPLAY=y is set. So we can remove
setting driver enabling Kconfig values in various .conf and
defconfig files.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that flash drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
All IEEE 802.15.4 drivers are now automatically enabled if they are
'okay' in DT and all of its dependencies are 'y', including
CONFIG_IEEE802154. This means individual driver enablement is not
necessary anymore in Kconfig.defconfig files or samples/tests. Boards
need to still make sure any dependencies are enabled, e.g. SPI bus in
some cases.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
COUNTER_RTC_STM32 used to be enabled directly based on COUNTER status.
This should not be the case anymore as we should first check
DT_HAS_ST_STM32_RTC_ENABLED status (which is already done in
drivers/counter/Kconfig.stm32_rtc).
Remove these 3 lines that are not correct anymore.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This is temporary until support has been enabled. lpc55s36's IAP controller
is different and does not match previous implementations.
The Zephyr driver uses a data structure matching the IAP controller to
implement a feature that should normally come out of the ROM.
Since IAP support is not in yet, disabling the option in the SoC's Kconfig
and disabling the node in the device tree is the proper way to go forward.
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
LPC55s3x family has an additional analog mode bit available. Update
IOCON binding and IOCON driver to support setting this bit via a pin
control property.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Now that CAN drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the CAN.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Use Devicetree to describe the radio and IEEE 802.15.4. This allows to
remove usage of IEEE802154_NRF5_DRV_NAME in preparation for the
removal of NET_CONFIG_IEEE802154_DEV_NAME.
All SoC files have been updated with the addition of an ieee802154 node
(disabled and only on those SoCs that define ieee802154-supported. The
peripheral has been enabled in the nRF52840DK board (used for testing
ieee802154).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use Devicetree to describe the radio and IEEE 802.15.4. This allows to
remove usage of IEEE802154_KW41Z_DRV_NAME in preparation for the removal
of NET_CONFIG_IEEE802154_DEV_NAME.
KW41Z files have been updated with the addition of radio and an
ieee802154 nodes The peripheral has been enabled in the frdm_k41z board
(used for testing ieee802154).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use Devicetree to describe the radio and IEEE 802.15.4. This allows to
remove usage of IEEE802154_CC13XX_CC26XX_DRV_NAME in preparation for the
removal of NET_CONFIG_IEEE802154_DEV_NAME. All boards used in testing
have been updated to enable the peripheral in DT as well.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Now that watchdog drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
watchdog and not respect the devicetree state of the watchdog.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that DAC drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the DAC.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that ADC drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the ADC.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Add the "zephyr/" prefix to various #include statements that are
preventing the CI form running with LEGACY_INCLUDE_PATH=n.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The HAS_I2C_DW was to limit Kconfig visibility to only platforms
that utilize the I2C DW IP. The Kconfig for I2C_DW depends on
DT_HAS_SNPS_DESIGNWARE_I2C_ENABLED which will cause the same
visbility limitation to only platforms that have I2C DW devicetree
nodes. Thus we can remove HAS_I2C_DW and its references.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that I2C drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the I2C.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that clock control drivers are enabled based on devicetree we
need to remove any cases of them getting enabled by Kconfig.defconfig*
files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a sensor and not
respect the devicetree state of the clock control. Additionally we
can get problems with prj.conf/defconfig getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that PWM drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the PWM.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that SPI drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the SPI.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that serial drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the serial.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that gpio drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the GPIO.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that sensor drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the sensor.
Additionally we can get problems with prj.conf/defconfig
as well getting incorrectly overridden.
Fixes#48198
Signed-off-by: Kumar Gala <galak@kernel.org>
This CL adds a DT node, 'power_leakage_io', which property,
'leak-gpios', contains GPIOs that have leakage current. In oerder to get
better power consumption, npcx power driver will disable the connections
between these io pads and input buffers before entering deep sleep.
Then, restore the connections after ec wakes up.
The users can overwrite this property at board DT file. Here is an
example:
&power_leakage_io {
leak-gpios = <&gpio0 0 0
&gpiob 1 0>;
};
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL configures low-voltage (1.8V) detection via GPIO driver with
GPIO_VOLTAGE_1P8 flag. It also adds support for this flag in
pin_get_config() function.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Cleanup npcx low-voltage (1.8V) detection configuration. It removes
unused soc utilities, macros, and DT node. We will configure this
feature by GPIO driver with GPIO_VOLTAGE_1P8 flag later.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The driver has be DT_INST based for a while so the Kconfig
symbols CONFIG_UART_PL011_PORT0<n> aren't used. So lets
remove them.
Signed-off-by: Kumar Gala <galak@kernel.org>
MISRA C:2012 Rule 14.4 (The controlling expression of an if statement
and the controlling expression of an iteration-statement shall have
essentially Boolean type.)
Use `do { ... } while (false)' instead of `do { ... } while (0)'.
This commit is a subset of the original commit:
5d02614e34a86b549c7707d3d9f0984bc3a5f22a
Signed-off-by: Simon Hein <SHein@baumer.com>
Any project with Kconfig option CONFIG_LEGACY_INCLUDE_PATH set to n
couldn't be built because some files were missing zephyr/ prefix in
includes
Re-run the migrate_includes.py script to fix all legacy include paths
Signed-off-by: Tomislav Milkovic <milkovic@byte-lab.com>
Include linker sections header to move z_arm_platform_init to text
section. It is now is placed in the TEXT section.
Signed-off-by: Bernard Lee <bernard.lee@nordicsemi.no>
For SAML21-based parts, the REFCTRL register is locked while the ADC is
enabled. Permit some parts to declare that they need the ADC to be
disabled before modifying REFCTRL.
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Implement support for SAMR34 and SAMR35 parts, tested on a SAMR34
Xplained Pro dev board. Confirmed operational peripherals: UART, GPIO,
PWM, ADC.
NOTE: The SAMR34 datasheet lists NVIC line 20 for the ADC's interrupt,
but the SAML21 datasheet gives line 22. It appears that the SAMR34 sheet
is incorrect (the ADC doesn't function with line 20), and as such, I have
also omitted the adjustments for TC4 and AC...
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Implement support for SAML21 parts, tested on a SAML21 Xplained Pro dev
board. Confirmed operational peripherals: UART, GPIO, PWM, ADC.
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Clean up unused psl functions in scfg.c, unused DT macros, unused psl DT
nodes and related yaml files. Currently, PSL pad configurations are made
by pinctrl mechanism. Please refer
https://issuetracker.google.com/234861079 for more detail.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
irq_lock() returns an unsigned integer key.
Generated by spatch using semantic patch
scripts/coccinelle/irq_lock.cocci
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Clean up unused pinmux function 'npcx_pinctrl_mux_configure()' and
related 'NPCX_DT_IO_ALT*' macro functions.
Please refer https://issuetracker.google.com/234861079 for more detail.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Fix build error if CONFIG_PM and CONFIG_INIT_VIDEO_PLL are enabled.
Added 2 missing semicolons.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Add static MPU regions for this SoC.
These regions will be initialized as static region during system boot.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
This adds a new stm32f412Rx in the list of stm32F4 devices.
The module stm32cube/stm32f4/soc/stm32f412rx.h exists
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This CL introduces how to configure PSL (Power Switch Logic) pads
properties such as input detection mode/polarity, pin-muxing and so
on via pinctrl mechanism. It includes:
1. Add two pinctrl properties and their enums for PSL input
detection configuration.
psl-in-mode:
- "level"
- "mode"
psl-in-pole:
- "low-falling"
- "high-rising"
2. Add macro functions to get PSL input detection and pin-muxing
configurations from 'pinmux', 'psl-offset' abd 'psl-polarity'
properties.
Here is an example to configure PSL_IN2 as the PSL detection input and
its mode and polarity.
/* A falling edge detection type for PSL_IN2 */
&psl_in2_gp00 {
psl-in-mode = "edge";
psl-in-pol = "low-falling";
};
A device will be introduced later which uses this pinctrl node to
configure PSL input detection settings and how to turn off VCC1 power
rail by PSL_OUT.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Following zephyr's style guideline, all if statements, including single
line statements shall have braces.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Select HAS_MCUX_XBARA Kconfig symbol for MIMXRT1062,
since the XBARA Inter-Peripheral Crossbar Switch peripheral is present
on this SOC.
Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
Added mchp mec zephyr image generator python script. It takes
zephyr.bin as input and produces zephyr.mchp.bin.
The default behavior is to not pad to SPI flash size.
(Enable through CONFIG_MCHP_MEC_UNSIGNED_HEADER=y and
CONFIG_MCHP_MEC_HEADER_FLASH_SIZE_256K=y)
zephyr.mchp.bin is composed of:
1. First 4KB contains TAG at offset 0 and header at offset 0x100
2. Offset 0x1000 is the start of zephyr.bin which has been padded
to a multiple of 128 bytes.
3. Boot-ROM EC Info Block (128 bytes)
4. Boot-ROM Co-Signature Block (96 bytes)
5. Boot-ROM trailer (160 bytes) contains the SHA-384 digest of 2-4.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
enable swo output for iMX RT 10xx series. SWO pinmux settings are
currently only present for the RT1060 and RT1064
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Default to 1 CPU core on the Xilinx Zynq-7000 SoC series since Zephyr does
not yet suppport SMP on aarch32.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add Xilinx Zynq-70000 pinctrl header file to define SoC specific
pinctrl_soc_t structure. This is used to store pin configurations for the
pinctrl driver.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Unlock the Xilinx Zynq-7000 System Level Control Registers (SLCR) at boot
to allow write access using the generic syscon driver.
Since the generic syscon driver uses the DEVICE_MMIO_* APIs for
memory-mapped IO we can remove the dedicated SLCR MMU region.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
When using CONFIG_NPCX_IMAGE_OUTPUT_HEX, set the hex_file
runners_yaml_props_target property, so that west flash will flash the
correct file.
Change the cmake flash rules to populate the hex_file value in the
runners.yaml file if either CONFIG_BUILD_OUTPUT_HEX is enabled or some
cmake file set the runners_yaml_props_target hex_file property.
Update the npcx9m6f_evb instructions now that the filename is implicit.
Signed-off-by: Jeremy Bettis <jbettis@google.com>
Select missing HAS_MCUX_SRC Kconfig symbol for MIMXRT1062,
that allows using NXP i.MX mcux SRC hwinfo driver.
Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
Commit b91d21d32c added the possibility to define MPU regions from the
device tree, however commit c276088567 removed that possibility for H7
SoC, as it now uses a SoC specific definition of the MPU regions without
the DT-defined regions (probably because the two PRs got developped in
parallel).
Fix that by adding the macro which adds the DT-defined regions to the
STM32H7 specific file.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
- The MX25UM51345G flash is connected to FLEXSPI PortA for
mimxrt595_evk.
- Updated flexspi_mx25um51345g driver to support DTR OPI mode.
- Tested with tests/drivers/flash.
Signed-off-by: Chay Guo <changyi.guo@nxp.com>
Add watchdog support to the mimxrt595 platform.
The mimxrt595 platform is excluded from the watchdog
test case because the test case uses variables in the
noinit section that need to be retained through a reset
but the rt595 does not retain this memory through a
reset.
Signed-off-by: Chay Guo <changyi.guo@nxp.com>
Enable access to the HS_SPI pins(JP26) on the mimxrt595_evk board.
Using DMA mode, tested with spi_loopback testcase.
Signed-off-by: Chay Guo <changyi.guo@nxp.com>
Enable I2C access to FXOS7000 sensor on the mixrt595_evk board
Tested using samples/sensor/fxos8700 for mimxrt595_evk_cm33.
Signed-off-by: Chay Guo <changyi.guo@nxp.com>
Select HAS_MCUX_ADC_ETC Kconfig symbol for MIMXRT1062,
since the ADC External Trigger Control eripheral is present
on this SOC.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
Aspeed AST10x0 series SOC has a SYSCON hardware block at address
0x7e6e2000. Enable this option to enable relative driver.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
This PR adds a soft off mode to the RT10xx Power Management API.
Additionally, it corrects the PM API function in rt10xx_power.c to
use the correct function prototype to be properly overridden.
Signed-off-by: Nickolas Lapp <nickolaslapp@gmail.com>
There was a confusion on MB_MEMx definitions. Both MB_MEM1/2
should be located in SRAM1. Fix this.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Adds few missing zephyr/ prefixes to leftover #include statements that
either got added recently or were using double quote format.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The current sam0 adc driver not implement correctly the adc_reference
enum values. This try homonize adc input referece by tracking VDDANA
at ADC_REF_VDD_1. The ADC_REF_VDD_1_2 were fixed with correct INTVCCx
channel selection.
Fixes#45443
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The stm32f7 (like stm32H7) should be able to disable
the Dcache when using the DMA. This is to avoid any
pb of cache coherency on the DMA buffers.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit adds a call to the Colorama initialisation function during
the module execution so that ANSI color sequences are properly
converted to the relevant Win32 API calls on the Windows.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Up till now the usage of CONFIG_NOCACHE_MEMORY also explicitly disables
data cache on the STM32H7 SoC.
With this change the usage of CONFIG_NOCACHE_MEMORY has been decoupled
from data cache enabling as new Kconfig option - namely
CONFIG_DCACHE is now used to explicitly enable it.
After this change it would be possible to use data cache on STM32H7
with DMA buffers, fragile to cache coherency issues, defined with
'__nocache' attribute.
Such approach would improve the overall STM32H7 performance until the
moment when proper (i.e. in-DMA) buffer cache management is developed.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Config pwm open-drain mode without enabling STORE_REG. This CL
collects all active PWM's base address and related index in an
array. Then, pinctrl driver configs its open-drain mode by
finding the corresponding 'channel' index.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Set SYS_CLOCK_TICKS_PER_SEC to 128 for non-tickless kernel.
Previously it was set to 32768 disregarding kernel mode and that
lead to too frequent interrupts in non-tickless mode (tick every
30 us). Change to smaller value.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
The GigaDevice HAL defines CAN_MODE_NORMAL, which conflicts with the
zephyr/drivers/can.h header definition. Undefine it in soc.h.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Updated PSoC 6 implementation to use hal_infineon/mtb-pdl-cat1
This PR is reflected changes according to Task#1 for RFC#42883.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
On STM32WB and dual-core STM32H7 MCUs, the RNG peripheral is shared
between the cores and its access is protected by a hardware semaphore.
Locking was not performed in the current entropy driver, leading to a
race condition when multiple cores concurrently used the RNG. This
commit implements the necessary logic for locking the HSEM during entropy
generation on multi-core STM32 MCUs. It also reconfigures the RNG in case
the configuration was changed by the other core, as this can happen e.g
on STM32WB MCUs.
Signed-off-by: Thomas Altenbach <taltenbach@witekio.com>
Add pin control support for IOMUXC peripheral present
on mimx8ml8_m7 soc. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a
new header and compatible binding to handle the
different register layout on this SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for IOMUXC peripheral present
on mimx8mq6_m4 soc. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a
new header and compatible binding to handle the
different register layout on this SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for mcimx7_m4 SOC. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a new header and
compatible binding to handle the different register layout on this SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for mcimx6x. The IOMUXC peripheral present on
this SOC is identical to the one used on the iMX RT10xx series, so the
dts bindings are reused.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Refactor iMX RT pin control support to use more generic names, as the
IOMUXC peripheral is present on non RT iMX application cores.
Additionally, make selection of the pin control driver occur at the SOC
level.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This CL is the initial version for npcx pinctrl driver and introduces
pinctrl nodes for both IO-pads and peripheral devices for each npcx
series. Users can set pin configuration via these nodes in the board
layout DT file. It also wraps all configurations related to pin-muxing
in pinctrl_soc.h. Regarding the other pin properties, we will implement
them later.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The drive-mode property is nRF specific, so prefix it with `nordic,`,
same as the `nordic,invert` property.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Enabling an eSPI channel (r.g. Peripheral Channel, Virtual Wire Channel,
etc.) during an eSPI transaction might (with low probability) cause the
eSPI_SIF module to transition to a wrong state and therefore response
with FATAL_ERROR on an incoming transaction.
This CL workarounds this issue by clearing the bit 4 of NPCX eSPI
specific register#2.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Convert the can_mode enum to a bit field to prepare for future extensions
(CAN-FD mode, transmitter delay compensation, one-shot mode, 3-samples
mode, ...).
Rename the existing modes:
- CAN_NORMAL_MODE -> CAN_MODE_NORMAL
- CAN_SILENT_MODE -> CAN_MODE_LISTENONLY
- CAN_LOOPBACK_MODE -> CAN_MODE_LOOPBACK
These mode names align with the Linux naming for CAN control modes.
The old CAN_SILENT_LOOPBACK_MODE can be set with the bitmask
(CAN_MODE_LISTENONLY | CAN_MODE_LOOPBACK).
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Enable pin control for lpc11u6x soc by selecting CONFIG_PINCTRL=y.
At this time no drivers are ported.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
soc: arm: privilege: add Cyclone V SoC FPGA suppport
Add support for the Intel Cyclone V SoC FPGA (arm Cortex-A9).
Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
This is a follow-up to commit 586e26e8fc.
Add missing `qdec0` node labels in definitions of SoCs that have only
one QDEC instance so that the `HAS_HW_NRF_QDEC0` option is properly set
for them. Use the same pattern as in the WDT case and keep the existing
`qdec` labels for backward compatibility.
Also update validation of base addresses so that both QDEC0/QDEC and
QDEC1 are checked.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
ADC threshold control register offset is provided by devicetree, this
change will add this property into `adc_npcx_config` structure and
update macro to access register accordingly. Driver behavior is not
meant to be impacted.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
The pm hooks for this target were not updated to follow the current API.
These weak functions will never be called for the pm subsystem.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Assembler files were not migrated with the new <zephyr/...> prefix.
Note that the conversion has been scripted, refer to #45388 for more
details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Linker files were not migrated with the new <zephyr/...> prefix. Note
that the conversion has been scripted, refer to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Enable the UTMI PLL (UPLL) clock and add a static definition of its clock
frequency.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
Enable the UTMI PLL (UPLL) clock and add a static definition of its clock
frequency.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
In order to bring consistency in-tree, migrate all soc code to the
new prefix <zephyr/...>. Note that the conversion has been scripted,
refer to zephyrproject-rtos#45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This reverts commit 91d4b7766c.
Zephyr SDK 0.14.1 now includes QEMU 6.2, which supports the emulation
of the MVE instructions.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Update the Microchip XEC PS2 driver to support MEC172x.
NOTE: MEC15xx has two PS2 controllers and
MEC172x has one.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
add pincontrol headers for IOCON peripheral present on NXP iMX RT600
and RT500 SOCs, and update LPC pin control driver for iMX RT family
differences.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
added support for NXP iMX RT600/RT500 to use to SDHC driver, with SD
subsystem. Tested with RT685 EVK
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable new USDHC driver for all RT10xx boards, since those will have
the SDHC driver selected by Kconfig
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
In c5b59282d6, Kconfig option
CPU_CORTEX_M_HAS_CACHE was added only to a subset of stm32h7 soc
descriptions.
There is no reason not to extend to all socs as they all actually
feature a cache.
Fixes#45073
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
We no longer need to relocate the SDK power management
source file to SRAM. Instead specific functions from the
SDK file are relocated to the ramfunc section.
This commit fixes Issue#44670
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
If a Zephyr binary is booted on the Zynq-7000 not via JTAG download,
but via u-boot's ELF boot function instead, Zephyr will have to revert
certain changes made by u-boot in order to boot properly:
- clear the ICache/DCache enable, branch prediction enable and
strict alignment enforcement enable bits in the SCTLR register.
By default, u-boot will also set up the MMU prior to Zephyr
doing so as well, this can be avoided by changing the u-boot
build configuration. Therefore, the MMU enable bit is not changed
at this point.
- set the VBAR register to 0. U-boot moves the interrupt vector
table to a non-standard location using the VBAR register (no
change is made by u-boot for SCTLR.V, only VBAR is changed
to a non-zero memory location).
Without these changes, Zephyr will crash upon the first context
switch at latest, when SVC is invoked and u-boot's vector table
is used rather than the vectors copied to address zero by Zephyr.
In order to perform these changes before coming anwhere near the
MMU / device driver / kernel initialization stages or even the
first context switch, the z_arm_platform_init hook is used, which
is now enabled for the Zynq via the Kconfig.defconfig file.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
pin control definitions present for LPC55xx are not generic to all LPC
IOCON controllers. Make pin control header file LPC55xx specific.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
all the consumers of the obsolete pinmux driver is
updated to use pinctrl API, this commit removes
the pinmux driver and assosciated sections.
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
Add pinctrl driver for CC13XX/CC26XX family of SoCs
to facilitate transition from pinmux to pinctrl.
`IOCPortConfigureSet()` from TI hal driverlib used to
implement the generic pinctrl driver.
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
The Cache is an optional configuration of both the ARM Cortex-M7 and
Cortex-M55. Previously, it was just checking that it was just an M7
rather than knowing that the CPU actually was built with the cache.
Signed-off-by: Ryan McClelland <ryanmcclelland@fb.com>
Zephyr kernel will always execute WFI in k_cpu_idle(), so access to TCM
will be gated. Keep the AHB clock enabled in sleep unless CONFIG_PM is
selected, to avoid this error.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add MPU REGION_FLASH_SIZE definitions for 128M-512M flash sizes, to handle
arm SOCs with large flash regions.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
When we use a third-party or custom bootloader, there is also
need to remove the boot header. Change the select to imply,
so that the boot header can be removed by configuration when
MCUBoot is not used.
Signed-off-by: Frank Li <lgl88911@163.com>
DBGMCU register, which is used for SWO pin configuration,
may not have TRACE_MODE bits in some STM32 MCUs.
Replace register access with LL functions selected based on SoC family.
Fixes#44584
Signed-off-by: Alexander Vasiliev <alex.m.vasil@gmail.com>
Due to a wide range of variuation in the LSI RC oscillator
characteristics given by the datasheet of the soc,
It is necessary to add a delay for hardware watchdog.
This is done by the CONFIG_TASK_WDT_HW_FALLBACK_DELAY
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add soc_secure_mem_read implementation for secure.
This simplifies users code so that ifdefs are not required.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
The limitation on HWINFO_NRF depending on not nonsecure was removed in
52be3030aa.
This caused problems when TF-M was not enabled.
This happens on the thingy53_nrf5340_cpuapp_ns board since this board
is not supported by TF-M.
Introduce proper dependency handling for the soc secure functions
to make HWINFO_NRF unavailable when no secure services exist in
nonsecure.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Add pinctrl definition header, to parse pinctrl groups in board level
DTS into pinctrl_soc_pin_t values.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The autoconf.h header is not required because the definitions present in
the file are exposed using the compiler `-imacros` flag.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Currently the only way for a BOARD/SOC to configure at compile time the
MPU regions is to add, in a soc-specific file, the 'mpu_config' struct
adding static entries for the new regions with the needed attributes
(cacheable, non-cacheable, etc...). This exported struct is then read by
the MPU driver at boot time and used to properly setup the MPU regions.
At the same time it is now possible to introduce new memory regions in
the DT using the newly introduced 'zephyr,memory-region' attribute.
What is missing is the link between these two solutions: that is how to
declare the memory regions in the DT and automatically configure these
regions in the MPU with the correct attributes.
This patch is trying to address exactly this problem.
It is now possible to declare the memory regions in the DT and define
the MPU attributes for the regions using the 'zephyr,memory-region-mpu'
property. When this new property is present together with the
'zephyr,memory-region' property and a the 'zephyr,memory-region'
compatible, the 'mpu_config' struct is automatically extended at
compile-time to host the DT defined regions with the correct MPU
attributes.
So for example in the DT we can now have:
sram_cache: memory@20200000 {
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20200000 0x100000>;
zephyr,memory-region = "SRAM_CACHE";
zephyr,memory-region-mpu = "RAM";
};
and a new region will be created called "SRAM_CACHE" and a new MPU
region will be configure at boot time with the attribute
"REGION_RAM_ATTR".
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add soc_secure_read_deviceid function for reading the device ID from
FICR when executing in non-secure processing environment.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Refactor soc_secure handling to not use TF-M directly in the header.
Move from nRF53 to common since nRF91 also supports TF-M.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Instead of selecting appropriate HAS_HW_NRF_* options for particular
nRF SoCs (and simulated nRF52 target), set their values basing on
information from devicetree.
Correct also semantics of those options so that they are set only when
a corresponding DT node is enabled. This allows using them directly in
Kconfig dependencies of Zephyr drivers for nRF peripherals. Update
appropriately these dependencies.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add missing devicetree nodes representing the following peripherals
in nRF SoCs:
- ACL
- BPROT
- CCM
- COMP/LPCOMP
- CTRLAP
- DCNF
- MPU (nRF MPU peripheral in nRF51 Series, not ARM MPU)
- MUTEX
- MWU
- NFCT
- OSCILLATORS
- POWER (in nRF51 and nRF52 Series)
- PPI
- RESET
- SWI
- USBREG
Add also corresponding bindings and validation of base addresses of
these nodes.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The NXP SDK defines CodeQuickAccess and DataQuickAccess sections
for locating critical items that need faster access. Centralize
the handling of these sections instead of doing it per SOC.
Fixes#44453
Signed-off-by: David Leach <david.leach@nxp.com>
Correct eSPI flash macro so it not always results in zero,
leading to eSPI flash read operation in all cases:
Read, write, erase.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Added support for 8 MB MPU regions for SRAM sizes between 4 and 8 MB,
and 16 MB MPU regions for SRAM sizes between 8 and 16 MB.
Signed-off-by: Johan Öhman <johan.ohman@softube.com>
Enabled the Shared Memory Reset feature for nRF5340 Application Core
when the RPMsg backend for IPC Service is enabled.
Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>
Based on introduction of plain GPIO configurations in STM32 pinctrl
bindings, update STM32 pinctrl/gpio drivers to make this functionality
available.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Some pinctrl related definitions are still defined
in pinmux related files.
Duplicate definitions to prepare pinmux removal.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
All iMX RT 1xxx boards are now expected to use pin control, so the USDHC
pinmuxing callbacks can be removed.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable soc ethernet ref clock output at the SOC level instead of board
level, since it is required for all iMX.RT SOCs
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
RT11xx series has similar pin configuration peripheral to RT10xx, with
some differences in register layout. Create new pinctrl definition
header file, and reuse existing driver code for RT10xx.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
iMX.RT parts use a GPR register for some pinmux settings. Update pinctrl
driver to support this GPR register definition.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
OCRAM can be used for DMA, and in this case it should be marked as
noncacheable. Add KConfig symbol and appropriate linker scripts to
enable OCRAM region to be defined as noncacheable, and initialized with
data from flash at boot.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This update current Atmel sam0 pinctrl initiative to current Zephyr
pinctrl API. It update current devicetree bindings and add the sam0
pinctrl driver.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update current Atmel sam pinctrl initiative to current Zephyr
pinctrl API. It update current devicetree bindings and add the sam
pinctrl driver.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
In npcx adc driver, we select 'Scan' (Multiple Channels Operation Mode)
mode by default. It means that selected channels in ADCCS will be
converted automatically. Then, read the measured data from CHNDAT
registers if EOCCEV (Event is set after all selected channels are
converted.) flag in ADCSTS is set.
But we enable the wrong interrupt type, INTECEN, during adc
initialization. Ec will send the interrupt after each channel in ADCCS
is converted. It has no harm to the current driver since the driver
reads all selected channels and turns off ADC converter only after
EOCCEV is set in ISR. But it does generate spurious interrupts.
This CL enables the correct interrupt type, INTECCEN, during adc
initialization. Ec only sends the interrupt after all of channels in
ADCCS are converted.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This is required to include the resource table in the build output. The
Linux remoteproc framework explicitly looks for this section while loading
the elf and may complain if the resource table is missing.
Signed-off-by: Matthias Fend <matthias.fend@emfend.at>
Aspeed ast10x0 series SoCs contain a ARM Cortex-M4F processor. This
processor operates at 200MHz and executes on SRAM.
This patch adds support for ast1030 as the first SoC of this series
which is targeted but not limited at the bridge IC in a server system.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I668af1ff8a36a05da791c3329ae08f5ae712bdd4
KW24 and KW22 series support open drain pins, while rest of kinetis KW
SOCs do not. Don't redefine PORT_PCR_ODE for these SOCs
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Extend the macro with checks for DT properties related to pin
assignments that are defined but would be ignored, depending on
whether PINCTRL is enabled or not, what presumably indicates
a resulting configuration different from what the user expects.
Add also a possibility to indicate that the pinctrl-1 property
should not be checked because the caller does not support the
sleep state.
Rename the macro so that its name better reflects its function.
Update accordingly all drivers that use it.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add Kconfig items that can be used to query if the current SoC
support the HW peripheral CTRLAP.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
The pm_constraint_* APIs were effectively used by the policy manager
only. This patch renames the API to the policy namespace and makes its
naming more explicit:
- pm_constraint_set -> pm_policy_state_lock_get()
- pm_constraint_release -> pm_policy_state_lock_put()
- pm_constraint_get -> pm_policy_state_lock_is_active()
The reason for these changes is that constraints can be of many types:
allow/disallow states, impose latency requirements, etc. The new naming
also makes explicit that the API calls will influence the PM policy
behavior.
All drivers and documentation have been updated accordingly.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add support for configuring pins to be used by the nRF PWM, QDEC, and
QSPI peripherals.
A new custom property "nordic,invert" is added to the pin configuration
group binding to allow configuring PWM channel outputs as inverted.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add a 4k indentity mapping in the MMU for the Processor System GPIO
controller if the parent device node is enabled in the device tree.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
USB pll clock should be enabled if USB driver is used. Add required
configuration for USB pll clock.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This is mostly the same than the aarch64 one, excepted that we
force the armv8r fvp to run in aarch32 profile. So that we can simulate
the Cortex-R52.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
According to Kconfig guidelines, boolean prompts must not start with
"Enable...". The following command has been used to automate the changes
in this patch:
sed -i "s/bool \"[Ee]nables\? \(\w\)/bool \"\U\1/g" **/Kconfig*
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add build assertions that will ensure that every peripheral for
which a driver instance is created has some pins assigned to it.
Neither pinctrl-0 nor *-pin properties can be currently marked as
required in devicetree, so these assertions will help users avoid
invalid configurations where it could be hard to figure out why
the UART is not working.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
nRF5340 application core should not attempt to pass control over any
pins to the nRF5340 network core if the latter is disabled.
This commit fixes https://github.com/zephyrproject-rtos/zephyr/issues/43476.
Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
Enables low power clocks for mimxrt1064. This allows the soc to
transition into very low power states during idle, as most PLLs can be
disabled. Power states need to be enabled and selected at the board
level.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add power management code for the RT10xx SOC. By default, the code will
simply gate the core clock and transition the SOC to WAIT mode when
sleeping, but if clocking hooks are register to reduce clock frequencies
these will be called as well, and the SOC core voltage will be lowered
for additional power savings.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add KConfig symbols to select power management HAL drivers required for low
power modes. Set ZTEST_NO_YEILD if PM is enabled, since RT series SOCs
do not connect to a debugger in WAIT mode.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The NXP KE1xF SoC series does not support neither slew rate nor open
drain PORT configuration registers.
Fix pinctrl compilation for the KE1xF by defining dummy register macros
for the SRE and ODE registers.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Remove a redundant symbol that was used as a proxy to enable CONFIG_PM.
If an application needs to enable PM, it should just enable PM subsystem
Kconfig options. Furthermore, there's no clue "SOC_POWER_MANAGEMENT" is
a Microchip specific option.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Rename CONFIG_SOC_POWER_MANAGEMENT_TRACE to CONFIG_NPCX_PM_TRACE so that
it is clear that it's a NPCX specific option.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Remove a redundant symbol that was used as a proxy to enable CONFIG_PM
and CONFIG_PM_DEVICE. If an application needs to enable PM, it should
just enable PM subsystem Kconfig options. Furthermore, there's no clue
"SOC_POWER_MANAGEMENT" is a NPCX specific option.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add pinctrl include file to define SOC specific pinctrl_soc_t structure,
used to store pin configuration for pinctrl driver
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Attaching SFRO clock to FlexCOMM0 should be conditional on the
device tree as an application may not need SFRO attached to FlexCOMM0.
Signed-off-by: Bryce Wilkins <bryce.wilkins@gmail.com>
The Bluetooth HCI driver based on the RPMsg transport now uses the IPC
service module. The compatible Bluetooth sample - HCI RPMsg - has also
been migrated to the new IPC solution.
Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>
Add configurable init priority for nrf53 synchronized rtc module.
Add build time assert to ensure that initialization is done after
mbox.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
The constraints API offered by TI HAL is meant to be used externally,
for example, when implementing a policy using their policy mechanism
(not used on Zephyr). The API is likely designed for systems where a
thin RTOS is used (e.g., FreeRTOS, TI-RTOS?), places where you basically
get a Kernel and a few services around, but not a system like Zephyr
where you also get, for example, a power management subsystem. This
means that it gets difficult for an RTOS like Zephyr to use such HAL
APIs while using its own constraints API. The first question is why we
allowed such kind of HAL code to be part of upstream Zephyr. It
certainly does useful things, but it is also uses a HAL infrastructure
which is hardly exportable to an RTOS like Zephyr. Part of the
Power_init() code, for example, should likely be in a clock controller
driver, where Zephyr APIs can be used.
The _solution_ that was done to workaround this case was allowing custom
full re-implementations of the constraints API. So we are basically
overwriting a functional API with custom HAL code because of poor HAL
designs. This is in general a bad design principle. If we allow this, we
can hardly offer any guarantees to the API users. For example, is
re-implemented as thread-safe? What is the API behavior then? ...
Platforms like TI that have incomplete support in Zephyr tend to leverage
to HAL code certain functions that should be proper Zephyr
drivers. Such platforms should not influence the design of APIs because
they lack solid foundations.
This patch removes the custom implementation since the HAL has been
patched so that it forwards PM state constraints to Zephyr.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Aligning with the rest of PM API, replace pm_power_state_exit_post_ops
with pm_state_exit_post_ops.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Commit 7cdd10bf89
("soc: arm: nordic: add NRF_DT_GPIOS_TO_PSEL_BY_IDX") added a use of
NRF_GPIO_PIN_MAP to soc_nrf_common.h without including the relevant
HAL header where it is defined, hal/nrf_gpio.h.
Unfortunately, including that header causes even more problems, since
it causes undefined NRFX_ASSERT() calls to appear elsewhere in the
tree.
It's not really worth bothering to use this macro. Just expand it
inline instead.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Extend initialization code for nRF5340 application core to iterate over
child nodes of GPIO pin forwarder node and pass control over detected
pins to the network core.
Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
Add a macro that allows to retrieve pin's PSEL from its devicetree
representation taking into account its index into GPIO array.
Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
With a number of the i.MX SoCs (e.g., the i.MX8M Plus), NXP has moved to
supporting the integrated Cortex-M cores with the MCUXpresso SDK (MCUX).
As a result, certain Zephyr drivers (such as the IPM driver) need to be
updated to utlize this new MCUX-based SDK.
This change adds support for the MCUX Messaging Unit driver pulled in by
this PR:
https://github.com/zephyrproject-rtos/hal_nxp/pull/130
Additionally, this change enables the new IPM_IMX_REV2 config for the
mimx8ml8_m7 SoC target which utilizes this new revision of the driver.
Signed-off-by: Chris Trowbridge <chris.trowbridge@lairdconnect.com>
The current MCUX IGPIO driver assumes that the target SoC supports
the DR_SET, DR_CLEAR, and DR_TOGGLE functionality, but some do not
(namely, the M7 core of the i.MX8M Plus SoC). Current releases of
the MCUXpresso SDK IGPIO driver contain utility functions to set,
clear, and toggle pins which include provisions to support SoCs
with and without DR_SET, DR_CLEAR, and DR_TOGGLE, and this change
switches to using these utility functions.
Additionally, this change enables GPIO support on the mimx8ml8_m7
target.
Signed-off-by: Chris Trowbridge <chris.trowbridge@lairdconnect.com>
Do not include psl-in related code is the status of vsby-psl-in-list is
disabled, which can help reduce a little RAM/flash size.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The help for MCHP_ECIA_XEC is defined in
drivers/interrupt_controller/Kconfig.xec. defconfig files must not
re-define prompts or help, just modify the default value.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The SoC Kconfig.defconfig.series files re-defined multiple Kconfig help
entries. The help for such symbols should only be present in places
where symbol is actually defined, not where the defaults are changed.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The ADC driver now supports three different implementations. To maintain
readability, this patch implements an adc_fixup.h that permits more
generic access to relevant registers.
This patch also introduces support for a new third shape ADC - as found
in the SAML21 for example.
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Divisor must be set to calculate SD host controller clock frequency in
clock driver.
Fixes#42380
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added basic support for the RP2040 SoC. Support
includes booting and starting the kernel, on one
core only.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add handling of secure-only code with TF-M enabled that can only be done
from secure processing environment.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Clear the LPSDSR bit of PWR_CR to restore the voltage regulator
mode when exiting from STOP mode. Leaving LPSDSR set can cause
cause stability issues because the MCU will enter low-power sleep mode
instead of normal sleep mode when the core idles and this is not what
the rest of the implementation expects.
Signed-off-by: Alexander Mihajlovic <a@abxy.se>
Re-organize the SoC family/series/model configuration data so that:
* Board definitions can distinguish between the single-core (XC7ZxxxS)
and dual-core (XC7Zxxx) ARM Cortex-A9 models. Further descriptions
of on-chip resources, in particular relating to the programmable logic
capabilities if support of this functionality is to be implemented,
can be added at a later time.
* Separate SoC initialization code exists for the two series, so that
the init code of the XC7Zxxx series can consider SMP while the init
code of the single-core XC7ZxxxS series doesn't have to.
* Device drivers which don't have to distinguish between the single-
and double-core series of the SoC family can use a common configuration
item whenever the pre-processor is used to enable Zynq-7000-specific
code.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
1. Setup VDD_SOC with the appropriate setting
depending on the SoC
2. Do not configure PLL_SYS and PLL_USB. These
are already configured by the ROM code using
the DCD
3. Fix setting for USDHC clock
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Fix for issue #41012 to allow compiler to treat
IRQn_Type to be more than 8-bit. This will ensure NVIC numbers
more than 127 (required for MEC172x device) will work
correctly with irq_enable() API
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add a module which is responsible for getting offset between RTCs
used for system clock on NET and APP cores. After getting an offset
between NET and APP clocks, it can be used for logging timestamping
on NET core to ensure that timestamping is in sync on both cores.
Synchronization is done using PPI, IPM task and events and RTC
capture feature.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
All options in Kconfig.soc are only for nrf53 series. Added file
wide guard instead of option specific options.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Enables basic power management for the RT11xx series SOCs. The following
power saving measures are currently implemented:
- system reduces core voltage during sleep
- core clock can be gated in deep sleep
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
GPC driver is used for power management operations on RT series SoCs.
Enable inclusion of the driver into the build.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Arm Cortex-M3 DesignStart FPGA-Xilinx edition doesn't have to use XIP.
Our board doesn't need it. Make it optional by replacing "select" with
"imply".
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Change the stm32_power_init to be executed PRE_KERNEL_1
for all the devices with the low power mode (power.c)
When GPIO and UART are not yet up and running.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
gPTP module clock is enabled for rt11xx. gPTP is not working correctly
on the RT10xx or RT11xx series, but this module clock needs to be
enabled
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The SAM spi driver depends on GPIO driver to work. It seems that this
dependency chain it is not handled. This select GPIO driver when SPI
driver is enabled. It rework GPIO and SPI Kconfig to select driver by
devicetree and drop entries at Kconfig.defconfig.series file.
Fixes#41525
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Introduce Pin Function Controller for Renesas R-Car family.
This first implementation support to set a given pin as gpio
or peripheral (GPSR), to set a peripheral function to a
pin (IPSR), to set pull-up, pull-down (PUEN, PUD).
In addition this driver allows to set driving capabilies(DRVCTRL).
Pins are identified thanks to the per SoC binding for
pin definition which also contains pin alternate function
parameters.
Some pins can also have driving capabilities, some have bias
capabilities.
In order to find the correct bias and drive registers pfc_r8a77951.c
describes the different registers.
Each SoCs or package will need to define getters
for these registers: pfc_rcar_get_bias_regs() and
pfc_rcar_get_drive_regs().
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
The Q variant is the same as non-Q, except the Q has SMPS built-in.
This symbol addition is to have the correct
SOC definition ("STM32H7A3XXQ")
Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The reg_def.h was not self-contained: it uses DT API but doesn't
include <devicetree.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Many ARM SoCs included <devicetree.h> likely due to:
1. nvic.h not being self-contained
2. As a result of copy-paste
Some RISC-V SoCs had the same problem, in this case likely due to
copy-paste from ARM. The <devicetree.h> header has been removed using
the following command:
sed -i ':a;N;$!ba;s/#include <devicetree\.h>\n//g' soc/**/soc.h
soc.h files that make a legitimate usage of the API have not been
changed.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The source file uses boolean types internally, however, <stdbool.h> was
not included. It was likely included indirectly before via
<devicetree.h> -> <sys/util.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Almost none of the soc_*.h headers were self-contained. This patch adds
all necessary includes to improve the situation.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
NPCX7/9 has a different ADC register structure. NPCX7 has 3 threshold
detectors from offset 0x14 & has 10 input channels. NPCX9 has 6
threshold detectors from offset 0x60 & has 12 input channels.
This commit fixes the NPCX ADC register structure.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Set TF-M option for nordic HAL library path to use the included
nordic HAL instead of the version that TF-M downloads.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Having DWT-based NULL-pointer detection enabled by default trips a lot
of users since it will make any debugging fail when enabled. Disable it
by default and let users enable it if they desire to.
Fixes#39216.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Change the settings to support pinctrl on the GD32VF103.
- Split soc/arm/gigadevice/common/pinctrl_soc.h
and put it into include/dt-bindings.
- Leave some definitions that can't handle with device tree compiler
in pinctrl_soc.h.
- Remove dependency to SOC_FAMILY_GD32 because always enabled it
if GD32_HAS_AF(IO)_PINMAX was selected.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
In this commit, the driver sets the PM constraint to prevent the system
from entering the suspend state for a CONFIG_UART_CONSOLE_INPUT_EXPIRED
period when data come in. The constraint releases after the
CONFIG_UART_CONSOLE_INPUT_EXPIRED time expires, .
With this change, the PM policy doesn't have to check the timestamp
by calling npcx_power_console_is_in_use() explictly. So the related
npcx_power_console_is_in_use*() functions can be removed.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
RT11xx can peripheral had incorrect clocking configuration in SOC clock
init code and DTS. Fix peripheral configuration.
Fixes#41251
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add board support for NXP i.MX8M Plus EVK. This board has the following
features:
Processor : i.MX8M Plus Quad applications processor
Memory : 32-bit LPDDR4 w/6 GB
eMMC 5.0/5.1 w/32 GB
SD/MMC connector
QSPI w/32 MB
Connectivity : MIMO 2x2 Wi-Fi 802.11b/g/n/ac and BT 4.2
2x Ethernet (1x w/ TSN)
PCIe M.2
2x CAN FD DB9 Female connectors
USB : USB 3.0 Type C for Power
USB 3.0 Type A
USB 3.0 Type C
Debug : JTAG connector
MicroUSB for debug console
More information about this board can be found in NXP website: https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-plus-applications-processor:8MPLUSLPD4-EVK
Signed-off-by: Chris Trowbridge <chris.trowbridge@lairdconnect.com>
USDHC driver build failure fix for mimxrt685_evk, dat3 pull function was
not defined at the SOC level.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds support for using GPT as the hardware timer source (as opposed to
systick) for all RT1xxx platforms. This requires moving the clock
frequency of these devices into a defconfig so it can be overridden by
the GPT clock frequency.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This enables the GPT timer for use as a hardware clock on the
MIMXRT1064. The timer will be disabled when builds use the GPT timer as
a counter, and the build will fall back to using the Cortex M systick as
a timer. This was tested using the kernel tickless test, to verify the
driver functions as expected.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added a driver to enable the GPT timer on RT1xxx parts to be used
instead of systick as a clock source. The timer is set to run in reset
mode, and uses the low frequency 32kHz oscillator for power savings
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable flexspi for RT11xx SOCs. This requires selecting the correct
KConfig symbol for the cortex m4 and m7 SOCs, as well as correcting an
error in the flexspi DTS node and updating the clock init for RT11xx
SOCs.
Note that in addition, the NXP hal must be updated to properly support
including the cache management driver for the Cortex M4.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
QEMU doesn't currently support MVE until the QEMU 6.2 release is out.
So for now only enable MVE support if we are NOT targetting QEMU.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
STM32H7 has different power supply modes but now Zephyr supports just LDO
and direct SMPS. This commit introduses POWER_SUPPLY_CHOICE configuration
parameter and add support for missed power supply modes.
Signed-off-by: Gennady Kovalev <gik@bigur.com>
Fixes#40730.
Add driver for MEC172x QMSPI with local DMA(LDMA). The driver
support SPI asynchronous operation.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
RT11xx clock init code was not handling difference between RT1160 and
RT1170 Bus_Lpsr clock correctly. Fix this.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
the RT685 contains an additional flexcomm peripheral, that supports
only I2C. This commit adds this peripheral to the device tree,
and enables pins and clocks for flexcomm15.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds a driver using the SNVS high power and optionally low power
RTC instances. A device specific function `mcux_snvs_rtc_set` is
provided to update the current counter value.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
RT11xx SOC definitions did not enable USDHC controller. Select Kconfig
symbols required to enable it.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
A Cortex-M specific function (sys_clock_isr()) was defined as a weak
function, so in practice it was always available when system clock was
enabled, even if no Cortex-M systick was available. This patch
introduces an auxiliary Kconfig option that, when selected, the ISR
function gets installed. External SysTick drivers can also make use of
this function, thus achieving the same functionality offered today but
in a cleaner way.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The device PM callback needs to be used only to suspend/resume devices.
If the system cannot be suspended because UART is in a particular
state, the pm_constraint_set/release API should be used. For NPCX UART,
the chip can't enter low power idle state until UART completes the data
transmission.
This commit changes NPCX UART to use pm_constraint_set/release & fixes
UART lost data from low power idle.
Fix#40621
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
RT600 uses the mcux flexspi driver, which can produce RWW hazards when
calling code linked into flash (such as the logging subsystem). Disable
logging in flexspi driver by default for RT600 series.
Fixes#40744
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit adds support for IMX6SX PWM.
The PWM module is the same module present on the IMX7D and so dts
bindings has been renamed following the one present on linux.
Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
Some PM cases were not handled correctly (missing default statement).
The error was caught by CI while doing other PM related work.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Since the addition of pinctrl the common folder is added to the Zephyr
include path. This can be re-used to place the soc_nrf_common.h header
in the common folder and include it directly, without the need of
relative paths.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add initial support for nRF pin controller driver. The implementation in
this patch does not yet support any peripheral. Only states
representation and basic driver functionality is introduced.
Note:
The nrf_pin_configure function has been marked as __unused since it may
not be used in certain scenarios until all peripherals are supported by
the pinctrl driver. For example, if only UART/E is supported but the
board does not enable UART, the function will never get called. However,
that board will likely have other peripherals that will gain support in
the future.
Thanks to Marti Bolivar for bindings documentation.
Co-authored-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add initial version for STM32 pinctrl driver. Driver has been written
re-using many of the already existing parts in
drivers/pinmux/pinmux_stm32.c.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Program flow will behave incorrectly (memory and instruction fetches
return invalid data) if Flexspi is accessed by the Flexspi driver while
being used as XIP memory by the Cortex M7.
Set logging to disabled by when XIP mode is used in the memc and
flexspi drivers, and warn the user if they attempt to enable it.
Fixes#40133
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable pinctrl by default, since it is an essential component on almost
every firmware. Inclusion of series defconfig has also been guarded with
SoC availability (was missing).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a pin control driver for GD32 SoCs using the AFIO model.
Thanks to Gerson Fernando Budke for testing and implementation
suggestions.
Co-authored-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Despite the "F4" prefix, GD32F403 is an SoC with significant differences
compared to other F4 MCUs:
- It has a completely different HAL
- It has significant hardware differences, for example, the pinctrl
mechanism uses AFIO (all others use AF)
The grouping principles applied to other similar vendors such as ST
can't be applied for GD32 due to these reasons, so the approach taken
here is to define series based on the used HAL. A different HAL likely
means that there are significant hardware differences between, e.g. F403
and F405. The vendor likely chose a confusing naming scheme, but we need
to deal with it.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The Flexspi memory address defines the location of the externally
attached flash to the MXRT600 based board. The flexspi has two
different memory spaces for secure and non-secure access that are
not aligned for the Flexspi register space and the memory map
address space. The normal method of handling this via the two
different dts files for secure/non-secure is not able to handle
this because a base address is applied uniformly across multiple
reg items.
Changes include:
- pull flexspi out of peripherals block to allow it to be explicitly
expressed in the respective secure/non-secure SOC DTS files.
- move the flash size definition to the board level definition and
use the size of the actual flash device found on the board.
:
Signed-off-by: David Leach <david.leach@nxp.com>
Use SMPS power supply only if enabled.
The default power supply configuration for the
NUCLEO board with -Q subfix is SMPS,
so it's essential to match with hardware configuration
to avoid deadlocks due to mismatch.
if a custom board with LDO configuration is in use,
then no need to enable `CONFIG_POWER_SUPPLY_SMPS`
Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
Updates to MEC172x eSPI driver to support ACPI shared
memory region and EC Host Command Subsystem through
ACPI_EC1 and Embedded Memory Interface (EMI).
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add Kconfig items that can be used to query if the current SoC
support the HW peripherals for some peripherals that are missing.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Provide some factorization in pm_power_state_set procedure
to prepare shutdown case introduction.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add baseline support for mimxrt1160_evk Cortex M4 and M7 cores
UART shell, synchronization, and hello world have all been verified to
build and run correctly.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The FIU/UMA module in the NPCX chip provides an dedicated SPI interface
to access the SPI flash. This commit adds the driver support for it.
With this commit, the application can call the flash APIs
(via spi_nor.c) to access the internal flash of NPCX EC chips.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I32bbf09f6e014b728ff8e4692e48151ae759e188
Add SoC-specific code, the basic device tree and Kconfig data as well
as the corresponding linker command file for the Xilinx Zynq-7000
family of SoCs. This SoC - either as a QEMU simulation or on actual
hardware such as the Avnet/Digilent ZedBoard - is suitable as an ini-
tial target for the ARMv7 Cortex-A support.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
MEC172x eSPI driver, eSPI pin programming, interrupt updates related
to eSPI and other updates for MEC172x eSPI driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Errata ES0392 Rev 8:
2.2.9: Reading from AXI SRAM may lead to data read corruption
Workaround: Set the READ_ISS_OVERRIDE bit in the AXI_TARG7_FN_MOD
register.
This is applicable only to RevY (REV_ID 0x1003)
Fixes#38933
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Refactors all of the ADC drivers to use a shared driver class
initialization priority configuration, CONFIG_ADC_INIT_PRIORITY, to
allow configuring ADC drivers separately from other devices. This is
similar to other driver classes like I2C and SPI.
The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEVICE to preserve the
existing default initialization priority for most drivers. The
exceptions are lmp90xxx, mcp320x, and mcux_adc16 drivers which have
dependencies on GPIO, SPI, and/or DMA drivers and must therefore
initialize later than the default device priority.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Refactors all of the clock control drivers to use a shared driver class
initialization priority configuration,
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, to allow configuring clock control
drivers separately from other devices. This is similar to other driver
classes like I2C and SPI.
Most drivers previously used CONFIG_KERNEL_INIT_PRIORITY_OBJECTS or
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, therefore the default for this new
option is the lower of the two, which means earlier initialization.
The even lower defaults for STM32 and Arm Beetle are preserved by
SoC-family level overrides.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Add a Kconfig option, similar to the one that is already available
for nRF5340, that allows enabling the REG0 (VDDH) DC/DC converter
in nRF52840. Make use of this option in Nordic boards: nRF52840 DK
and nRF52840 Dongle.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Configures the default serial driver initialization priority for NXP
SoCs to ensure that serial drivers initialize after clock control
drivers.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Uses the stats subsys to provide simple but useful debugging stats for
power management state changes and timing.
Removes the no longer needed PM_DEBUG config option
Replaces the use of PM_DEBUG for a test clock output pin for mec1501 and
adds in its place an SoC Kconfig option to enable it.
Adds a STATS_SET macro for assigning a value to a stat group field
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
The parameters to FIELD() should be the position and size of each bit
field. Correct the size of IOMODE and MAXFREQ. Otherwise, the MAXFREQ
field is overwritten by the IOMODE update during espi_npcx_configure().
Signed-off-by: Diana Zigterman <dzigterman@google.com>
Provide power modes implementation for u5 socs.
For now STOP3 mode is not implemented as this mode is not
compatible with LPTIM activation and hence cannot be used
as a workable suspend to idle state using LPTIM as kernel
tick source.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
When existing stop mode 1&2, VCO is set to range 4
and should be set back to range 1 to allow full speed
operations.
Rather than setting VCO at startup, set it inside clock
setting procedure so that it could done
in clock reset procedure when existing stop modes.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
A new stm32f412vx devices is introduced.
The soc devices stm32f412cx, stm32f412vx, stm32f412zx are
removed to have a more generic stm32f412xx Kconfig.
The stm32cube modules stm32f412cx/vx/zx exists.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
When exiting Stop mode, if system clock is MSI, MSI oscillator is
selected as wakeup from stop clock; otherwise HSI16 oscillator is
selected.
It is otherwise reconfigured as MSI just after, but it slightly
increases the wake-up time and power consumption.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
A few HAS_HW_NRF_* Kconfig options for peripherals available in nRF5340
are not selected. Fix it.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Following the migration of the clock source configuration in DTS (commit
2691541ad2), HSI is always used as wake-up source on STM32LX. It is
reconfigured as MSI just after, but it slightly increase the wake-up
time and power consumption.
It happens as the file defining STM32_SYSCLK_SRC_MSI is not included.
Fix that.
Fixes#38807
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Similarly to what was done on stm32g0, disable DBGMCU clock
after operation to avoid conflict with openocd.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
If clock is not enabled write access on that registers are no-op.
Disable clock after operation to avoid conflicts with openocd which
can also access this clock when flashing.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
During review of #38681, switching from HAL to LL,
involuntarily enable DBGMCU clock instead of DMA clock.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
On some STM32 boards, for unclear reason,
RTT feature is working with realtime update only when
* one of the DMA is clocked
and sometimes also
* one of the DBGMCU bit STOP/STANDBY/SLEEP is set
Fixes#34324
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
It happens that CM7 wakeups CM4, before CM4 goes to sleep.
Thus when CM4 goes to sleep,
there no more wakeup from CM7. And CM4 hangs.
For a simple synchronisation implementation,
CM4 doesn't go to sleep any more,
instead it waits (active wait) for CM7 to take HSEM
(meaning that clock configuration is finished).
Fixes#38069
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
On STM32L0, there are some hardfault when DBGMCU bit Sleep, Stop
or Standby are enabled. See #37119
For unclear reason, enabling DMA clock fixes this issue.
(similarly than #38561, DMA clock comes with DBGMCU bits)
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
CONFIG_PM_DEVICE was a de-facto requirement when enabling CONFIG_PM=y
since some device, i.e. UART, used the PM device hooks to block
suspension process while the device was busy finishing transmission.
This has now been fixed using constraints, so CONFIG_PM=y can be enabled
without further requirements.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
TI Hal has its own constraint API that is used by its drivers. These
constraints need to be correlated with Zephyr constraints to be
constraints set in the HAL be visible on Zephyr and vice-versa.
Fixes#38362
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
In commit "pm: Fix weak linkage symbols" (PR #35274),
PM SoC hooks were converted to __weak to avoid clash with
new definition of these symbols in subsys/pm/power.c.
G0 power implementation was implemented in parallel
with this change and missed the update.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Low power modes entry on stm32wb depends on requests coming from both
cores, with no consideration of the fact that C2 is booted or not.
By default, set C2 power mode to shutdown at C1 start up.
If required, it will be updated by C2.
In case C2 is not started, this will allow C1 to enter any power mode
with no dependency on C2.
Fixes#38173
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
the config symbol was missing for some reason even though
the soc does have a flexspi peripheral like most other socs
in the family.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
This is the initial version of a Zephyr CMake linker file for the arm
architecture.
This file defines memory regions, groups, linker sections and symbols
for the arm architecture.
It also sources the common common-ram.cmake, common-rom.cmake,
debug-sections,cmake, and thread-local-storage.cmake.
It configure sections for SoC families using zephyr_linker_sources()
functions:
- nxp_imx
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Microchip MEC172x series I2C driver implementing controller
and target modes. The driver implemenents its own I2C port
pin control functions and does not depended upon pinmux. Future
updates will make use of PINCTRL when that subystem is finalized.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add Kconfig options that allow users to select the way the APPROTECT
mechanism is handled in the SystemInit() function.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
1. Update soc.c file to add USB clock setup
2. Add a linker script file to move USB transfer
buffer and controller buffers to USB RAM
3. Update Kconfig's to add USB support
4. Add zephyr_udc0 nodelabel
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Update soc.c file to add USB clock setup
2. Add a linker script file to move USB transfer
buffer and controller buffers to USB RAM
3. Update Kconfig's to add USB support
4. Add zephyr_udc0 nodelabel
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
