Commit graph

11,885 commits

Author SHA1 Message Date
Benjamin Cabé
18b5c740e4 dts: cpu: Make descriptions consistent
Streamline the description field for CPU bindings by removing
inappropriate use of terminology such as "This is a representation
of...", or mentions to "node".

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2025-02-25 07:55:09 +01:00
Mathieu Choplain
5af9a0ae4c dts: st: stm32u595: remove OTGHSPHY enable bit from usbotg_hs clocks
37bdc38ec6 failed to take into account commit
f72ef5c237, and added the OTGHSPHYEN bit
back into the OTGHS controller's `clocks` property. This should have no
functional impact (due to how the USB driver is implemented), but ought
to be removed anyways as duplicates information and is confusing.

Clean the DTSI for U595 and revert back OTGHS controller `clocks` such
that it only contain the controller's clock enable bit, as it should.

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
2025-02-21 18:03:03 +00:00
Sadik Ozer
4901863742 dts: arm: adi: Fix MAX32670 I2C clock index
I2C2 clock index is 21 for MAX32670

Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
2025-02-21 18:02:41 +00:00
Mert Ekren
1fb3bd7986 dts: arm: adi: Update MAX32675 I2C2 instance clock bit
I2C2 GCR bit is different than common defined in MAX32xxx.dtsi

Signed-off-by: Mert Ekren <mert.ekren@analog.com>
2025-02-21 18:02:41 +00:00
Furkan Akkiz
4bcd2dbb37 dts: arm: adi: Delete I2C2 node for MAX32662
Deleted I2C2 node which is not supported by MAX32662.

Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
2025-02-21 18:02:41 +00:00
Benjamin Cabé
35a535fb9a drivers: sensor: fix spelling of "addtional"
s/addtional/additional/

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2025-02-21 11:41:46 +00:00
Benjamin Cabé
8500063a94 dts: spi: fix spelling of "transfer"
s/trasnfer/transfer/

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2025-02-21 11:41:46 +00:00
Benjamin Cabé
9f18d3dcf6 dts: add binding types registry
A file similar to vendor-prefixes.txt that provides a short description
of the top-level folders contained in dts/bindings

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2025-02-21 04:47:17 +01:00
Pieter De Gendt
817c0396b9 drivers: ethernet: phy: dm8806: Fix driver bindings
There were some driver bindings issues for the davicom dm8806 driver:
- Missing type for reg-switch binding
- Missing required: true for int/reset gpios
- Fix macro for reg-switch

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2025-02-20 11:47:21 +01:00
Jacob Wienecke
9e1bf0b496 dts: arm: nxp: RT10xx/11xx .dtsi Files: Remove flexram,bank-spec property
This commit removes the flexram,bank-spec property from dtsi files.
The property causes flexram to be dynamically configured based on
the configuration in flexram,bank-spec. This is a problem for 2 reasons:
1) The FlexRAM will always be dynamically reconfigured to default
fuse configuration. This is unnecessary if using default fuses.
2) If a user decides to program fuses. The FlexRAM will still be
reconfigured to the default fuse configuration.

Modify description in the binding to show how to use the property at:
dts/bindings/memory-controllers/nxp,flexram.yaml

Added board overlay to mimxrt1170_evk_cm7 magic_addr:
samples/boards/nxp/mimxrt1170_evk_cm7/magic_addr/boards

Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
2025-02-20 06:04:46 +01:00
Benjamin Cabé
4417fdb128 drivers: sensor: fix "Celsius" spelling
s/Celcius/Celsius/  -- preserved original case

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2025-02-19 18:51:13 +01:00
Mathieu Choplain
37bdc38ec6 dts: st: stm32u5: restore correct clocks on multi-bit devices
During the transition to STM32_CLOCK macro (in 57723cf), the `clocks`
property of peripherals requiring more than one bit to be set were
mistakenly modified. Commit 2c3294b079
partially fixed these errors, but some nodes for the U5 series are still
wrong.

Restore `clocks` on affected devices in corresponding STM32U5 DTSI.

Fixes: 57723cf405
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
2025-02-19 14:50:36 +00:00
Sergei Ovchinnikov
b432a01c23 drivers: regulator: npm1300: add reference to anomaly 38
Added reference to nPM1300 anomaly 38 replacing generic "LDO bug"

Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
2025-02-19 14:50:02 +00:00
Quy Tran
292f7454d4 soc: renesas: ra: Move configs from board deconfig into SoC deconfig
- Move config BUILD_OUTPUT_HEX and CLOK_CONTROL from board deconfig
into SoC deconfig
- Add clock-frequency in dts to get config
SYS_CLOCK_HW_CYCLES_PER_SEC from dts

Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
2025-02-18 18:38:15 +01:00
Adam Kondraciuk
865b2456c0 dts: nordic: Add support for clock outputs
Add support for GRTC clock output pins.

Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
2025-02-18 18:37:35 +01:00
Ting Shen
d743b31af6 dts: npcx: fix incorrect unit-address of sram node
The unit-address must match the first address specified in the reg
property of the node.

Signed-off-by: Ting Shen <phoenixshen@google.com>
2025-02-17 10:21:49 +01:00
The Nguyen
86098acfbc dts: arm: renesas: add CANFD dllclk limit on Renesas RA family
Add information on CANFD dllclk upper and lower limits on these SoCs:
- RA8: RA8M1, RA8D1, RA8T1
- RA6: RA6E2
- RA4: RA4E2

Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
2025-02-15 07:23:10 +01:00
The Nguyen
b0debcc302 drivers: can: add DLL bitrate limit check for can_renesas_ra
Add condition to check uppper/lower limit of DLL clock rate

Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
2025-02-15 07:23:10 +01:00
Mert Ekren
6280d2acbf dts: Add MAX32666 SDHC nodes and bindings
Include sdhc0 in MAX32666 devicetree and add devicetree bindings for
MAX32 SDHC driver

Signed-off-by: Mert Ekren <mert.ekren@analog.com>
2025-02-14 20:20:03 +01:00
Aleksandr Senin
12ad8f0f6e drivers: eth: dsa_ksz8xxx: Add support for KSZ8463/KSZ8463F
This commit adds basic support for KSZ8463/KSZ8463F chips to the
dsa_ksz8xxx.c driver.

These chips have limited register compatibility with other members
of the KSZ8XXX family - their registers are 16 bits wide as opposed
to the 8-bit registers supported by the driver for KSZ8794 and
KSZ8863. Following the general logic of the existing code,
the 16-bit registers of KSZ8463 are split into 8-bit halves.

For the KSZ8463F chip, it is assumed that both ports are used
in Fiber mode.

A new configuration option, CONFIG_DSA_KSZ_PORT_ISOLATING, has been
added to isolate traffic between DSA slave ports.

The driver has been tested on a custom board with an STM32F7 SoC.

Signed-off-by: Aleksandr Senin <al@meshium.net>
2025-02-14 20:16:25 +01:00
Guillaume Gautier
76344062ed dts: arm: st: n6: add spi
Add SPI support to STM32N6

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2025-02-14 19:15:09 +00:00
Thao Luong
168284a8cc soc: renesas: ra2l1: Add initial support for Renesas RA2L1 SOC series
Add basic support for Renesas RA2L1 SOC series.

Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
2025-02-14 19:14:30 +00:00
Lucien Zhao
ba982a0f85 dts: arm: nxp: register ostimer for cm33_cpu0/1
register ostimer for cm33_cpu0/1
disable systick
set ostimer per sec 1000000 times

Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
2025-02-14 17:24:58 +01:00
Lucien Zhao
f378a8c7cc dts: arm: nxp: rt118x: add two usdhc instances
enable clock in soc.c
register two usdhc instances

Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
2025-02-14 16:21:11 +00:00
Thao Luong
0b97890163 soc: renesas: ra: Add minimal support for ra4l1
Add minimal support for RA4L1 SoC and devicetree

Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
2025-02-14 17:15:43 +01:00
Bjarki Arge Andreasen
d01c93c120 dts: nordic,nrf-saadc: set pm device runtime auto
Set pm device runtime runtime auto flag to ensure saadc instances
are initialized correctly if pm device runtime is used.

Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
2025-02-14 17:12:03 +01:00
Tomas Galbicka
34575e84cd dts: soc: Add DTS MBOX and CM7 boot for NXP RT1180
This commit adds MBOX device tree entry for RT1180.

Adds functions to copy and boot CM7 core.

Adds MPU region for shared memory without caching.

Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
2025-02-14 17:11:50 +01:00
Yasin Ustuner
c62606daa7 include: zephyr: dt-bindings: Add MAX32660 DMA binding
This commit adds binding file for DMA slots

Signed-off-by: Yasin Ustuner <Yasin.Ustuner@analog.com>
2025-02-14 17:04:57 +01:00
Yasin Ustuner
de9f48ee33 soc: adi: Add MAX32660 SoC
This commit adds MAX32660 SoC
and dts files.

Signed-off-by: Yasin Ustuner <Yasin.Ustuner@analog.com>
2025-02-14 17:04:57 +01:00
Sean Madigan
a3474b76dc dts: nordic: nrf5340: Revert nRF5340 IPC backend to rpmsg
This reverts commit 70419bdee7.

This is because there are issues around slow IPC thoughput
with icbmsg, which is causing issues with BLE when lots of
data is required to be exchanged, e.g. with ISO.

Also there is an assert icmsg.c#L190 which occurs when
initializing bluetooth and IPC in certain circumstances.

Signed-off-by: Sean Madigan <sean.madigan@nordicsemi.no>
2025-02-14 13:35:53 +01:00
Burak Babaoglu
1db033dd62 soc: adi: Add the MAX32650 SoC
This commit adds MAX32650 Kconfig
and dts files for basic port.

Signed-off-by: Burak Babaoglu <Burak.Babaoglu@analog.com>
Signed-off-by: Yasin Ustuner <Yasin.Ustuner@analog.com>
2025-02-14 13:35:26 +01:00
Dominik Kilian
84a215aff8 ipc_service: icmsg: Add "unbound" functionality
In some cases, CPUs that may need to reset or
temporary stop communication. This commit adds "unbound"
functionality that provides a callback to IPC service user
when connection was interrupted for some reason, e.g.
expected or unexpected CPU reset, closing the
endpoint. The "unbound" callback is optional to implement
by endpoints. This commit implements it in the ICMsg
backend.

Signed-off-by: Dominik Kilian <Dominik.Kilian@nordicsemi.no>
2025-02-14 13:34:49 +01:00
Guillaume Gautier
20d1b6c6c7 dts: arm: st: n6: add adc node to stm32n6 dtsi
Add ADC1 and ADC2 to STM32N6 device tree.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2025-02-14 10:48:35 +01:00
Guillaume Gautier
8cdee9fe51 dts: bindings: adc: add adc bindings for stm32n6
STM32N6 ADC doesn't have an integrated prescaler, so these properties have
to be removed.
Though the F1 compatible also removes these two same properties, grouping
the N6 with the F1 would not be convenient since there are lots of
differences between the two.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2025-02-14 10:48:35 +01:00
Guillaume Gautier
ba251072b8 dts: arm: st: n6: add i2c
Add I2C nodes to STM32N6

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2025-02-14 10:43:44 +01:00
Yishai Jaffe
c1d05bfaea dts: st: use ST DMA defines
Use dma_stm32.h DMA defines instead of using hard-coded values

Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
2025-02-14 10:43:37 +01:00
Titouan Christophe
d2818c4d49 audio: codec: add new cs43l22 driver
Add new driver for the Cirrus CS43L22 audio DAC.

Signed-off-by: Titouan Christophe <moiandme@gmail.com>
2025-02-14 10:42:53 +01:00
Khaoula Bidani
1c6915b9b1 dts: bindings: clock: make clocks property required
Modify properties clocks as required in stm32-clock-mux.yaml.


Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
2025-02-14 10:42:42 +01:00
Wilfried Chauveau
c0139fad06 drivers: gpio: mmio32: update gpio_mmio32 to behave like other divers
The current implementation requires SoCs/Boards to manualy instantiate
the preripherals and initilize them.

The change lets Zephyr rely on the device tree setup to instantiate &
initialize the relevant gpio peripheral.

Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
2025-02-14 10:42:02 +01:00
Kacper Brzostowski
d6fdbb8953 dts: st: h5: addSTM32H562xG SoC support
Added STM32H562xG dts file

Signed-off-by: Kacper Brzostowski <kapibrv97@gmail.com>
2025-02-14 10:41:51 +01:00
Titouan Christophe
baa41f43af boards: stm32h7s78-dk: add support for OTGFS (USB port 2)
Add OTGFS peripheral to the stm32h7rs soc series, and enable it on the
Discovery board STM32H7S78-DK, where it is wired to USB Type-C port 2.

Signed-off-by: Titouan Christophe <moiandme@gmail.com>
2025-02-14 10:41:43 +01:00
Lubos Koudelka
21e4084917 dts: arm: st: wba: Add MCO1 peripheral to STM32WBA device tree
Added MCO1 peripheral definition to the STM32WBA device tree to enable
MCO functionality.

Signed-off-by: Lubos Koudelka <lubos.koudelka@st.com>
2025-02-14 10:41:18 +01:00
The Nguyen
b513a8db34 dts: arm: renesas: add phys-clock for usbhs node
Add phys-clock to usbhs node in case internal phys-clock-src is used

Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
2025-02-14 08:44:39 +01:00
The Nguyen
164847f3a6 dts: arm: renesas: add UDC support for USBFS module
Add device node of usbfs on Renesas RA SoC

Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
2025-02-14 08:44:39 +01:00
The Nguyen
227f2c4fb4 drivers: udc: add UDC support for USBFS on Renesas RA family
First commit to add support for USBFS module on Renesas RA
- Remove renesas,ra-usb binding
- Add 2 new binding for Renesas RA USBFS and USBHS
- Remove unused interrupts of USBHS

Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
2025-02-14 08:44:39 +01:00
The Nguyen
0fc95b8927 dts: arm: renesas: add uclk clock node for ra2a1
Add missing clock node of uclk on Renesas RA2A1 SoC

Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
2025-02-14 08:44:39 +01:00
Andrei Menzopol
e9cdc6e776 dts: nxp: add ieee and trng bindings and nodes
Add ieee802154 and trng bindings and nodes

Signed-off-by: Andrei Menzopol <andrei.menzopol@nxp.com>
2025-02-14 03:08:48 +01:00
Marcin Lyda
f370d38363 drivers: rtc: Add Maxim DS1337 RTC driver
This PR adds support for Maxim Integrated
DS1337 RTC chip.

Supported functionalities:
* Alarm interrupt (both alarms trigger INTA pin)
* Time setting/reading
* Both alarms setting/reading
* SQW frequency configuration

Tested on nRF52833-DK using rtc_api test set.

Signed-off-by: Marcin Lyda <elektromarcin@gmail.com>
2025-02-14 03:03:56 +01:00
Yangbo Lu
ccc21a082e dts: arm: nxp: add M7 ITCM/DTCM region into linker
Added M7 ITCM/DTCM region into linker.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2025-02-14 03:03:38 +01:00
Camille BAUD
637686695c sensor: Introduce Phosense XBR818 Driver
This Introduces a driver for the i2c interface of Phosense XBR818.
XBR818 is a 10.525Ghz Radar chip with builtin detection algorithm.

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-02-14 03:03:22 +01:00