The current implementation iterates over all channels
even if only several channels share the same irq. This
introduces one more dt property to describe an offset
between two channels share the same interrupt id.
Beside that, the error interrupt must be put as last
element of "interrupt" dt property.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
With the current implementation, the 1st cell is not DMAMUX id
as mentioned in the bindings (0 for DMAMUX0 and 1 for DMAMUX1).
Moreover, the referenced Linux bindings is obsoleted, it was
migrated to use yaml syntax
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
These worked because edtlib allows 'pinctrl-.*' properties without
specifying them on the bindings. However, this has never been an
anounced pinctrl feature, the reference documents explicitly mention
that usage of pinctrl-device.yaml is mandatory.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Revise property's name & cells' name for further
devicetree reset macro used.
Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Based on RM0456, each PLL in the STM32U5 has the
capability to work either in integer or fractional mode.
In this update, the fractional mode can be enabled
by setting the fracn value in the device tree.
Signed-off-by: Jatty Andriean <jandriea@outlook.com>
The old CONFIG_UART_NS16550_ACCESS_IOPORT has been used to
indicate whether to access the NS16550 UART via IO port
before device tree is used to describe hardware. Now we have
device tree, and we can specify whether a particular UART
needs to be accessed via IO port using property io-mapped.
Therefore, CONFIG_UART_NS16550_ACCESS_IOPORT is no longer
needed (and thus also CONFIG_UART_NS16550_SIMULT_ACCESS).
Remove these two kconfigs and modify code to use device tree
to figure out how to access the UART hardware.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Introduce support for Texas Instruments TMAG5170
high-precision linear 3D Hall-effect SPI sensor.
This driver allows to configure measurements on
magnetic and temperature channels. It is also
possible to read rotation of the magnet.
Signed-off-by: Michal Morsisko <morsisko@gmail.com>
Added a phandle named dma-parent to get base address instead of
adding DMA as child node because it is causing a build warning
(avoid_unnecessary_addr_size) if the parent instance has
"#address-cells/#size-cells" dts properties marked required
and child doesn't have reg property. DMA doesn't have reg
as it gets the base address from parent device
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Adds initial support for hm330x dust sensor series. Allows to read PM1,
PM2.5 and PM10 concentrations in atmospheric environment. A further
update to the driver may add support for also reading "standard" CF1
concentrations by exposing of a custom sensor attribute or a Kconfig
option. Tested with Grove - Laser PM2.5 Sensor (HM3301) attached to a
Wio Terminal.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
When the alternate setting is configured as func3, in addition to
the setting of func3-gcr, some pins require external setting.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add support for SMARTDMA to RT5xx SOCs. SMARTDMA ram banks will be
powered up, so code can be programmed into this region for the SMARTDMA
engine.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce SMARTDMA dma driver. The SMARTDMA is a peripheral present on
some NXP SOCs, which implements a programmable DMA engine. The DMA
engine does not use channels, but rather provides a series of API
functions implemented by the firmware provided with MCUX SDK.
These API functions can be selected by the dma_config slot parameter. A
custom API is also provided to allow the user to install an alternate
firmware into the SMARTDMA.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add MDIO driver that works through GPIO pins. This driver is
useful when a microcontroller doesn't have MDIO bus or when multiple
separate MDIO buses are required. The driver provides access to
the MDIO bus through GPIO pins for any SoC that has GPIO pin control
available.
Signed-off-by: Aleksandr Senin <al@meshium.net>
Add a property for STM32 ADC to indicate which type of sequencer is used
by the device (fully configurable or not).
Add defines to help with this setting.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use clock control API to retrieve the module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Use clock control API to retrieve the module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The PIT maximum load value may not be always 32-bit. Allow the SoC to
define this value from devicetree.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Remove temp-, vref- and vbat-channel from STM32 ADC nodes as it is not
used in the driver anymore.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use clock control API to retrieve the module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Deprecate the advanced CAN timing devicetree properties in favor of setting
advanced timing parameters from application code.
The advanced timing properties are giving in number of time quanta (Tq) and
requires reverse-calculation to find a suitable CAN clock divider. The
resulting bitrate error is compared against a threshold in the driver
initialization code, but the application is not able to retrieve it.
Forcing applications to use the CAN timing APIs directly instead makes it
up to the application to determine if the bitrate error is acceptable or
not.
The deprecated properties are:
- prop-seg
- phase-seg1
- phase-seg2
- prop-seg-data
- phase-seg1-data
- phase-seg2-data
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add phandle prop to reference any regulator that must
be enabled in order for the LPADC to function as intended.
Change LPADC driver to use this property if present.
LPADC on LPC55S36 depends on VREF peripheral, enable for this platform.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add node for VREF0 peripheral to LPC55S3X SOC DT
Clock VREF peripheral if status = okay in DT
Enable VREF on lpcxpresso55s36
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add binding, include header, and driver for NXP VREF IP block.
NXP VREF is an internal voltage reference generator on some SOCs
that fits well with the regulator API in zephyr.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Enable clock control driver for NXP S32ZE SoCs and add clock sources
definitions for devicetree.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The ARM Cryptocell 310/312 IP is wrapped by Nordic specific registers.
It is organized as follows:
- Base address: Nordic wrapper
- Base address + 0x1000: ARM Cryptocell IP registers
Following more standard devicetree conventions, use a single node for
what is exposed as a single peripheral. The node contains 2 register
entries, one for the wrapper and a second one for the 3rd party IP.
Compatibles are used from more specific (nordic,cryptocell) to more
generic (arm,cryptocell-3xx).
Other minor fixes: peripheral is disabled by default (as it should be in
SoC dts files).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This platform (SOC_SERIES_EFM32PG1B) is also using SOC_GECKO_SERIES1 and
needs a pinctrl device defined to build the gecko-uart driver
successfully.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The gecko UART driver needs pinctrl support for SOC_GECKO_SERIES1
devices, this has been added to jg and pg 12b series in 40fa96506b but
is missing in others, causing some build failurse.
Add the device nodes for the gg11b and gg12b files since they contain
gecko-uart references and seems to be under the SERIES1 define.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Rework RAM disk driver to be configured using devicetree and
support multiple instances.
This patch also removes a copy of the RAM disk driver,
tests/subsys/fs/fat_fs_dual_drive/src/disk_access_test_drv.c,
that was there for testing multiple disk drivers support.
Bonus: one SYS_INIT() less and a memory region can be exported to the
host.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
