This adds frontend of arm ethos-u core driver for nuvoton numaker m55m1x.
Special notes include:
1. Leaving application overriding dcache flush/invalidate weak functions
for cacheable NPU buffer
2. Configuring macs_per_cc to 256 in arm ethos-u core driver to match
m55m1x ethos-u RTL config
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
Allows to configure the alert or therm mode for triggers
based on the low/high temperature treshholds
Also adding simple PM
Signed-off-by: Tobias Meyer <tobiuhg@gmail.com>
Some instances of timers such as wakeup timer are not tied to a clock
bus so make this property optional.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Set MAX32657 cpu power states as idle, standby and powerdown. Power down
mode is disabled by default and can only be entered by calling
pm_state_force. Note that residency durations may need to be updated
depending on the resolution of chosen sleep timer.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Add basic power management states of MAX32657.
After UG/DS has been finalized the values and states
might be need to be updated.
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
- Add lux conversion to APDS-9306 driver
- Change settings of gain, resolution and
frequency to index-based settings
- Add Device Tree overlay sample for APDS-9306
- Fix wrong board name in light_polling README
- Add value checks for the attribute set API call
- Remove the reading of the sensor attributes
from the sensor and use buffered values instead
- Rename `frequency` property to `measurement period`
Closes#91104
Signed-off-by: Daniel Kampert <DanielKampert@kampis-elektroecke.de>
Make the common SPI CS delay property configurable from devicetree. This
can be required for using a nRF54L as a Bluetooth controller, since it
has an additional delay after waking up from the CS assertion until it
is ready to accept and transmit data (see OPS t_START_HFINT).
Signed-off-by: Jordan Yates <jordan@embeint.com>
Although the value currently hard-coded in the driver (10 ms) is quite
high, it may turn out to be insufficient when there is a need to use
some very low SCK frequency, like 250 kHz.
Make the timeout value configurable per-instance, via devicetree.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Before this commit size of rx and tx queues was set to 1, which is out of
spec. This commit adds queue logic, ability to set their size and exposes
configuration options w.r.t rx queue interrupts
Signed-off-by: Jakub Michalski <jmichalski@antmicro.com>
Add support the host I/O over eSPI peripheral channel for private
channel.
The default port number of ESPI_PERIPHERAL_HOST_IO_PVT_PORT_NUM
for ITE SoC is 0x68.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Transition nrf54h away from the soc specific gpd
(global power domain) driver which mixed power domains, pinctrl
and gpio pin retention into a non scalable solution, forcing soc
specific logic to bleed into nrf drivers.
The new solution uses zephyrs PM_DEVICE based power domains to
properly model the hardware layout of device and pin power domains,
and moves pin retention logic out of drivers into pinctrl and
gpio, which are the components which manage pins (pads).
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Introduce the NRF GPIO Pad Group device driver and binding. The
pad group device represents the GPIO pads (pins), contrary to a
GPIO controller, which is one of the many devices which can be
muxed to pads in the pad group.
The pad group belong to a power domain, which is not neccesarily the
same power domain as devices being muxed to the pads, like GPIO or
UART. If no ACTIVE device is using any of the pads in the pad
group, the pad groups power domain may be SUSPENDED. Before the pad
groups power domain is SUSPENDED, pad config retention must be
enabled to prevent the pads from loosing their state. That's what
this device driver manages. Once retained, the pad configs and
outputs are locked, even when their power domain is SUSPENDED.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Update NETC device nodes according to NETC driver update:
1. Added "nxp,imx-netc" compatible for netc driver.
2. Added all memory region in MMIO reg propertiy to let driver to handle
MMIO mapping for all memory region.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Update NETC device nodes according to NETC driver update:
1. Added "nxp,imx-netc" compatible.
2. Added all memory region in MMIO reg propertiy to let driver to handle
MMIO mapping for all memory region.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Update NETC device nodes according to NETC driver update:
1. Added NETC block control device node to handle block control
initialization in netc block driver.
2. Added "nxp,imx-netc" compatible for netc driver.
3. Added all memory region in MMIO reg propertiy to let driver to handle
MMIO mapping for all memory region.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
As reg property is not used by the driver and there is no proper address
could be assigned to it, so remove it.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Add NETC block driver, it could do some block memory region MMIO mapping
and also so dome block initialization, moved some netc related
configuration form board_init() to block driver so that it could be reused
between different platforms, although some configuration is different for
different platform, but put all NETC related code in the same driver to
make it easier to be maintained.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Update the driver to support DMA operations on L4 series devices, with
a shared DMA channel. Split channels do not work on these chips, since
there is no dedicated TX and RX channels on the DMA, so configuring two
channels with SDMMC as the peripheral results in a non-functional
configuration.
Fixes#91216.
Signed-off-by: Jordan Yates <jordan@embeint.com>
1. Update nxp irtc driver to fix issue in init and alarm function.
2. Update RTC device tree binding to support "share-counter".
3. Update RT700 dtsi to support rtc0 for cpu0 and rtc1 for cpu1.
4. Update readme.
5. Update unit test project conf for RT700.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
The driver gets FMC bank address using
`FMC_BANK1_<parent_register_value>` define.
This approach has some flaws:
- The parent (bank) register's value might not correspond
sequentially to the expected bank number.
For example: `STM32_FMC_NOSRAM_BANK3` maps to `FMC_BANK1_4`,
instead of `FMC_BANK1_3`.
- Some families don't even define the necessary `FMC_BANK1_x` macros.
To address this, the commit adds an optional `bank-address` property,
providing a direct way to define the FMC bank address for the driver.
Signed-off-by: Georgij Černyšiov <geo.cgv@gmail.com>
This files can be used by the 32-bit as well as 64-bit ARM
architectures. Move them into the dts/vendor/ti directory to
make the ISA independant.
All nodes located in the AM64x MAIN domain should have the main_
prefix. This makes it more clear where those pins are actually
located in the chip.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Add missing ranges to nrf54h20.dtsi reserved-memory. No translation
is required so ranges is set to <empty>.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add missing ranges to global_peripherals to explicitly translate
child addresses of global_peripherals in ram (0x2f000000).
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The Raspberry Pi Pico 2 uses a QMI flash controller, which differs from the
SSI controller used in the original Pico. Zephyr already has support for
the SSI controller, but lacked support for QMI.
This change adds the QMI flash controller implementation in the
flash_rpi_pico.c driver file. Additionally, the RP2350 SoC devicetree file
(rp2350.dtsi) has been updated to enable and describe the flash controller
for Pico 2.
Signed-off-by: Hanan Arshad <hananarshad619@gmail.com>
As a first step to enable the similar variants (e.g: ICM42686),
refactor common functionality into icm4268x files. As a result,
applications using the icm42688 will need to have both compatible
properties: "invensense,icm42688" and "invensense,icm4268x" defined.
In-tree boards have been modified to comply with this pattern.
This patch does not contain functional changes. The driver should
work the same as before.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
SPI(M/S)20 and SPIM(M/S)21 instances enable usage of pins on different
port, but require request for constant latency mode. Added
handling of such scenario in the driver. Added testcase
to cover it.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
UARTE20 and UARTE21 instances enable usage of pins on different
port, but require request for constant latency mode. Added
handling of such scenario in the driver. Added testcase
to cover it.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
update exti num-lines to depict total number of lines
add clocks entry to exti nodes of certain series
Signed-off-by: Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
