nordic,entropy-prng does not exist in Zephyr (it is part of NCS)
but we have in both the nordic,nrf-cracen-ctrdrbg which is
an actual source of true entropy and works with this SOC.
Let's use that instead.
Fixes failures to build targeting the nrf54lm20dk any test/sample
which uses the entropy driver.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The DT hierachy of the RT11xx series was somewhat incoherent. The boards
targets were directly including the series level DTSI with no SOC dtsi
in between, and there existed an SOC DTSI that had to be separately
included by a different board file, which didn't include the series DTSI
itself. It seems that this was only working if you included the files
exactly in the correct order in specific board files. Also, as a result
of this change, need to (correctly) define the cpu core only in the DTSI
for that core, instead of in the series generic dtsi, because that DTSI
was actually written with incorrect syntax due to duplicated node labels
on nodes right next to each other in the same file, and was relying on
other DTSI files to delete the duplicate nodes in order for it to build.
So overall this was a mess, needed cleanup.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
All this can be rolled into the single latency number.
Exit latency also triggers an additional timeout which
is not required for this SoC.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit adds a device-tree prop for the audio streaming
terminals to specify the bInterval values for the Isochronous
endpoints.
Signed-off-by: Victor Brzeski <vbrzeski@gmail.com>
AXISRAM3/4/5/6 nodes are added as children of their respective controller.
They're declared as "zephyr,memory-region" and disabled by default.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
1. add the ostimer
2. by default, the systick is used.
3. The ostimer could be tested with below configure in xxx.overlay:
&systick {
status = "disabled";
};
&ostimer0 {
status = "okay";
};
And below configure in xxx.conf:
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000
Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
Fixed typo whereby the description field started with `description: |`
instead of actual description.
Also added a proper title field while at it
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add driver for Microchip PolarFire SoC (MPFS) peripheral clock and soft
reset control.
Normally, the peripheral clocks and reset state are controlled by the
Hart Software Services (HSS) running on the Monitor processor. As an
alternative to using HSS services, applications can now enable the reset
controller in a device tree overly, for example:
&reset {
status = "okay";
};
&uart4 {
resets = <&reset MSS_RESET_ID_MMUART4>;
};
Embedded the reset controller node in system controller node.
Signed-off-by: Frank Kühndel <frank.kuehndel@embedded-brains.de>
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
Introduce a new USB Video Class (UVC) implementation from scratch.
It exposes a native Zephyr Video driver interface, allowing to call the
video_enqueue()/video_dequeue() interface. It will query the attached
video device to learn about the video capabilities, and use this to
configure the USB descriptors. At runtime, this UVC implementation will
send this device all the control requests, which it will send to the
attached video device. The application can poll the format currently
selected by the host, but will not be alerted when the host configures
a new format, as there is no video.h API for it yet.
Signed-off-by: Josuah Demangeon <me@josuah.net>
TI MSPM0 SoC series has General Purpose Timer and Advanced control timers
with Compare block which is used to generate time expiry and output
waveform like PWM. Add driver support for MSPM0 PWM output.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Add support to use DMA mode with cc23x0 SPI module. This consists in
specifying the DMA channels and peripherals.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Two DMA channels are assigned to TX and RX respectively:
- A TX DMA single request is asserted when there is space in the FIFO.
- A RX DMA single request is asserted when data is in the FIFO.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Adding supporting soc files for the k32lx platforms and updating
soc.yaml.
Signed-off-by: Ishraq Ibne Ashraf <ishraq.i.ashraf@gmail.com>
soc: nxp: kinetis: k32lx: Use device tree provided value
This clock frequency value will be defined in the board device tree.
Signed-off-by: Ishraq Ibne Ashraf <ishraq.i.ashraf@gmail.com>
