TI MSPM0 timer module has capture block used to capture timings of input
signal. Add a support for TI MSPM0 PWM capture.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Allow for users to define the sampling period via the sampleper
register on a per instance basis through device-tree properties.
The previous value was hard coded. The same value is now the default
value.
Signed-off-by: Mark Geiger <MarkGeiger@posteo.de>
We want to simplify the maintenance burden and confusion of having
more than one driver for the same kernel timer peripheral used on
all Microchip MEC parts. The XEC version of the driver was converted
register definitions in the driver. Register access is performed using
Zephyr sys_read/write architecture specific inline routines. Driver DT
YAML was updated to use phandle for the 32-bit basic timer used for
ARCH_HAS_CUSTOM_BUSY_WAIT support, basic timer max value property,
and GIRQ interrtup aggregator hardware information.
SoC part Kconfigs, chip level/board level DTSI updated to use the
unified driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
The leds-group-multicolor binding allows to combines several
monochromatic LEDs into one multi-color LED.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
This patch moves the label and color-mapping LED property definitions
from led-controller.yaml into led-node.yaml.
This allows to use these properties from a LED node which is not a
child node of a LED controller. This is preparatory work for adding
the leds-group-multicolor binding.
In addition this patch also removes the redundant "label" property
definitions in gpio-leds.yaml and pwm-leds.yaml. It is now included
from led-node.yaml.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
PIO interrupts are useful for some of the virtual
peripherals, so describe them in the DT.
This has no direct implications to existing drivers.
Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
Adding initial support for NXP FRDM K32L2B3 board.
Signed-off-by: Ishraq Ibne Ashraf <ishraq.i.ashraf@gmail.com>
dts: arm: nxp: Fix SRAM node name
Fix address part of the SRAM node name.
Change the SRAM start address definition to lower
case hexadecimal to be consistent.
Signed-off-by: Ishraq Ibne Ashraf <ishraq.i.ashraf@gmail.com>
Restructured counter and timer.
CTimer/Timer is now parent to pwm and counter.
Created PWM driver and tied to pwm and pwm-led
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
Moved pinctrl dtsi files for slwrb4250b and slwrb4255a from the soc
directory to the board directory as is done in other boards.
Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
Introduce subdirectory for xg1 socs.
As a porduct of this - `efm32_pg_1b.dtsi` and `efr32fg1p.dtsi` were
merged into `xg1.dtsi`.
Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
Add optional autostarts boolean to the quectel,bg95 binding and make
MODEM_CELLULAR_DEFINE_INSTANCE() use it through DT_PROP_OR().
Boards that carry a BG95-M3 Mini-PCIe card—or any other variant that
boots at VCC can now declare the property and skip the PWRKEY pulse,
while existing designs continue to behave unchanged.
Signed-off-by: Van Petrosyan <van.petrosyan@sensirion.com>
- Add sdif node to nxp_lpc55s2x_common.dtsi
- Add sdif pinmux configuration to LPCXpresso55S28 board
- Enable sdif and sdmmc disk on LPCXpresso55S28 board, providing SD card
storage capabilities.
Signed-off-by: David Christian Katheder <david.katheder@rohde-schwarz.com>
The existing driver requires setting multiple attributes in order to
work basic fetch/get reads. Simplify this by allowing the user to set
dts node properties based on the use-case.
As a result, basic settings results in the driver being up and running
from the start, one can just get sensor readings out of the box.
These still can be overriden at run-time if need be.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
1. enable sensor/nxp,lpcmp support
2. verified samples/sensor/mcux_lpcmp
3. update the mcux_lpcmp to support different port
Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
Update common flash test and jesd216 samples to work on the
APARD32690-SL board which has MX25U6432FM2I02 on-board.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Xilinx Window Watchdog Timer IP uses window mode.
Window watchdog timer(WWDT) contains closed(first) and open(second)
window with 32 bit width each. Write to the watchdog timer within
predefined window periods of time. This means a period that is not too
soon and a period that is not too late.
The WWDT error interrupts (IRQs) occur when the watchdog timer is not
serviced within the predefined window periods. These IRQs are routed to
the Processing System Manager (PSM) error accumulator module. The PSM is
responsible for managing power and system-level errors, generating a
System on Chip (SoC) reset when a WWDT error occurs. The system reset
event is signaled as a system error for the PSM firmware to handle and a
reset output signal to the MIO/EMIO.
Signed-off-by: Harini T <harini.t@amd.com>
rename gpio stepper to h bridge stepper
minor correction in stepper_stop, stepper_stop shall cancel all active
movements and should not be concerned about keeping the coils energized
or not, since that is a concern of a motion controller and not a stepper
driver.
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
Added driver and binding file for samd5x dac peripheral, the already
implemented dac_sam0.c lacks the configuration registers for this
microcontroller family and is fixed to only have one dac channel output,
also, the code gets too bulky when adding the samd5x dac configuration
using preprocessor directives that’s why I moved the implementation to its
own file.
Added dac to the supported list of same54_xpro.yaml, fixed Kconfig.samd5x
help spacing, added board defines to test_dac.c and test it out with
twister script on board.
Signed-off-by: Rafael Aldo Hernández Luna <aldo.hernandez@daikincomfort.com>
Adds a I2C+GPIO Target device binding for MCTP communication over I2C.
The binding requires an i2c bus and gpio pin, along with a specified I2C
and endpoint address pair. These are then used to create an MCTP binding
which can be used to communicate in a peer to peer manner among other
MCTP endpoints.
Each message transmit signals to the bus controller using a GPIO logical
high and is unset on transmission completion. Pending transmitters are
queued using a semaphore avoiding memcpy being needed to asynchronously
transmit mctp pktbufs.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Adds a custom MCTP binding for an I2C bus controller using GPIO signaling
for write requests rather than mode switching.
This binding operates a lot like the I3C binding specification DMTF has
for MCTP. The controller expects to receive interrupts (from GPIO pins)
and upon getting an interrupt read a message from the I2C target device.
The macro does a lot of the heavy lifting to setup all the state needed
for capturing GPIOs, being able to do asynchronous reads/writes, and
such. The entire controller works using state machines driven by
interrupts leading to low latency and clear ram costs.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
This patch adds the initial support for the OMAP Multi-Channel SPI. Some
things should be noted however:
- DMA xfers are not supported yet. Only PIO is supported as of now.
- Multi-Channel controller is not supported yet. Only single-channel
controller mode is supported, this means that the controller can xfer
messages with one slave at a time.
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
Fixed a bug where unconfigured clocks were connected to the can
interface in the device tree for SAM0, causing the interface to work
incorrectly. Fixed by adding the correct index when calling GENCTRL.
Also, the default divider has been reduced to 6 to allow setting
the bitrate to 500 kbps.
Tested on a canopennode sample on a board with an ATSAMC21E18A
microcontroller.
Signed-off-by: Vitaliy Livnov <vitaliy.livnov@devkit.agency>
- Change erase-block-size from 8192 to 4096 bytes to match
the 4 KB page size of STM32U3 flash.
- Update max-erase-time from 5 ms to 14 ms according to
datasheet specifications.
- These changes ensure correct flash erase behavior
and timing on STM32U3 devices.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
The Quectel BG95 binding currently marks mdm-power-gpios as
required. This fits designs that expose the PWRKEY pin, but the
BG95-M3 in Mini PCIe form-factor boots automatically via its
on-module “Automatic Power-On Circuit” and does not route
PWRKEY to the card edge.
Signed-off-by: Van Petrosyan <van.petrosyan@sensirion.com>
SENT, PSI5, Virtio where all recently added types. Add them to the
binding-types.txt file so that their full name can be displayed in the
documentation.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
LPTIM2 is enabled by default; disable it to avoid
the build failure:
"Error: Only one LPTIM instance should be enabled"
when LPTIM1 is also enabled in the DTS.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Description of parameters in st,control property didn't match the values
used in the code.
Modify the description to match with the current driver implementation.
Also add a description for reg property to help setting it properly and
add corresponding dt-bindings.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Move the IronSide APIs to soc/nordic from drivers/firmware since
these are vendor specific APIs. The header files are now included
from <nrf_ironside/*.h>. Adjust code that uses these APIs accordingly.
Also move the DT binding for "nordic,ironside-call" from
bindings/firmware to bindings/misc.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
