In the CONFIG_SPI_NOR_SFDP_MINIMAL configuration this value is hard
coded to 256 bytes. Make it configurable via devicetree.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
We currently have three keyboard scanning drivers in the code base
(npcx, it8xxx2 and mchp_xec, last two yet to be converted to input).
These have been largely copy pasted from each other and share a lot of
the same structure and code.
This PR lays a foundation to start decoupling feature from those drivers
into a common code base, and it is heavily inspired by the current
regulator common data/config one.
Feature wise this only moves the thread struct, stack and initialization
to the common code and declares the thread callback as the only API, but
the intent is to move as much code as possible in there an only abstract
device specific callbacks in the api structures.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This commit adds a GNSS driver for the Quectel LCX6G
series of GNSS modems (LC26G, LC76G, LC86G). It is
based on the modem subsystem, and the GNSS utilities
added in the two previous commits.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
The default is that the high time for open-drain clk is one
PPBAUD, which is typically very short. Some device require
a longer high time during the open-drain address phase so
add a property to allow device tree to override the default.
Signed-off-by: Mike J. Chen <mjchen@google.com>
The labels used in chosen node are not defined in dtsi file.
They are defined on board level and also chosen is already set there to
proper values.
Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
The header file defines macros that are not used in the boards dts but on
the SoC level. They should be include where they are used.
Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
for nucleo_stm32g0b1 board.
the HSI48 clock is the clock used by default for the USB controller,
however its default tolerance is not enough for the USB specification,
leading to some random errors depending on many factors, including the
upstream HUB or host.
this commit adds an option in the device tree to enable the STM32 Clock
recovery system (CRS) using USB SOF packet reception as a reference,
which brings the HSI48 within the required accuracy for USB transfers.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
Refactor the pinctrl nodes slightly so that the port devices are not
child of the main pinctrl node. This is because the pinctrl node is
being used as parent for pinctrl setting nodes itself, and having the
port nodes as child end up creating a circular depdency with the edt
child enumeration patch.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Refactor the pinctrl nodes slightly so that the port devices are not
child of the main pinctrl node. This is because the pinctrl node is
being used as parent for pinctrl setting nodes itself, and having the
port nodes as child end up creating a circular depdency with the edt
child enumeration patch.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Modified files (yaml, dts, overlay, and c) which were using spi-cpol
and spi-cpha to be compatible with the new structure.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Add support to set SPI clock polarity (CPOL), clock phase (CPHA), and
hold-on-cs in a dts file to get rid of using related macros in spi.c driver
since each board may work on a different SPI mode rather than the default
one (based on CPOL and CPHA).
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
This commit adds basic support for m5stacks M-Bus extenions port that is
support my core and core2 module.
Signed-off-by: Martin Kiepfer <m.kiepfer@teleschirm.org>
Allows device tree to enable usage of the controller feature
where HS clock is disabled when not in use, which is good
for reducing power consumption if MIPI DSI is mostly idle.
Signed-off-by: Mike J. Chen <mjchen@google.com>
The BCM2711 SoC exposes 58 GPIOs. The first 28 (bank 0) are accessible
to users via the 40-pin header, while the others (bank 1) are used for
controlling on-board peripherals.
This also update doc of `rpi_4b` board.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
No reason to declare it per node, as it is almostly shared by all
peripherals.
Also introduced `DT_FREQ_M` macro for better readability.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
This files has been changed as part of a refactoring in 13a87081b9.
Unfortunately the refactoring introduced few issues:
- usage of devicetree macros before their definition
- usage of pinctrl label before the definition of the corresponding node
- removal of few node overrides that are causing build errors
Unfortunately there's no board usptream using this specific dts file, so
the issue has not been caught in CI and was only found downstream.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This commit adds the RTC device to the following
atmel sam devicetrees:
- sam3x.dtsi
- sam4e.dtsi
- sam4s.dtsi
- same70.dtsi
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
Enable driver for intel lw uart.
Changes from review:
- refactor spinlock to inside of loop
- use menuconfig for kconfig
- add CONFIG_UART_INTEL_LW_AUTO_LINE_CTRL_POLL
Signed-off-by: Teoh Shi Lin <shi.lin.teoh@intel.com>
add basic sensor support for 3-axis accelerometer, currently
this driver support data acquisition and motion detection
features.
Signed-off-by: Karthikeyan Krishnasamy <karthikeyan@linumiz.com>
HAS_DTS has become a redundant option. All Zephyr architectures now
select this option, meaning devicetree has become a de-facto
requirement. In fact, if any board does not provide a devicetree
source, the build system uses an empty stub, meaning the devicetree
machinery always runs.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
STM32WB MCUs has two AES peripeherals. Add AES1 definition, AES2 must not
be used by application CPU core.
Signed-off-by: Lukasz Hawrylko <lukasz@hawrylko.pl>
Add wakeup_duration support. (WAKE_DUR in WAKE_UP_DUR)
Value is configurable through DT per instance.
Signed-off-by: Adrian Wojak <adrian.wojak@outlook.com>
Use a new property, "clock-mux" to select the clock mux for the SAI.
Previously, the clock mux was being selected using the "bits" specifier
of the "clocks" phandle property, which is not the purpose of this
specifier. This can be shown by the regression introduced by 5bebbb91,
which changed the "bits" field to the clock gate shift (which is the
intended meaning).
This incidently worked for the SAI1 and SAI3 peripherals, as the lower 2
bits of the correct clock source selection (0b10) are the same as the new
value placed in the "bit" specifier. For SAI2, the clock source was
switched to PLL3 PDF0 by this change.
To resolve this, use an explict "clock-mux" property for this selection.
Fixes#63541
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add a new SPI shim driver for Intel SoCs. Builds upon the SEDI bare
metal SPI driver in the hal-intel module.
Co-Authored-By: Kong Li <li.kong@intel.com>
Signed-off-by: Ye Weize <weize.ye@intel.com>
Adds a devicetree for describing common battery characteristics used
by multiple devices and subsystems.
Signed-off-by: Ricardo Rivera-Matos <ricardo.rivera-matos@cirrus.com>
MEC172X series SoCs share most IP but the -LJ series expands the PWM and
ADC channels available as well as defines extra pinctrl pins.
Separating these better to be able to simplify their inclusion and
driver code. Any board based on either the -SZ or -LJ package can just
include the mec172x<sz/lj> dtsi files for their specific package.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
This commits adds the DA14695 variant.
The main difference with the DA14699 is a smaller package with less
GPIO.
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
