Change the synchronization of RMC and GGA NMEA messages from a
timeout to matching their UTC timestamps.
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
Add driver for NXP nx20p3483 power path controller that can be used
to control and protect sink and source path of USB-C connector.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Add calls to the PPC API that enables and disables the sink and source
paths in the appropriate USB-C stack states.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Add support of voltage control to Renesas PFC driver. Voltage register
mappings have been added to r8a77951 and r8a77961 SoCs.
Allow 'power-source' property for 'renesas,rcar-pfc' node. This property
will be used for configuring IO voltage on appropriate pin. For now it
is possible to have only two voltages: 1.8 and 3.3.
Note: it is possible to change voltage only for SD/MMC pins on r8a77951
and r8a77961 SoCs.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Add definition of the DMIC to the RT5xx devicetree, including all
PDM channels.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Co-authored-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Add driver for NXP DMIC peripheral. This peripheral is present on the
iMX RT5xx and iMX RT6xx parts, as well as some LPC SOCs. The following
features are supported:
- up to 2 simultaneous channels of L/R PCM data (4 channels are not
supported due to limitations of the DMA engine)
- individual configuration of gain and filter parameters for each DMIC
channel input
The driver has been tested with up to 4 PCM data streams (2 L/R channels),
as well as the MEMS microphones present on the RT595 EVK.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Co-authored-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Extend api test suite to cover the new devicetree macros. This
includes extending the devicetree overlay with two new bindings:
- GPIO device which is also an interrupt controller
- interrupt holder using interrupts-extended to point to both
existing interrupt controller test_intc, and the newly added
GPIO device
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
add Master Inter-Data Idleness and
Master SS Idleness field. That fields
are integers.
Signed-off-by: Mustafa Abdullah Kus <mustafa.kus@sparsetechnology.com>
Add RGPIO gpio driver. This driver is used for i.MX93 and i.MX8ULP.
GPIO pinctrl, read/write and interrupt is supported. Runtime mmio
configuration is enabled, so no need for region definition in
mimx9/mmu_region.c
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
The wakeup-source is not used by the driver. Most probably this was
inadvertently left when copying the binding from pcf8523 driver.
Signed-off-by: Martin Jäger <martin@libre.solar>
Move the nRF comparator devicetree bindings from ADC to sensors, where the
rest of the comparator bindings are placed.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Since the pins of bt-spi instance are wired internally in the chip, it will
make sense to move the definition to soc dts so no need for every board
using the chip to redefine the same.
Signed-off-by: Aaron Ye <aye@ambiq.com>
SOC_ESP32_NET is now SOC_ESP32_APPCPU, following espressif's
naming convention in the same manner as ESP32S3 app cpu.
SOC_ESP32_APPCU is now a subset of SOC_SERIES_ESP32.
This commit also changes the necessary files, samples and tests
for bisect purposes.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Add support for M5Stack AtomS3 Lite development board.
The AtomS3 Lite is a smaller version of the AtomS3 that
features only a StatusLED and no LCD display.
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
A 1KHz counter is present in the LPC RTC.
Add support for this counter to get better
resolution for certain applications.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
A 1KHz counter is also available inside the NXP LPC RTC
block. Add a binding to support that counter.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit implements `otPlatResetToBootloader` in two ways:
- trigger reset to bootloader using boot mode retention API
- trigger reset to bootloader by triggering GPIO pin (applicable
for nRF52840 Dongle)
Signed-off-by: Maciej Baczmanski <maciej.baczmanski@nordicsemi.no>
Use the common io-channel-cells name "input" instead of "channel" to make
this binding work with the various ADC DT macros.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This is a driver targetting the Bosch BMA 4-series accelerometers. It
has been specifically developed for the BMA422 but should be compatible
with others in that line, excepting the BMA400. Supports key attributes
and async RTIO one-shot operation. I2C operation is supported, with
stubs for a SPI implementation provided for future improvement.
Signed-off-by: Tristan Honscheid <honscheid@google.com>
In preparation for supporting all synchronization modes, this
commit introduces the rx_sync_mode/tx_sync_mode DTS properties.
Using these, the user will be able to specify which synchronization
mode the SAI should use.
At the moment, the driver does nothing with the values from
said properties but still checks if their values are sane
(i.e: it checks if the directions are both in SYNC mode which
is forbidden). By default, if "rx_sync_mode" or "tx_sync_mode"
is not specified, the direction will be set to ASYNC mode.
As such, below one may find a couple of valid examples
depicting this idea:
tx_sync_mode = <0>;
rx_sync_mode = <0>;
is the same as not specifying any of the properties,
tx_sync_mode = <1>;
rx_sync_mode = <0>;
is the same as:
tx_sync_mode = <1>;
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add support for specifying the domain/kernel clock along with a common
clock divider for the STM32H7 CAN controller driver via devicetree.
Previously, the driver only supported using the PLL1_Q clock for
domain/kernel clock, but now the driver defaults to the HSE clock, which is
the chip default. Update existing boards to continue to use the PLL1_Q
clock.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Some MCU have limitations with GPIO interrupts. Add a polling mode to
the gpio-keys driver to support those cases.
This required a bit of a refactoring of the driver data structure to add
a instance wide data, and move the pin specific pointer in the config
structure.
For polling, reuse the button 0 delayed work so we minimize the resource
waste, the two work handler functions are only referenced when used so
at least those are discarded automatically if no instance needs them.
Fix a bug in the PM structure instantiation as well.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add an input driver to read data from an analog device, such as a
thumbstick, connected to an ADC channel, and report it as an input
device.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add driver that based on RPI-PICO's PIO feature for ws2812.
This driver can handle WS2812 or compatible LED strips.
The single PIO node can handle up to 4 strips.
Any pins that can be configured for PIO can be used for strips.
I verified the samples/driver/led_ws2812 sample
working with WS2812(144 pcs) led strip using following patches.
- samples/drivers/led_ws2812/boards/rpi_pico.overlay
```
/ {
aliases {
led-strip = &ws2812;
};
};
&pinctrl {
ws2812_pio0_default: ws2812_pio0_default {
ws2812 {
pinmux = <PIO0_P21>;
};
};
};
&pio0 {
status = "okay";
pio-ws2812 {
compatible = "worldsemi,ws2812-rpi_pico-pio";
status = "okay";
pinctrl-0 = <&ws2812_pio0_default>;
pinctrl-names = "default";
bit-waveform = <3>, <3>, <4>;
ws2812: ws2812 {
status = "okay";
output-pin = <21>;
chain-length = <144>;
color-mapping = <LED_COLOR_ID_GREEN
LED_COLOR_ID_RED
LED_COLOR_ID_BLUE>;
reset-delay = <280>;
frequency = <800000>;
};
};
};
```
- samples/drivers/led_ws2812/boards/rpi_pico.conf
```
CONFIG_WS2812_STRIP_RPI_PICO_PIO=y
```
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Switch to using named IRQs as index-based access makes no guarantees about
devicetree interrupt order.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Switch to using named IRQs as index-based access makes no guarantees about
devicetree interrupt order.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Consistently use "int0" and "int1" as interrupt names for CAN controllers
based on the Bosch M_CAN IP core. This aligns with the upstream Linux
bindings.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Use the common io-channel-cells name "input" instead of "positive" and
"negative" to make this binding work with the various ADC DT macros.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This is in preparation for xmc4xxx mdio/ethernet patch set. In the
ethernet drivers, the DMA memory (including descriptor and buffers)
must live in dsram1 or dsram2.
Currently, in xmc47_relax_kit the RAM is the psram1 region meaning
that DMA transfers will not work. Switch to using dsram regions instead.
Also, merge dsram1 and dsram2 into a single region since they are
contiguous.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
