for Renesas RA family
Add SPI device node to support SCI B SPI driver on Renesas RA SoCs:
- ra8x1.dtsi
- ra8x2.dtsi
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Support for the Silabs EFM32TG-STK3300 Starter Kit.
Board features:
* EFM32TG840F32 MCU with 32 kB flash and 4 kB RAM
* Advanced Energy Monitoring
* Real-time, accurate energy and power profiling
* Light, LC and touch sensors
* 8 x 20 LCD
* SEGGER J-Link debugger
Signed-off-by: Lukas Woodtli <woodtli.lukas@gmail.com>
* ARM Cortex-M3 processor
* Up to 32 kB Flash and 4 kB RAM memory
* Energy efficient and autonomous peripherals
* Ultra low power Energy Modes
* Fast wake-up
Signed-off-by: Lukas Woodtli <woodtli.lukas@gmail.com>
Deprecate the 'ETH_SAM_GMAC_MAC_I2C_EEPROM' for the 'mac-eeprom' option,
Limite it to be used when there's only one activated GMAC instance.
Signed-off-by: Tony Han <tony.han@microchip.com>
As jumbo frame size is not supported by the networking subsystem, only
max_frame_size 1518 and 1536 can be used. The Frame size 1536 would
allow for packets with a vlan tag, so enable GMAC_NCFGR_MAXFS when
NET_VLAN is configured.
Signed-off-by: Tony Han <tony.han@microchip.com>
For ESP32 devices, not all boards are required to configure pinctrl
for signals like Chip Detect (CD) and Write Protect (WP). Remove
pinctrl property as mandatory.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
The added stm32-adc properties in c21cdd8569 ("dts: bindings: adc:
stm32: add new properties to simplify the driver") were missing from adc2
within the stm32n6.dtsi.
Since adc1 and adc2 are almost identical, just copy the missing properties
from adc1 which was fixed up as part of 5f0c63ea35 ("dts: arm: st: fill
out adc nodes with the new properties").
This fixes compilation when using adc2:
```
devicetree error: 'st,adc-internal-regulator' is marked as required in
'properties:' in [...]/zephyr/dts/bindings/adc/st,stm32n6-adc.yaml, but
does not appear in <Node /soc/adc@50022100 in
[...]/zephyr/dts/arm/st/n6/stm32n6.dtsi:456>
```
Signed-off-by: Emil Dahl Juhl <emil@s16s.ai>
The CMU clock controller node for HFRCO was wrongly interpreted
as a PLL reference clock. This prevented configuring the HFRCO
in open-loop mode. Since the node isn't used for anything,
remove it as a minimal stopgap solution.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This commit fixes CYW20829 that was broken on main after the
below commit
https://github.com/zephyrproject-rtos/zephyr/pull/95333
The root cause of the issue is that, bootstrap section is located at
the end of the RAM. So the start address of the section needs to
be calculated based on the size of the section.
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in `.dts` and `.dtsi` files within the `boards` and `dts` directories.
Note: To pass CI compliance checks, also fix the formatting in
`/dts/arm/infineon/edge/pse84/system_clocks.dtsi`
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Fixes some recently introduced issues with this file whereby
addresses were wrongly using global addresses instead of relative
to the parent node and whereby parent node names were not used
when they should have been
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
`sram0_ns_modem` and `sram0_ns_app` are child nodes of `sram0_ns`, not
`sram`. Addresses should be relative to the former, not the later.
Signed-off-by: Jordan Yates <jordan@embeint.com>
The h7rs option byte default setting configures the AXI SRAM1-4 as one
contiguous memory, sram0 can therefore be increased to 456k (3x128k + 72k).
The .yaml files of the boards nucleo_h7s3l8 and stm32h7s78_dk are adjusted
accordingly.
Signed-off-by: Thomas Decker <decker@jb-lighting.de>
This probably should have been caught much earlier, but well, here we
are. The original license came from the following linux dt that
BeagleBoard.org uses [0]. However, due to differences between linux and
zephyr dt and the fact that zephyr does not yet support most of the
devices on this soc, the only lines same between the two files are the
`status = "disabled";`, and some of the address (not all since things
like GPIO are handled differently). Keeping that in mind, this file
should never have used that license or have TI Copyright.
If it's too late to change the license now, we can probably add this
file to exceptions, since the current license of the file, i.e. GPL-2.0
and MIT should cover all cases where Apache-2 can be used. Again,
apologies since there was no reason for this file to use the dual
license.
[0]:https://github.com/beagleboard/BeagleBoard-DeviceTrees/blob/v6.12.x-Beagle/src/arm64/ti/k3-am62-main.dtsi
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
This fix addresses the issue encountered when power management (pm)
is enabled, as the PWM test suites utilize the GPIO driver, which
now incorporates the latest power domain enhancements and requires
CONFIG_POWER_DOMAIN to be enabled. Power domain functionality
manages device power actions such as turning on and off.
Accordingly, the pm device support for the pwm_silabs_siwx91x
driver has been updated to align with the recent power domain
improvements.
Signed-off-by: S Mohamed Fiaz <Fiaz.Mohamed@silabs.com>
- Correct address and size for sdram-controller node
- Move sdram-controller node from r7fa8d1xh.dtsi to ra8x1.dtsi,
since all RA8x1 devices have this hardware IP
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
This patch fixes a bug where the siwg917 SoC didn't enter deep sleep
even when the CONFIG_PM Kconfig option was selected, due to the
default power state of the network coprocessor.
Users should only need to activate the CONFIG_PM Kconfig option
when they want to enable power management and be able to deep
sleep by default.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Clarify that the AMD Xilinx PS Triple Timer Counter (TTC) is used in both
Zynq UltraScale+ MPSoC (ZynqMP) and Versal platforms. Update the device
tree binding description and Kconfig accordingly.
Also, rephrase the Kconfig help text to fix grammar issues and improve
clarity.
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Uses the correct way to partition memory as per the linux binding,
also fixes names which were not compliant with the zephyr
devicetree guidelines
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Uses the correct way to partition memory as per the linux binding,
also fixes names which were not compliant with the zephyr
devicetree guidelines
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Updates the Port DTS nodes to use microchip gpio g1 driver.
Updates the file structure as per the ordering information.
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
1.Add "mux-1-dc-0-div" and "mux-2-dc-0-div" property
in mc_cgm device tree for STM clock divider setting
and set these properties in frdm_mcxe31b.dts
2.Enable STM peripheral clock in mc_cgm_clock_control_on
function
3.Support to get STM frequency from mc_cgm_get_subsys_rate
function
4.Configure STM clock in mc_cgm_init function
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Adds the pinctrl node and encapsulates the port nodes within
the pinctrl node for pic32cx sg series of socs.
Signed-off-by: Muhammed Asif <muhammed.asif@microchip.com>
Added waveshare dsi panel driver. It is on I2C bus.
Signed-off-by: Winteri Wang <dongjie.wang@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Ruoshan Shi <ruoshan.shi@nxp.com>
Added mcux_lcdifv3 driver and enabled runtime mmio configuration.
Signed-off-by: Winteri Wang <dongjie.wang@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Ruoshan Shi <ruoshan.shi@nxp.com>
Add support for KSZ9131 (Gigabit Ethernet Transceiver with RGMII Support).
As first starter, 100MBit/s mode is tested.
https://www.microchip.com/en-us/product/ksz9131
Signed-off-by: Tony Han <tony.han@microchip.com>
