soc: intel: renamed soc from ace30_ptl to ace30

Renamed soc from ace30_ptl to ace30.
We were previously using the wrong soc name.
The correct name is ace30.

There is only one ptl platform, but there can be several ace30 platforms.

Signed-off-by: Grzegorz Bernat <grzegorzx.bernat@intel.com>
This commit is contained in:
Grzegorz Bernat 2024-09-23 13:14:55 +02:00 committed by Alberto Escolar
commit a654bfbdfa
29 changed files with 740 additions and 44 deletions

View file

@ -8,5 +8,5 @@ config BOARD_INTEL_ADSP
select SOC_INTEL_ACE15_MTPM if BOARD_INTEL_ADSP_ACE15_MTPM_SIM
select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL
select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL_SIM
select SOC_INTEL_ACE30_PTL if BOARD_INTEL_ADSP_ACE30_PTL
select SOC_INTEL_ACE30_PTL if BOARD_INTEL_ADSP_ACE30_PTL_SIM
select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL
select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL_SIM

View file

@ -11,6 +11,8 @@ boards:
- name: ace20_lnl
variants:
- name: 'sim'
- name: ace30_ptl
- name: ace30
variants:
- name: 'sim'
- name: 'ptl'
variants:
- name: 'sim'

View file

@ -0,0 +1,12 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_MAIN_STACK_SIZE=4096
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_BUILD_OUTPUT_BIN=n
CONFIG_DAI_SSP_HAS_POWER_CONTROL=y
CONFIG_DCACHE_LINE_SIZE=64

View file

@ -1,4 +1,4 @@
identifier: intel_adsp/ace30_ptl
identifier: intel_adsp/ace30/ptl
name: ACE 3.0 Panther Lake Audio DSP
type: mcu
arch: xtensa

View file

@ -1,4 +1,4 @@
identifier: intel_adsp/ace30_ptl/sim
identifier: intel_adsp/ace30/ptl/sim
name: ACE 3.0 Panther Lake Audio DSP
type: sim
simulation: custom

View file

@ -160,7 +160,7 @@ static inline void dai_dmic_release_ownership(const struct dai_intel_dmic *dmic)
static inline uint32_t dai_dmic_base(const struct dai_intel_dmic *dmic)
{
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30)
return dmic->hdamldmic_base;
#else
return dmic->shim_base;
@ -173,7 +173,7 @@ static inline void dai_dmic_set_sync_period(uint32_t period, const struct dai_in
uint32_t val = CONFIG_DAI_DMIC_HW_IOCLK / period - 1;
uint32_t base = dai_dmic_base(dmic);
/* DMIC Change sync period */
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30)
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | FIELD_PREP(DMICSYNC_SYNCPRD, val),
base + DMICSYNC_OFFSET);
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_SYNCPU,
@ -287,7 +287,7 @@ static void dai_dmic_irq_handler(const void *data)
static inline void dai_dmic_dis_clk_gating(const struct dai_intel_dmic *dmic)
{
/* Disable DMIC clock gating */
#if (CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL)
#if (CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30)
sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) | DMICLVSCTL_DCGD),
dmic->vshim_base + DMICLVSCTL_OFFSET);
#else
@ -299,7 +299,7 @@ static inline void dai_dmic_dis_clk_gating(const struct dai_intel_dmic *dmic)
static inline void dai_dmic_en_clk_gating(const struct dai_intel_dmic *dmic)
{
/* Enable DMIC clock gating */
#if (CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL)
#if (CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30)
sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) & ~DMICLVSCTL_DCGD),
dmic->vshim_base + DMICLVSCTL_OFFSET);
#else /* All other CAVS and ACE platforms */
@ -313,7 +313,7 @@ static inline void dai_dmic_program_channel_map(const struct dai_intel_dmic *dmi
const struct dai_config *cfg,
uint32_t index)
{
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30)
uint16_t pcmsycm = cfg->link_config;
uint32_t reg_add = dmic->shim_base + DMICXPCMSyCM_OFFSET + 0x0004*index;
@ -322,7 +322,7 @@ static inline void dai_dmic_program_channel_map(const struct dai_intel_dmic *dmi
ARG_UNUSED(dmic);
ARG_UNUSED(cfg);
ARG_UNUSED(index);
#endif /* defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) */
#endif /* defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) */
}
static inline void dai_dmic_en_power(const struct dai_intel_dmic *dmic)
@ -332,7 +332,7 @@ static inline void dai_dmic_en_power(const struct dai_intel_dmic *dmic)
sys_write32((sys_read32(base + DMICLCTL_OFFSET) | DMICLCTL_SPA),
base + DMICLCTL_OFFSET);
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30)
while (!(sys_read32(base + DMICLCTL_OFFSET) & DMICLCTL_CPA)) {
k_sleep(K_USEC(100));
}

View file

@ -173,7 +173,7 @@ struct dai_intel_dmic {
/* hardware parameters */
uint32_t reg_base;
uint32_t shim_base;
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30)
uint32_t hdamldmic_base;
uint32_t vshim_base;
#endif

View file

@ -282,7 +282,7 @@ static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic, const int c
static inline void dai_dmic_clock_select_set(const struct dai_intel_dmic *dmic, uint32_t source)
{
uint32_t val;
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) /* ACE 2.0,3.0 */
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) /* ACE 2.0,3.0 */
val = sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET);
val &= ~DMICLVSCTL_MLCS;
val |= FIELD_PREP(DMICLVSCTL_MLCS, source);
@ -303,7 +303,7 @@ static inline void dai_dmic_clock_select_set(const struct dai_intel_dmic *dmic,
static inline uint32_t dai_dmic_clock_select_get(const struct dai_intel_dmic *dmic)
{
uint32_t val;
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) /* ACE 2.0,3.0 */
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) /* ACE 2.0,3.0 */
val = sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET);
return FIELD_GET(DMICLVSCTL_MLCS, val);
#else

View file

@ -269,7 +269,7 @@ struct dai_intel_ipc4_ssp_mclk_config_2 {
} __packed;
struct dai_intel_ipc4_ssp_driver_config {
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
#ifdef CONFIG_SOC_INTEL_ACE30
struct dai_intel_ipc4_ssp_config_ver_3_0 i2s_config;
#else
struct dai_intel_ipc4_ssp_config i2s_config;

View file

@ -800,7 +800,7 @@ static void dai_ssp_pm_runtime_en_ssp_power(struct dai_intel_ssp *dp, uint32_t s
ret = dai_ssp_poll_for_register_delay(dai_ip_base(dp) + I2SLCTL_OFFSET,
I2SLCTL_CPA(ssp_index), I2SLCTL_CPA(ssp_index),
DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE);
#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL
#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30
sys_write32(sys_read32(dai_hdamlssp_base(dp) + I2SLCTL_OFFSET) |
I2SLCTL_SPA(ssp_index),
dai_hdamlssp_base(dp) + I2SLCTL_OFFSET);
@ -835,7 +835,7 @@ static void dai_ssp_pm_runtime_dis_ssp_power(struct dai_intel_ssp *dp, uint32_t
I2SLCTL_CPA(ssp_index), 0,
DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE);
#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL
#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30
sys_write32(sys_read32(dai_hdamlssp_base(dp) + I2SLCTL_OFFSET) & (~I2SLCTL_SPA(ssp_index)),
dai_hdamlssp_base(dp) + I2SLCTL_OFFSET);
@ -873,7 +873,7 @@ static void dai_ssp_program_channel_map(struct dai_intel_ssp *dp,
/* Program HDA input stream parameters */
sys_write16((pcmsycm & 0xffff), reg_add);
}
#elif defined(CONFIG_SOC_INTEL_ACE30_PTL)
#elif defined(CONFIG_SOC_INTEL_ACE30)
const struct dai_intel_ipc4_ssp_configuration_blob_ver_3_0 *blob30 = spec_config;
const struct dai_intel_ipc4_ssp_configuration_blob *blob = spec_config;
uint64_t time_slot_map = 0;
@ -930,7 +930,7 @@ static void dai_ssp_empty_tx_fifo(struct dai_intel_ssp *dp)
* SSSR_TNF is cleared when TX FIFO is empty or full,
* so wait for set TNF then for TFL zero - order matter.
*/
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
#ifdef CONFIG_SOC_INTEL_ACE30
ret = dai_ssp_poll_for_register_delay(dai_base(dp) + SSMODyCS(dp->tdm_slot_group),
SSMODyCS_TNF, SSMODyCS_TNF,
DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE);
@ -959,7 +959,7 @@ static void dai_ssp_empty_tx_fifo(struct dai_intel_ssp *dp)
}
}
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
#ifdef CONFIG_SOC_INTEL_ACE30
static void ssp_empty_rx_fifo_on_start(struct dai_intel_ssp *dp)
{
uint32_t retry = DAI_INTEL_SSP_RX_FLUSH_RETRY_MAX;
@ -1191,7 +1191,7 @@ static int dai_ssp_bclk_prepare_enable(struct dai_intel_ssp *dp)
mdiv = ft[DAI_INTEL_SSP_DEFAULT_IDX].freq / ssp_plat_data->params.bclk_rate;
#endif
#ifndef CONFIG_SOC_INTEL_ACE30_PTL
#ifndef CONFIG_SOC_INTEL_ACE30
if (need_ecs) {
sscr0 |= SSCR0_ECS;
}
@ -1724,7 +1724,7 @@ static int dai_ssp_set_config_tplg(struct dai_intel_ssp *dp, const struct dai_co
sys_write32(sspsp2, dai_base(dp) + SSPSP2);
sys_write32(ssioc, dai_base(dp) + SSIOC);
sys_write32(ssto, dai_base(dp) + SSTO);
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
#ifdef CONFIG_SOC_INTEL_ACE30
for (uint32_t idx = 0; idx < I2SIPCMC; ++idx) {
sys_write64(sstsa, dai_base(dp) + SSMODyTSA(idx));
}
@ -1777,7 +1777,7 @@ clk:
ssp_plat_data->clk_active |= SSP_CLK_BCLK_ES_REQ;
if (enable_sse) {
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
#ifdef CONFIG_SOC_INTEL_ACE30
dai_ssp_update_bits(dp, SSMIDyCS(dp->tdm_slot_group),
SSMIDyCS_RSRE, SSMIDyCS_RSRE);
dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group),
@ -1806,7 +1806,7 @@ clk:
LOG_INF("hw_free stage: releasing BCLK clocks for SSP%d...",
dp->dai_index);
if (ssp_plat_data->clk_active & SSP_CLK_BCLK_ACTIVE) {
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
#ifdef CONFIG_SOC_INTEL_ACE30
for (uint32_t idx = 0; idx < I2SOPCMC; ++idx) {
dai_ssp_update_bits(dp, SSMODyCS(idx), SSMODyCS_TSRE, 0);
}
@ -1985,7 +1985,7 @@ static int dai_ssp_parse_tlv(struct dai_intel_ssp *dp, const uint8_t *aux_ptr, s
~I2CLCTL_MLCS(0x7)) |
I2CLCTL_MLCS(link->clock_source), dai_ip_base(dp) +
I2SLCTL_OFFSET);
#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL
#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30
sys_write32((sys_read32(dai_i2svss_base(dp) + I2SLCTL_OFFSET) &
~I2CLCTL_MLCS(0x7)) |
I2CLCTL_MLCS(link->clock_source),
@ -2065,7 +2065,7 @@ static int dai_ssp_set_clock_control_ver_1(struct dai_intel_ssp *dp,
return 0;
}
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
#ifdef CONFIG_SOC_INTEL_ACE30
static void dai_ssp_set_reg_config(struct dai_intel_ssp *dp, const struct dai_config *cfg,
const void *spec_config)
{
@ -2184,7 +2184,7 @@ static int dai_ssp_set_config_blob(struct dai_intel_ssp *dp, const struct dai_co
struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp);
int err;
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
#ifdef CONFIG_SOC_INTEL_ACE30
dp->tdm_slot_group = cfg->tdm_slot_group;
#endif
@ -2322,7 +2322,7 @@ static void dai_ssp_start(struct dai_intel_ssp *dp, int direction)
/* enable DMA */
#if CONFIG_SOC_INTEL_ACE30_PTL
#if CONFIG_SOC_INTEL_ACE30
if (direction == DAI_DIR_PLAYBACK) {
dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group),
SSMODyCS_TSRE, SSMODyCS_TSRE);
@ -2392,7 +2392,7 @@ static void dai_ssp_stop(struct dai_intel_ssp *dp, int direction)
if (direction == DAI_DIR_CAPTURE &&
dp->state[DAI_DIR_CAPTURE] != DAI_STATE_PRE_RUNNING) {
LOG_INF("SSP%d RX", dp->dai_index);
#if CONFIG_SOC_INTEL_ACE30_PTL
#if CONFIG_SOC_INTEL_ACE30
dai_ssp_update_bits(dp, SSMIDyCS(dp->tdm_slot_group), SSMIDyCS_RXEN, 0);
dai_ssp_update_bits(dp, SSMIDyCS(dp->tdm_slot_group), SSMIDyCS_RSRE, 0);
#else
@ -2407,7 +2407,7 @@ static void dai_ssp_stop(struct dai_intel_ssp *dp, int direction)
if (direction == DAI_DIR_PLAYBACK &&
dp->state[DAI_DIR_PLAYBACK] != DAI_STATE_PRE_RUNNING) {
LOG_INF("SSP%d TX", dp->dai_index);
#if CONFIG_SOC_INTEL_ACE30_PTL
#if CONFIG_SOC_INTEL_ACE30
dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group), SSMODyCS_TSRE, 0);
dai_ssp_empty_tx_fifo(dp);
dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group), SSMODyCS_TXEN, 0);

View file

@ -52,7 +52,7 @@
#include "ssp_regs_v1.h"
#elif defined(CONFIG_SOC_INTEL_ACE20_LNL)
#include "ssp_regs_v2.h"
#elif defined(CONFIG_SOC_INTEL_ACE30_PTL)
#elif defined(CONFIG_SOC_INTEL_ACE30)
#include "ssp_regs_v3.h"
#else
#error "Missing ssp definitions"
@ -116,7 +116,7 @@ struct dai_intel_ssp_plat_data {
uint32_t base;
uint32_t ip_base;
uint32_t shim_base;
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30)
uint32_t hdamlssp_base;
uint32_t i2svss_base;
#endif

View file

@ -235,7 +235,7 @@ int intel_adsp_hda_dma_status(const struct device *dev, uint32_t channel,
stat->pending_length = used;
stat->free = unused;
#if CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL
#if CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30
/* Linear Link Position via HDA-DMA is only supported on ACE2 or newer */
if (cfg->direction == MEMORY_TO_PERIPHERAL || cfg->direction == PERIPHERAL_TO_MEMORY) {
uint32_t tmp;

View file

@ -0,0 +1,682 @@
/*
* Copyright (c) 2024 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <xtensa/xtensa.dtsi>
#include <mem.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "cdns,tensilica-xtensa-lx7";
reg = <0>;
cpu-power-states = <&d0i3 &d3>;
i-cache-line-size = <64>;
d-cache-line-size = <64>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "cdns,tensilica-xtensa-lx7";
reg = <1>;
cpu-power-states = <&d0i3 &d3>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "cdns,tensilica-xtensa-lx7";
reg = <2>;
cpu-power-states = <&d0i3 &d3>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "cdns,tensilica-xtensa-lx7";
reg = <3>;
cpu-power-states = <&d0i3 &d3>;
};
cpu4: cpu@4 {
device_type = "cpu";
compatible = "cdns,tensilica-xtensa-lx7";
reg = <4>;
cpu-power-states = <&d0i3 &d3>;
};
};
power-states {
d0i3: idle {
compatible = "zephyr,power-state";
power-state-name = "runtime-idle";
min-residency-us = <200>;
exit-latency-us = <100>;
};
/* PM_STATE_SOFT_OFF can be entered only by calling pm_state_force.
* The procedure is triggered by IPC from the HOST (SET_DX).
*/
d3: off {
compatible = "zephyr,power-state";
power-state-name = "soft-off";
min-residency-us = <0>;
exit-latency-us = <0>;
status = "disabled";
};
};
sram0: memory@a0020000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0xa0020000 DT_SIZE_K(4608)>;
};
sram0virtual: virtualmemory@a0020000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0xa0020000 DT_SIZE_K(8192)>;
};
sram1: memory@a0000000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0xa0000000 DT_SIZE_K(64)>;
};
sysclk: system-clock {
compatible = "fixed-clock";
clock-frequency = <38400000>;
#clock-cells = <0>;
};
clkctl: clkctl {
compatible = "intel,adsp-shim-clkctl";
adsp-clkctl-clk-wovcro = <0>;
adsp-clkctl-clk-ipll = <1>;
adsp-clkctl-freq-enc = <0xc 0x4>;
adsp-clkctl-freq-mask = <0x0 0x0>;
adsp-clkctl-freq-default = <1>;
adsp-clkctl-freq-lowest = <0>;
wovcro-supported;
};
audioclk: audio-clock {
compatible = "fixed-clock";
clock-frequency = <24576000>;
#clock-cells = <0>;
};
pllclk: pll-clock {
compatible = "fixed-clock";
clock-frequency = <96000000>;
#clock-cells = <0>;
};
IMR1: memory@A1000000 {
compatible = "intel,adsp-imr";
reg = <0xA1000000 DT_SIZE_M(16)>;
block-size = <0x1000>;
zephyr,memory-region = "IMR1";
};
soc {
l1ccap: l1ccap@3fe80080 {
compatible = "intel,adsp-l1ccap";
reg = <0x3fe80080 0x4>;
};
l1ccfg: l1ccfg@3fe80084 {
compatible = "intel,adsp-l1ccfg";
reg = <0x3fe80084 0x4>;
};
l1pcfg: l1pcfg@3fe80088 {
compatible = "intel,adsp-l1pcfg";
reg = <0x3fe80088 0x4>;
};
lsbpm: lsbpm@71d80 {
compatible = "intel,adsp-lsbpm";
reg = <0x71d80 0x0008>;
};
hsbpm: hsbpm@17a800 {
compatible = "intel,adsp-hsbpm";
reg = <0x17a800 0x0008>;
};
core_intc: core_intc@0 {
compatible = "cdns,xtensa-core-intc";
reg = <0x00 0x400>;
interrupt-controller;
#interrupt-cells = <3>;
};
hdamlddmic: hdamlddmic@cc0 {
compatible = "intel,adsp-hda-dmic-cap";
reg = <0xcc0 0x40>;
status = "okay";
};
dmic0: dai-dmic0@10100 {
compatible = "intel,dai-dmic";
reg = <0x10100 0x8000>;
shim = <0x10000>;
fifo = <0x0008>;
interrupts = <0x08 0 0>;
interrupt-parent = <&ace_intc>;
power-domain = <&hub_ulp_domain>;
};
dmic1: dai-dmic1@10100 {
compatible = "intel,dai-dmic";
reg = <0x10100 0x8000>;
shim = <0x10000>;
fifo = <0x0108>;
interrupts = <0x08 0 0>;
interrupt-parent = <&ace_intc>;
power-domain = <&hub_ulp_domain>;
};
dmicvss: dmicvss@16000 {
compatible = "intel,adsp-dmic-vss";
reg = <0x16000 0x2000>;
status = "okay";
};
sspbase: ssp_base@28000 {
compatible = "intel,ssp-sspbase";
reg = <0x28000 0x1000>;
};
hdamlssp: hdamlssp@d00 {
compatible = "intel,adsp-hda-ssp-cap";
reg = <0xD00 0x40>;
status = "okay";
};
ssp0: ssp@28100 {
compatible = "intel,ssp";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00028100 0x1000
0x00079C00 0x200>;
i2svss = <0x00028C00 0x1000>;
interrupts = <0x00 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 1
&hda_link_in 1>;
dma-names = "tx", "rx";
ssp-index = <0>;
power-domain = <&io0_domain>;
status = "okay";
ssp00: ssp@0 {
compatible = "intel,ssp-dai";
reg = <0x0>;
status = "okay";
};
ssp01: ssp@1 {
compatible = "intel,ssp-dai";
reg = <0x1>;
status = "okay";
};
ssp02: ssp@2 {
compatible = "intel,ssp-dai";
reg = <0x2>;
status = "okay";
};
ssp03: ssp@3 {
compatible = "intel,ssp-dai";
reg = <0x3>;
status = "okay";
};
ssp04: ssp@4 {
compatible = "intel,ssp-dai";
reg = <0x4>;
status = "okay";
};
ssp05: ssp@5 {
compatible = "intel,ssp-dai";
reg = <0x5>;
status = "okay";
};
ssp06: ssp@6 {
compatible = "intel,ssp-dai";
reg = <0x6>;
status = "okay";
};
ssp07: ssp@7 {
compatible = "intel,ssp-dai";
reg = <0x7>;
status = "okay";
};
};
ssp1: ssp@29100 {
compatible = "intel,ssp";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00029100 0x1000
0x00079C00 0x200>;
i2svss = <0x00029C00 0x1000>;
interrupts = <0x01 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 2
&hda_link_in 2>;
dma-names = "tx", "rx";
ssp-index = <1>;
power-domain = <&io0_domain>;
status = "okay";
ssp10: ssp@10 {
compatible = "intel,ssp-dai";
reg = <0x10>;
status = "okay";
};
ssp11: ssp@11 {
compatible = "intel,ssp-dai";
reg = <0x11>;
status = "okay";
};
ssp12: ssp@12 {
compatible = "intel,ssp-dai";
reg = <0x12>;
status = "okay";
};
ssp13: ssp@13 {
compatible = "intel,ssp-dai";
reg = <0x13>;
status = "okay";
};
ssp14: ssp@14 {
compatible = "intel,ssp-dai";
reg = <0x14>;
status = "okay";
};
ssp15: ssp@15 {
compatible = "intel,ssp-dai";
reg = <0x15>;
status = "okay";
};
ssp16: ssp@16 {
compatible = "intel,ssp-dai";
reg = <0x16>;
status = "okay";
};
ssp17: ssp@17 {
compatible = "intel,ssp-dai";
reg = <0x17>;
status = "okay";
};
};
ssp2: ssp@2a100 {
compatible = "intel,ssp";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0002a100 0x1000
0x00079C00 0x200>;
i2svss = <0x0002AC00 0x1000>;
interrupts = <0x02 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 3
&hda_link_in 3>;
dma-names = "tx", "rx";
ssp-index = <2>;
power-domain = <&io0_domain>;
status = "okay";
ssp20: ssp@20 {
compatible = "intel,ssp-dai";
reg = <0x20>;
status = "okay";
};
ssp21: ssp@21 {
compatible = "intel,ssp-dai";
reg = <0x21>;
status = "okay";
};
ssp22: ssp@22 {
compatible = "intel,ssp-dai";
reg = <0x22>;
status = "okay";
};
ssp23: ssp@23 {
compatible = "intel,ssp-dai";
reg = <0x23>;
status = "okay";
};
ssp24: ssp@24 {
compatible = "intel,ssp-dai";
reg = <0x24>;
status = "okay";
};
ssp25: ssp@25 {
compatible = "intel,ssp-dai";
reg = <0x25>;
status = "okay";
};
ssp26: ssp@26 {
compatible = "intel,ssp-dai";
reg = <0x26>;
status = "okay";
};
ssp27: ssp@27 {
compatible = "intel,ssp-dai";
reg = <0x27>;
status = "okay";
};
};
mem_window0: mem_window@70200 {
compatible = "intel,adsp-mem-window";
reg = <0x70200 0x8>;
offset = <0x4000>;
memory = <&sram0>;
initialize;
read-only;
};
mem_window1: mem_window@70208 {
compatible = "intel,adsp-mem-window";
reg = <0x70208 0x8>;
memory = <&sram0>;
};
mem_window2: mem_window@70210 {
compatible = "intel,adsp-mem-window";
reg = <0x70210 0x8>;
memory = <&sram0>;
};
mem_window3: mem_window@70218 {
compatible = "intel,adsp-mem-window";
reg = <0x70218 0x8>;
memory = <&sram0>;
read-only;
};
adsp_idc: ace_idc@92000 {
compatible = "intel,adsp-idc";
reg = <0x92000 0x0400>;
interrupts = <24 0 0>;
interrupt-parent = <&ace_intc>;
};
dfpmcch: dfpmcch@71ac0 {
compatible = "intel,adsp-dfpmcch";
reg = <0x00071ac0 0x40>;
};
dfpmccu: dfpmccu@71b00 {
compatible = "intel,adsp-dfpmccu";
reg = <0x71b00 0x100>;
hub_ulp_domain: hub_ulp_domain {
compatible = "intel,adsp-power-domain";
bit-position = <15>;
};
ml0_domain: ml0_domain {
compatible = "intel,adsp-power-domain";
bit-position = <12>;
};
io1_domain: io1_domain {
compatible = "intel,adsp-power-domain";
bit-position = <9>;
};
io0_domain: io0_domain {
compatible = "intel,adsp-power-domain";
bit-position = <8>;
};
hub_hp_domain: hub_hpp_domain {
compatible = "intel,adsp-power-domain";
bit-position = <6>;
};
hst_domain: hst_domain {
compatible = "intel,adsp-power-domain";
bit-position = <5>;
};
};
shim: shim@71f00 {
compatible = "intel,cavs-shim";
reg = <0x71f00 0x100>;
};
tts: tts@72000 {
compatible = "intel,adsp-tts";
reg = <0x72000 0x70>;
status = "okay";
};
ace_rtc_counter: ace_rtc_counter@72008 {
compatible = "intel,ace-rtc-counter";
reg = <0x72008 0x0064>;
};
ace_timestamp: ace_timestamp@72040 {
compatible = "intel,ace-timestamp";
reg = <0x72040 0x0032>;
};
ace_art_counter: ace_art_counter@72058 {
compatible = "intel,ace-art-counter";
reg = <0x72058 0x0064>;
};
hda_host_out: dma@72800 {
compatible = "intel,adsp-hda-host-out";
#dma-cells = <1>;
reg = <0x00072800 0x40>;
dma-channels = <9>;
dma-buf-addr-alignment = <128>;
dma-buf-size-alignment = <32>;
dma-copy-alignment = <32>;
power-domain = <&hst_domain>;
interrupts = <13 0 0>;
interrupt-parent = <&ace_intc>;
status = "okay";
};
hda_host_in: dma@72c00 {
compatible = "intel,adsp-hda-host-in";
#dma-cells = <1>;
reg = <0x00072c00 0x40>;
dma-channels = <11>;
dma-buf-addr-alignment = <128>;
dma-buf-size-alignment = <32>;
dma-copy-alignment = <32>;
power-domain = <&hst_domain>;
interrupts = <12 0 0>;
interrupt-parent = <&ace_intc>;
status = "okay";
};
adsp_host_ipc: ace_host_ipc@73000 {
compatible = "intel,adsp-host-ipc";
status = "okay";
reg = <0x73000 0x30>;
interrupts = <0 0 0>;
interrupt-parent = <&ace_intc>;
};
hda_link_out: dma@79400 {
compatible = "intel,adsp-hda-link-out";
#dma-cells = <1>;
reg = <0x00079400 0x40>;
dma-channels = <9>;
dma-buf-addr-alignment = <128>;
dma-buf-size-alignment = <32>;
dma-copy-alignment = <32>;
power-domain = <&io0_domain>;
status = "okay";
};
hda_link_in: dma@79800 {
compatible = "intel,adsp-hda-link-in";
#dma-cells = <1>;
reg = <0x00079800 0x40>;
dma-channels = <11>;
dma-buf-addr-alignment = <128>;
dma-buf-size-alignment = <32>;
dma-copy-alignment = <32>;
power-domain = <&io0_domain>;
status = "okay";
};
/* This is actually an array of per-core designware
* controllers, but the special setup and extra
* masking layer makes it easier for MTL to handle
* this internally.
*/
ace_intc: ace_intc@94000 {
compatible = "intel,ace-intc";
reg = <0x94000 0xc00>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <4 0 0>;
num-irqs = <28>;
interrupt-parent = <&core_intc>;
};
tlb: tlb@17e000 {
compatible = "intel,adsp-mtl-tlb";
reg = <0x17e000 0x1000>;
paddr-size = <12>;
exec-bit-idx = <14>;
write-bit-idx= <15>;
};
timer: timer {
compatible = "intel,adsp-timer";
syscon = <&tts>;
};
};
hdas {
#address-cells = <1>;
#size-cells = <0>;
hda0: hda@0 {
compatible = "intel,hda-dai";
status = "okay";
reg = <0>;
};
hda1: hda@1 {
compatible = "intel,hda-dai";
status = "okay";
reg = <1>;
};
hda2: hda@2 {
compatible = "intel,hda-dai";
status = "okay";
reg = <2>;
};
hda3: hda@3 {
compatible = "intel,hda-dai";
status = "okay";
reg = <3>;
};
hda4: hda@4 {
compatible = "intel,hda-dai";
status = "okay";
reg = <4>;
};
hda5: hda@5 {
compatible = "intel,hda-dai";
status = "okay";
reg = <5>;
};
hda6: hda@6 {
compatible = "intel,hda-dai";
status = "okay";
reg = <6>;
};
hda7: hda@7 {
compatible = "intel,hda-dai";
status = "okay";
reg = <7>;
};
hda8: hda@8 {
compatible = "intel,hda-dai";
status = "okay";
reg = <8>;
};
hda9: hda@9 {
compatible = "intel,hda-dai";
status = "okay";
reg = <9>;
};
hda10: hda@a {
compatible = "intel,hda-dai";
status = "okay";
reg = <0x0a>;
};
hda11: hda@b {
compatible = "intel,hda-dai";
status = "okay";
reg = <0x0b>;
};
hda12: hda@c {
compatible = "intel,hda-dai";
status = "okay";
reg = <0x0c>;
};
hda13: hda@d {
compatible = "intel,hda-dai";
status = "okay";
reg = <0x0d>;
};
hda14: hda@e {
compatible = "intel,hda-dai";
status = "okay";
reg = <0x0e>;
};
hda15: hda@f {
compatible = "intel,hda-dai";
status = "okay";
reg = <0x0f>;
};
hda16: hda@10 {
compatible = "intel,hda-dai";
status = "okay";
reg = <0x10>;
};
hda17: hda@11 {
compatible = "intel,hda-dai";
status = "okay";
reg = <0x11>;
};
hda18: hda@12 {
compatible = "intel,hda-dai";
status = "okay";
reg = <0x12>;
};
};
};

View file

@ -20,7 +20,7 @@ zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_COMM_WIDGET comm_widget.c)
zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_COMM_WIDGET comm_widget_messages.c)
if (CONFIG_XTENSA_MMU)
zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_ACE30_PTL mmu_ptl.c)
zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_ACE30 mmu_ace30.c)
endif()
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

View file

@ -2,7 +2,7 @@
# SPDX-License-Identifier: Apache-2.0
if SOC_INTEL_ACE30_PTL
if SOC_INTEL_ACE30
config MP_MAX_NUM_CPUS
default 5

View file

@ -20,7 +20,7 @@ config SOC_INTEL_ACE20_LNL
help
ACE 2.0 Lunar Lake PCH
config SOC_INTEL_ACE30_PTL
config SOC_INTEL_ACE30
bool
select SOC_SERIES_INTEL_ADSP_ACE
help
@ -32,9 +32,9 @@ config SOC_SERIES
config SOC_TOOLCHAIN_NAME
default "intel_ace15_mtpm" if SOC_INTEL_ACE15_MTPM
default "intel_ace15_mtpm" if SOC_INTEL_ACE20_LNL
default "intel_ace30_ptl" if SOC_INTEL_ACE30_PTL
default "intel_ace30_ptl" if SOC_INTEL_ACE30
config SOC
default "ace15_mtpm" if SOC_INTEL_ACE15_MTPM
default "ace20_lnl" if SOC_INTEL_ACE20_LNL
default "ace30_ptl" if SOC_INTEL_ACE30_PTL
default "ace30" if SOC_INTEL_ACE30

View file

@ -351,8 +351,8 @@
#include <ace20_lnl/dmic_regs_ace2x.h>
#elif CONFIG_SOC_INTEL_ACE15_MTPM
#include <ace15_mtpm/dmic_regs_ace1x.h>
#elif CONFIG_SOC_INTEL_ACE30_PTL
#include <ace30_ptl/dmic_regs_ace3x.h>
#elif CONFIG_SOC_INTEL_ACE30
#include <ace30/dmic_regs_ace3x.h>
#else
#error "Unknown SoC"
#endif

View file

@ -96,7 +96,7 @@ void adsp_clock_init(void)
} else {
platform_lowest_freq_idx = ADSP_CPU_CLOCK_FREQ_IPLL;
}
#if CONFIG_SOC_INTEL_ACE30_PTL
#if CONFIG_SOC_INTEL_ACE30
/* Set the Cardinal clock divider to 18 to get 24.576MHz */
ACE_DfPMCCU.dfcrodiv &= ACE_CRODIV_CARCDS_MASK;
ACE_DfPMCCU.dfcrodiv |= ACE_CRODIV_CARCDS(0x12);

View file

@ -5,7 +5,7 @@ family:
socs:
- name: ace15_mtpm
- name: ace20_lnl
- name: ace30_ptl
- name: ace30
- name: intel_adsp_cavs
socs:
- name: cavs25