Add missing ranges to global_peripherals to explicitly translate
child addresses of global_peripherals in ram (0x2f000000).
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The Raspberry Pi Pico 2 uses a QMI flash controller, which differs from the
SSI controller used in the original Pico. Zephyr already has support for
the SSI controller, but lacked support for QMI.
This change adds the QMI flash controller implementation in the
flash_rpi_pico.c driver file. Additionally, the RP2350 SoC devicetree file
(rp2350.dtsi) has been updated to enable and describe the flash controller
for Pico 2.
Signed-off-by: Hanan Arshad <hananarshad619@gmail.com>
As a first step to enable the similar variants (e.g: ICM42686),
refactor common functionality into icm4268x files. As a result,
applications using the icm42688 will need to have both compatible
properties: "invensense,icm42688" and "invensense,icm4268x" defined.
In-tree boards have been modified to comply with this pattern.
This patch does not contain functional changes. The driver should
work the same as before.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
SPI(M/S)20 and SPIM(M/S)21 instances enable usage of pins on different
port, but require request for constant latency mode. Added
handling of such scenario in the driver. Added testcase
to cover it.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
UARTE20 and UARTE21 instances enable usage of pins on different
port, but require request for constant latency mode. Added
handling of such scenario in the driver. Added testcase
to cover it.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
update exti num-lines to depict total number of lines
add clocks entry to exti nodes of certain series
Signed-off-by: Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
add num-gpio-lines with default value of 16 to
st,stm32-exti.yaml
Co-authored-by: Mathieu CHOPLAIN <mathieu.choplain@st.com>
Signed-off-by: Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
As i.MX 95 19x19 and i.MX 95 15x15 have different pinmux definitions,
keep common part in nxp_mimx95_a55.dtsi, and define separate dts file
for each variants. These include the common part and their respective
pinmux definitions.
Signed-off-by: Aziz Sellami <aziz.sellami@nxp.com>
The GPIO block instance is based on the instance number during the
device driver initialization. This is not correct as instance numbers
in now way reflect any numbering scheme. Therefore, a DTS property
is introduced so that the block instance numbering is indicated
explicitly.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Add dts support for the STM32C091 and STM32C092 SoCs,
that are part of the STM32C0 series.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Fix interrupt level for acmp0 in the dts for xg21 device.
Only radio interrupts are critical and should have priority 0.
Signed-off-by: Bastien Beauchamp <bastien.beauchamp@silabs.com>
The icm45686-xxx example nodes have incorrect node labels.
The current node labels are for the icm42688.
Signed-off-by: Alden Haase <aldenhaase@gmail.com>
The Network Coprocessor on SiWx91x owns a large part of the flash. Zephyr
is not expected to access to theses areas.
However, it is still technically possible to access these. In addition, we
prefer the DTS contains a comprehensive and transparent description of the
hardware. So update the DTS with the real partitioning of the SoC.
Reference documentation is available here[1].
[1]: https://www.silabs.com/documents/public/application-notes/
an1416-siwx917-soc-memory-map.pdf
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
With commit d280d89 the gpiof port got moved from file stm32u5.dtsi to
file stm32u5_extra.dtsi. stm32u5_extra.dtsi is not included for
STM32U535/545. In same file stm32u5.dtsi still node wkup-pin@8 references
non-existent port gpiof.
Fixes#93445
Signed-off-by: Andreas Schmidt <andreas.schmidt@dormakaba.com>
Remove unused DMA clock property from device tree. Clock will
be managed by DMA driver for devices with GDMA peripheral.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
With IronSide SE there is only one defined UICR which is at
the location of the APPLICATION UICR. Update the devicetree
definition accordingly, and use the "nordic,nrf-uicr" compatible
on the node since the domain distinction added by the v2 compatible
is no longer relevant.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Refactor the default RAM memory map on nrf54h20dk:
Removes use of "nordic,owned-memory" which is no longer needed on
nrf54h20. Reserved memory nodes that were under "nordic,owned-memory"
have been moved directly under reserved-memory.
The memory shared between cpuapp-cpusec and cpurad-cpusec in RAM0x
is no longer used with IronSide, since IPC buffers toward the secure
domain are at new fixed locations. The cpuapp_data region
has been expanded to fill the available space in RAM0x when removing
these shared memory regions.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
This replaces the legacy SDFW compatible board configuration with the
IronSide SE compatible one, thus removing support for running samples
and tests on nRF54H20 devices with the old firmware.
All applications are expected to work on `nrf54h20dk/nrf54h20/cpuapp`
out of the box. For other board targets, all applications are expected
to boot, but may require additional peripheral configuration in UICR.
Build system support for the new UICR format is to be added separately.
Co-authored-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
move adi,adin1110.yaml adi,adin2111.yaml
from the phy subdir back into the ethernet dir.
They are ethernet controller bindings, not phy bindings.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Re-use the workqueue instead of having dedicated thread for handling
interrupts. This reduces memory usage and complexity.
Furthermore adds an auto mode for 100BASE-T1 negotiation.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Add declarations for High-Speed External (HSE) and High-Speed Internal
(HSI) clocks.
These clocks, based on oscillators, can be used to generate the system
clocks.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Foxville LM (0x125B) i226 variant and Intel Alder Lake platform was
used for developing and stabilizing the i226 Ethernet device driver.
However, users can reuse the provided device tree models as a reference
when enabling the support for other i226 variants and platforms.
This device-tree model include essential configurations for the i226
Ethernet controller, such as PCIe settings, interrupt mappings, Phy
MDIO, and DMA descriptor configurations.
Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
The Intel i226 Ethernet Controller is a PCIe Gen 2 one-lane modular
endpoint device that integrates a GbE Media Access Control (MAC) and
Physical Layer (PHY) port. This driver provides support for MAC and
DMA-specific initialization and runtime TX/RX operations.
Key features:
- MSI-X interrupts for TX/RX DMA channels.
- Multiple TX/RX DMA channel support with exclusive bottom-half.
- Implements a circular descriptor ring architechture with
producer-consumer semantics for high performance pkt processing.
- Full duplex support for 10/100/1000 Mbps.
- Half duplex support for 10/100 Mbps.
- Auto-negotiation for 10/100/1000 Mbps.
- MTU customization for flexible packet sizes.
- MAC address filtering based on:
- Random MAC generation.
- Local-mac-address mentioned in device tree.
- EEPROM pre-programmed mac address.
- Setting mac address via net shell.
- Support for multiple Ethernet interface instances.
Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
Signed-off-by: Ling Pei Lee <pei.lee.ling@intel.com>
Intel i226 MAC supports MDIO C22 and MDIO C45. Standard PHY registers
are accessible through MDIO C22, whereas PMAPMD and PCS are accssible
through MDIO C45.
Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
The Ethernet device model consists of multiple subsystem components, such
as MDIO, PHY, MAC and PTP_CLOCK. These components are mapped into a single
PCIe BAR location with same base address.
This platform driver retrieves the MMIO mapping details and provides a
framework to share it with all the child subsystem components. This
approach avoid the duplicate remapping, ensures efficient re-use of
MMIO mappings across related devices.
Example device tree structure for first ethernet instance:
parent0: parent0 {
compatible = "intel,eth-plat";
interrupt-parent = <&intc>;
vendor-id = <0x8086>;
device-id = <0xXXXX>;
igc0: igc0 {
compatible = "intel,igc-mac";
/*
* MAC specific properties.
*/
status = "okay";
};
mdio0: mdio0 {
compatible = "intel,igc-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy";
/*
* PHY specific properties.
*/
reg = <0x0>;
};
};
};
This framework is modular and re-usable for other PCIe based Ethernet
devices. It can also be extended to support additional platform specific
information shared across child nodes.
Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
According to the datasheet the flash erase timing is
typically 2ms, and max 10ms.
H503: DS14053 Rev 4: section 5.3.10, table 45, t_erase_max=10ms
H562/H563: DS14258 Rev 6: section 5.3.11, table 51, t_erase_max=10ms
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
M4F can use uarts from main domain of AM62. However, interrupts are not
supported.
The common main peripheral dts is kept in dts/venodor/ti to allow
sharing between arm targets (m4, r5) and arm64 targets (a53).
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Add a flash driver that is used to perform flash operations on a flash
chip that is connected to an Andes QSPI controller and is used for XIP
mode.
The driver is as small as possible, because necessary code has to be
placed in RAM. It is not possible to fetch code from flash while
performing erase/write operations.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Add stm32l1_disco and nucleo_l152re overlays for testing
sleep/stop/standby modes:
- samples/boards/st/power_mgmt/blinky;
- samples/boards/st/power_mgmt/wkup_pins;
I've measured consumption for each low-power mode:
- low-power sleep ~1.72mA;
- stop mode ~324uA;
- standby mode ~2.2 uA;
It's possible to use RTC as idle timer to exit from stop mode.
Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua>
This commit adds a new driver for the MaxBotix MB7040 ultrasonic
rangefinder. The driver uses I2C communication to read range data
from the sensor and exposes it via the Zephyr sensor API.
Tested on an esp32-s3 board using I2C bus. Verified readings at multiple
distances to confirm accuracy.
Signed-off-by: Sabrina Simkhovich <sabrinasimkhovich@gmail.com>
