Remove d0i1 and change threshold for d0i2 to 10ms for pm setting
according to the requirements to pass CTS for chrome projects.
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
According to the RV32M1 Series Manual, Rev 1.1 RV32M1 series supports the C
extension, and doesn't support the A extension. Apply fixes accordingly.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Currently imx8mm/n use pinctrl binding of nxp,imx8m-pinctrl.yaml which
is used for imx8mq series platforms, but imx8mm/n have different pinctrl
hardware module with imx8mq, so change imx8mm/n to use binding of
nxp,imx8mp-pinctrl.yaml as imx8mm, imx8mn and imx8mp have the same
pinctrl hardware module.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Add CANXL MRU handler, use the same RX, TX IRQ number.
Update the error priority that is lower priority than
the the tx_rx_mru priority incase the error interrupt
happens continuously, mru interrupt priority must be
higher to get report error counter. Otherwise the mru
interrupt can be delayed by error interrupt and
never call to MRU handler. This fixes#75022.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Fix the devicetree bindings to actually be used as the default
configuration, following the example set by various ST sensor devices.
This requires sadly dropping enums and using #defines for various
options as well as repeating many numbers, but presumably is the way to
do it given the precedent set by ST with sensors like the lsm6dso.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Add support for the EK RA8M1 board
This board is using Renesas RA8M1 MCU.
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
This is the initial commit to support for gpio driver
for RA8M1 MCU, the coding is base on renesas fsp hal
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Add initial support for the Cortex-M85 Core which is an implementation
of the Armv8.1-M mainline architecture.
The support is based on the Cortex-M55 support that already exists in
Zephyr.
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
This patch removes definitions of power domains from the ACE30 PTL DTS
file that do not exist in the actual hardware.
The following power domain nodes have been removed:
- 'ml1_domain' with a bit-position of <13>
- 'io3_domain' with a bit-position of <11>
- 'io2_domain' with a bit-position of <10>
These nodes were previously included in the DTS file but do not
correspond to any physical power domain in the ACE30 PTL hardware. Their
presence in the DTS could lead to confusion and misconfiguration, as the
software might attempt to interact with non-existent hardware features.
By removing these nodes, the DTS now accurately reflects the hardware
capabilities of the ACE30 PTL platform, ensuring that the power
management infrastructure within the firmware operates based on the
correct hardware configuration.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Remove the Audio Link Hub (ALH) nodes from the ACE 3.0 PTL DTS file.
This patch cleans up the Device Tree Source (DTS) for the ACE 3.0 PTL
platform by removing the definitions of the ALH DAI nodes. The ALH
interface is not utilized in the ACE 3.0 PTL architecture, making these
nodes redundant.
The following changes are made:
- Deleted the 'alh0' and 'alh1' nodes, which were previously defined
with FIXME comments indicating a problematic modeling of individual
ALH channels/instances using node labels.
This cleanup helps to prevent confusion and potential errors in device
configuration by ensuring that the DTS reflects the actual hardware
capabilities of the ACE 3.0 PTL platform.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Rearrange the power domain entries in the ACE30 PTL device tree source
file to be in ascending order according to their bit positions. This
reordering improves the readability of the device tree source by
grouping power domains logically according to their bit position within
the power management registers.
The changes in this patch include:
- Moving 'ml1_domain' and 'ml0_domain' to their correct positions
according to their bit-position values (13 and 12, respectively).
- Adjusting the order of 'io3_domain', 'io2_domain', 'io1_domain', and
'io0_domain' to reflect their bit positions (11, 10, 9, and 8).
- Placing 'hub_hp_domain' and 'hst_domain' at their new positions
according to their bit-position values (6 and 5).
No functional changes are introduced with this patch. It solely aims to
make the device tree source more intuitive and easier to navigate when
mapping power domains to their respective control bits.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit should deal with updating
the way USBD was handling the DMA
engine. Based on the #73803 request
DMA should be handled via the DMA
driver API class and not directly.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Cleanup leading spaces found via the following regexes:
r" compatible ="
r"^ "
in:
zephyr/**/*.dts
zephyr/**/*.dtsi
Signed-off-by: Jordan Yates <jordan@embeint.com>
Apply the workaround for the issue "BBRAM First Byte" in the
NPCX49nF_Errata. This bypass limits the access to the BBRAMs' first byte
(i.e., the offset 0). As a result, only 127 bytes are available in npcx4
chips.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Coverity found this legitimate issue: the datasheet specifies PS_IT
being 2-bits long (1, 2, 4, 8) and this driver assumes more steps are
available. Remove extraneous fields so the Proximity integration
setting fits in the expected 16-bit value.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
Clock NXP_S32_FTMx_CLK reference the output of PCC_FTMx clocks, but
FTM has an internal clock mux to select the clock source of the
counter, which for ucans32k1sic board is set to system clock. Fix the
clock nodes to use the correct clock name. So far this was working
because both NXP_S32_FTMx_CLK and NXP_S32_CORE_CLK are configured to
the same frequency.
Fixes#74348
Signed-off-by: Manuel Argüelles <marguelles.dev@gmail.com>
The current atmel,sam-tc-qdec sensor implementation shared the timer
counter node. This create issues when users wants define both modes.
The current proposal changes the qdec dedinition to be a child of
tc and refactor all the chain of definitions.
Fixes#71312
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add an optional DT property to specify the size of the RX/TX FIFO
implemented within the SPI core. The property name used is the same one
used by Xilinx's device tree generator.
When the FIFO is known to exist, we can use the RX FIFO occupancy register
to determine how many words can be read from the RX FIFO without checking
the RX FIFO empty flag after every read. Likewise with the TX FIFO, we can
use the FIFO size to avoid checking the FIFO full flag after every write.
This can increase overall throughput.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Add support for a workaround required when using the Xilinx Quad SPI core
with the USE_STARTUP option, which routes the core's SPI clock to the
FPGA's dedicated CCLK pin rather than a normal I/O pin. This is typically
used when interfacing with the same SPI flash device used for FPGA
configuration. In this mode, the SPI core cannot actually take control
of the CCLK pin until a few clock cycles are issued, which would break
the first transfer issued by the core. This workaround applies a dummy
command to the connected device to ensure that the clock signal is in the
correct state for subsequent commands.
See Xilinx answer record at:
https://support.xilinx.com/s/article/52626?language=en_US
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
LPTIM is not available in STOP3 mode, so RTC needs to be used instead.
This code usese similar approach as STM32WBAx for suspend to ram.
The STOP3 is disabled by default in device tree.
Signed-off-by: Adam Berlinger <adam.berlinger@st.com>
These three sensor types are all largely compatible. The SHT21 and
HTU21D can be supported by this driver by sending command 0xE3 instead
of 0xE0 to read the temperature.
Mention the sensor names in bindings and Kconfig to help those looking
for support to find it. There have been at least five PRs attempting to
add SHT21 and/or HTU21D support that did not realize the Si7006 is the
same.
As mentioned in PR #22862, the Sensirion SH21 is the original. The dts
bindings are adjusted (in a backward compatible way!) to make the sht21
the base binding and si7006 is derived from that.
Examples of dts compatibles:
TE Connectivity née Measurement Sepcialties HTU21D:
compatible = "meas,htu21d", "sensirion,sht21";
Sensirion SHT21:
compatible = "sensirion,sht21";
Silicon Labs Si7006
compatible = "silabs,si7006";
Silicon Labs Si7021
compatible = "silabs,si7021", "silabs,si7006";
Signed-off-by: Trent Piepho <tpiepho@gmail.com>
After changing the VEVIF and BELLBOARD names,
the dts for the individual boards must be aligned.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Renaming 'LOCAL' to 'RX' and 'REMOTE' to 'TX'.
This seems more descriptive and intuitive to use.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Add a mailbox driver for VEVIF events (VPR irq).
The driver can be built in either 'rx' or 'tx' configuration.
The VPR sends the event, so it uses the 'tx' configuration,
while the master core uses the 'rx' configuration of the driver
to receive the VPR events.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
The ATXP032 is a NOR flash device that supports up to ~100MHz
octal SDR/DDR with 4MB nonvolatile memory.
The device driver uses MSPI bus API and could be used across different
SoC controllers that implement the MSPI bus API.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
The APS6404L psram is a quad SDR SPI device that runs up to 100MHz.
It can provide 8MB of external RAM for SoCs that supports XIP feature.
The device driver uses MSPI bus API and could be used across
different controllers that implement the MSPI bus API.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
Kconfig, .ld and comments fixing
Fixed address of UART1, WDT and RTC timer disabled by default
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
