Add PM support to cc23x0 SPI module. This implies listing states which
cause power loss and enabling device runtime PM for the DMA in the DT.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
This driver adds support for the Infineon FM25XXX series of chips.
Has been tested on Infineon FM25CL64B-G.
Signed-off-by: Luna Pes <zephyr@orangemurker.com>
Move the watermark threshold trigger mode to a configurable dt boolean.
When using the default configuration of watermark threshold
interrupt greater than or equals, extra interrupts are serviced
to icm45686_event_handler().
When `fifo-watermark-equals;` is added to the sensor DT overlay,
the new behavior is only one interrupt is generated per watermark
threshold crossing. Until the host drains the fifo, no extra interrupts
will be generated.
Signed-off-by: Anthony Williams <anthony289478@gmail.com>
Add initial support for Nuvoton NuMaker-M333x SoC series,
including basic initialization and device tree includes.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
The goal of this patch is to switch from the nwp.c and nwp.h soc files
to the new nwp driver. During this transition, we also renamed
CONFIG_WISECONNECT_NETWORK_STACK to CONFIG_SILABS_SIWX91X_NWP which are
a better naming to let the user knows that the network coprocessor files
will be added to the compilation.
The switch from a soc file to a driver device introduce a notion of nwp
device that allows us to check for good initialization and ressources
allocation.
Before this patch, it is not possible to know if the nwp have booted
successfully or not. We can now check if the device driver is ready
or not before trying to do operation related to the nwp.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Correct STM32H7xx SoCs DMA lists that were not split by phandle and
seemed to form unique phandles. This is not currently as issue with
existing DT parsing macros and tools but may generate build errors
if tools are more strict on the DTS implementation formats.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Correct STM32H5xx SoCs DMA lists that were not split by phandle and
seemed to form unique phandles. This is not currently as issue with
existing DT parsing macros and tools but may generate build errors
if tools are more strict on the DTS implementation formats.
Clean indentation by the ways for the modified DTSI file lines.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Correct STM32F4xx SoCs DMA lists that were not split by phandle and
seemed to form unique phandles. This is not currently as issue with
existing DT parsing macros and tools but may generate build errors
if tools are more strict on the DTS implementation formats.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
For lptmr counter driver, since "prescaler" has been
deprecated and replaced by prescale-glitch-filter.
Update related setting in device tree files.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
In current code, if timer-mode-sel is 0(Timer Counter Mode),
bypass_prescaler_glitch will be 1, that makes prescaler setting
be bypassed. But this setting is very useful, especially for
long timing count.
In this patch, we update prescale-glitch-filter default value to 0,
to indicate prescaler and glitch filter are disabled, which comply
the existing devices DTS setting (prescaler = 1).
And if user sets prescale-glitch-filter properity other than 0,
we should set bypass_prescaler_glitch to false to make prescaler work,
and the clock frequence should be calculated with prescaler setting.
Update prescaler field in dt-bindings to tell developer should use
prescale-glitch-filter instead.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
The opamp addresses were wrong given the ranges translations.
This resulted in using the NS addresses on a S build.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add the description of NPU Cache (aka cacheaxi) to allow configuring
them in NPU Cache driver.
I intentionally chose this over creating a new dedicated node as
the exclusive user is NPU Cache and this could be done as part of
NPU driver initialization.
Update the NPU driver to take those into account as part of its init
routine.
Signed-off-by: Mickael Guene <mickael.guene@st.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Add DMA nodes for MCXW7X SOC DTS.
This SOC used TRIGMUX instead of DMAMUX.
Enable EDMAv3 for the frdm_mcxw71 and frdm_mcxw72
platforms.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Co-authored-by: Declan Snyder <declan.snyder@nxp.com>
Add Watchdog driver support for Renesas RZ/A3UL, N2L, T2M
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
This commit adds the following functionality support:
1. More baudrate setting.
2. 7 bit data moded.
3. Tx (CR_SOUT) and Rx (CR_SIN) signal invert.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Commits 72370b2 and ff34d57 added the requires-ulbpr
(Unlock Block Protection Register) property to the devicetree binding
for devices controlled by the STM32 QSPI peripheral, and support for
this property to the STM32 QSPI driver.
Some QSPI flash ICs (e.g. Microchip SST26VF series) require this
command to be sent before writing/erasing is possible.
This commit adds the same support to the STM32 OSPI and XSPI drivers.
Signed-off-by: Ben Marsh <ben.marsh@helvar.com>
In STM32 ADC binding, rename the possible values of the sequencer and
oversampler properties to use lowercase string, similar to the internal
regulator.
Adapts the driver and the dtsi with the new values.
Fixes a macro issue in the driver. Since the value from the dtsi didn't
start with internal_regulator_, the reconstruction of the defines by
the macro ANY_ADC_INTERNAL_REGULATOR_TYPE_IS was missing this prefix and
the comparison failed. Add a new argument to the IS_EQ_STRING_PROP to be
able to insert such a prefix.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
- Add support MRAM node on Renesas SoC dts layer for RA8P1, RA8T2
- Move the MRAM and SRAM resource defination to SoC dts layer
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
1. MCXN23x edma1 has 8 channels, not 16.
2. MCXN23x edma0 and edma1 have 94 requests, not 120.
3. MCXNx4x edma0 and edma1 have 117 requests, not 120.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add a property with which MSPI controllers can indicate their limits
on the maximum amount of data they can transfer in one packet.
Use the property for the SSI controller, for which the clock stretching
feature requires the use of the NDF field of the CTRLR1 register, which
is 16-bit wide, hence the data length limit is 64 kB.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
STM32 reset controller position argument provided to STM32_RESET()
macro sometime uses an unnecessary U suffix. Remove these useless
suffixes for this series for consistency among STM32 SoCs DTSI files.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
STM32 reset controller position argument provided to STM32_RESET()
macro sometime uses an unnecessary U suffix. Remove these useless
suffixes for this series for consistency among STM32 SoCs DTSI files.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
STM32 reset controller position argument provided to STM32_RESET()
macro sometime uses an unnecessary U suffix. Remove these useless
suffixes for this series for consistency among STM32 SoCs DTSI files.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
STM32 reset controller position argument provided to STM32_RESET()
macro sometime uses an unnecessary U suffix. Remove these useless
suffixes for this series for consistency among STM32 SoCs DTSI files.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
STM32 reset controller position argument provided to STM32_RESET()
macro sometime uses an unnecessary U suffix. Remove these useless
suffixes for this series for consistency among STM32 SoCs DTSI files.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
STM32 reset controller position argument provided to STM32_RESET()
macro sometime uses an unnecessary U suffix. Remove these useless
suffixes for this series for consistency among STM32 SoCs DTSI files.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
STM32 reset controller position argument provided to STM32_RESET()
macro sometime uses an unnecessary U suffix. Remove these useless
suffixes for this series for consistency among STM32 SoCs DTSI files.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
STM32 reset controller position argument provided to STM32_RESET()
macro sometime uses an unnecessary U suffix. Remove these useless
suffixes for this series for consistency among STM32 SoCs DTSI files.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
STM32 reset controller position argument provided to STM32_RESET()
macro sometime uses an unnecessary U suffix. Remove these useless
suffixes for this series for consistency among STM32 SoCs DTSI files.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
STM32 reset controller position argument provided to STM32_RESET()
macro sometime uses an unnecessary U suffix. Remove these useless
suffixes for this series for consistency among STM32 SoCs DTSI files.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
STM32 reset controller position argument provided to STM32_RESET()
macro sometime uses an unnecessary U suffix. Remove these useless
suffixes for this series for consistency among STM32 SoCs DTSI files.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
STM32 reset controller position argument provided to STM32_RESET()
macro sometime uses an unnecessary U suffix. Remove these useless
suffixes for this series for consistency among STM32 SoCs DTSI files.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
STM32 reset controller position argument provided to STM32_RESET()
macro sometime uses an unnecessary U suffix. Remove these useless
suffixes for this series for consistency among STM32 SoCs DTSI files.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
