Move the `overrun-character` property from the common Nordic SPI
binding to the `spi-controller` base binding. This gives users of the
SPI interface a way to query what the default value is at compile-time,
and potentially avoid allocation of large constant buffers.
Signed-off-by: Jordan Yates <jordan@embeint.com>
It's a superfluous value which used to be required by tooling, but now
we can remove it.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Between SoC revisions, the address was moved from 0x5F909000 in the
global domain, to 0xF0000000 in PPR's private address space.
Move the corresponding DT node out of `cpuppr_vpr` range to a separate
bus node, which is considered inaccessible to all cores but `cpuppr`.
This is expressed by selectively leaving out the `simple-bus` compatible
and `ranges` property, i.e., they're only set in `nrf54h20_cpuppr.dtsi`.
This lets the interrupt controller node remain visible at system level,
for the purpose of describing IRQ mappings between cores in devicetree.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
This update is to support clock API for RA8
Move the clock initialize function into clock driver
Peripheral clock now has 2 more property in clock cell for enable
and disable clock to peripheral module
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
This change adds the device tree property for specifying oe-override
(output-enable override behavior), as well as defines for possible values
of the property.
RP2040 GPIOs can be configured to automatically invert the output-enable
signal from the selected peripheral function. This is useful for tasks like
writing efficient PIO code, such as in the i2c example in the rp2040
datasheet.
Signed-off-by: Yiding Jia <yiding.jia@gmail.com>
On new SoCs, certain pins need to enable the clock setting on the pin
for it to work properly. For now, this has been handled internally in
the pinctrl driver, however, it appears to be an instance-specific
property (e.g. UARTE/SPIM instances in the fast domain do not require
such setting). Move the configuration of this settings to DT, the best
place where to have instance-specific hardware settings.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
HSFLL120 is a clock used by fast peripherals, and it is controlled by
the system controller. From an application perspective, it is a fixed
clock. Note that it has multiple outputs (clk_main @ 320MHz, and
clk_main2|4 which provide the main clock divided by 2 and 4,
respectivelu). Only the main frequency is represented for now.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Programming of the MLCS register was performed on the incorrect bits.
Additionally, saving the new version did not erase the previously set
value, which could result in an incorrect register value.
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
nRF53X HV regulator differs from eg nRF52X as it offers a silent mode
option. For this reason, a new compatible is used, even if now such
capability is not exposed yet.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The SoC main supply is part of the POWER IP block. The POWER IP is a
kind of multi-purpose block, so each of its functions is described as a
child node in DT, like similar other MFD. This allows to have specific
properties, e.g. for DC/DC mode.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Some Nordic SoCs, like nRF52 contain an internal regulator for the main
SoC supply. Depending on the SoC, the regulator can have multiple
configurations (e.g. single/double stage), which mainly depends on
supporting "high-voltage" mode or not (VDDH pin supply). This patch adds
bindings for nRF5X regulator and nRF52X HV regulator.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The TMAG3001 is quite similar to the tmag5273 and can be used with just
some small modifications.
Signed-off-by: Fabian Pflug <fabian.pflug@grandcentrix.net>
Enable the Software Watchdog Timer instance on this board.
Now that SWT is enabled for this board and made the default watchdog,
sample.task_wdt.no_hw_fallback can be removed as is no longer needed.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Convert NXP SWT watchdog driver to a native driver and extend the
SWT supported functionalities and configuration options.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Convert power management to native drivers retaining existing
functionalities. Presently only SoC reset support and power control
initialization is supported, but these drivers will be extended to
support power management as well.
MC_ME and MC_RGM peripherals are common enough to be reused by other NXP
S32 devices, whereas PMC has specific implementations for each SoC
series.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
