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driver: serial: Add serial driver support for Renesas RA8 devices

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Add implementation of sci_b_uart for Renesas RA device

Signed-off-by: The Thanh. Nguyen <the.nguyen.yf@renesas.com>
This commit is contained in:
The Thanh. Nguyen 2024-01-12 08:20:54 +00:00 • committed by Anas Nashif
commit f93f801c65
12 changed files with 1492 additions and 146 deletions
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6
boards/renesas/ek_ra8m1/ek_ra8m1-pinctrl.dtsi
View file

@ -4,15 +4,15 @@
*/
&pinctrl {
sci0_default: sci0_default {
sci9_default: sci9_default {
group1 {
/* tx */
psels = <RA_PSEL(RA_PSEL_SCI_0, 6, 9)>;
psels = <RA_PSEL(RA_PSEL_SCI_9, 10, 14)>;
drive-strength = "medium";
};
group2 {
/* rx */
psels = <RA_PSEL(RA_PSEL_SCI_0, 6, 10)>;
psels = <RA_PSEL(RA_PSEL_SCI_9, 10, 15)>;
};
};
};

18
boards/renesas/ek_ra8m1/ek_ra8m1.dts
View file

@ -17,6 +17,8 @@
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart9;
zephyr,shell-uart = &uart9;
};
leds {
@ -64,6 +66,12 @@
status = "okay";
};
&sciclk {
clk_src = <RA_CLOCK_SOURCE_PLL1P>;
clk_div = <RA_SCI_CLOCK_DIV_4>;
status = "okay";
};
&ioport1 {
status = "okay";
};
@ -75,3 +83,13 @@
&ioport6 {
status = "okay";
};
&sci9 {
pinctrl-0 = <&sci9_default>;
pinctrl-names = "default";
status = "okay";
uart9: uart {
current-speed = <115200>;
status = "okay";
};
};

2
drivers/serial/CMakeLists.txt
View file

@ -75,7 +75,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_INTEL_LW uart_intel_lw.c)
zephyr_library_sources_ifdef(CONFIG_UART_RENESAS_RA uart_renesas_ra.c)
zephyr_library_sources_ifdef(CONFIG_UART_ENE_KB1200 uart_ene_kb1200.c)
zephyr_library_sources_ifdef(CONFIG_UART_RZT2M uart_rzt2m.c)
zephyr_library_sources_ifdef(CONFIG_UART_RA8_SCI_B uart_renesas_ra8_sci_b.c)
zephyr_library_sources_ifdef(CONFIG_USERSPACE uart_handlers.c)
if(CONFIG_UART_NATIVE_POSIX)

2
drivers/serial/Kconfig
View file

@ -278,4 +278,6 @@ rsource "Kconfig.ene"
rsource "Kconfig.rzt2m"
source "drivers/serial/Kconfig.renesas_ra8"
endif # SERIAL

1
drivers/serial/Kconfig.renesas_ra
View file

@ -1,5 +1,4 @@
# Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
config UART_RENESAS_RA

25
drivers/serial/Kconfig.renesas_ra8 Normal file
View file

@ -0,0 +1,25 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
config UART_RA8_SCI_B
bool "Renesas RA SCI_B UART"
default y
depends on DT_HAS_RENESAS_RA8_UART_SCI_B_ENABLED
select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT
select SERIAL_SUPPORT_ASYNC
select USE_RA_FSP_SCI_B_UART
select USE_RA_FSP_DTC if UART_ASYNC_API
help
Enable Renesas RA SCI_B UART Driver.
if UART_RA8_SCI_B && (UART_INTERRUPT_DRIVEN || UART_ASYNC_API)
config UART_RA_SCI_B_UART_FIFO_ENABLE
bool "RA SCI_B UART FIFO usage enable"
default y if UART_INTERRUPT_DRIVEN
default n if UART_ASYNC_API
help
Enable RA SCI_B FIFO
endif

1163
drivers/serial/uart_renesas_ra8_sci_b.c Normal file
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File diff suppressed because it is too large Load diff

11
dts/arm/renesas/ra/ra8/r7fa8m1ahecbd.dtsi
View file

@ -5,3 +5,14 @@
*/
#include <arm/renesas/ra/ra8/r7fa8m1xh.dtsi>
/ {
soc {
flash-controller@407fe000 {
flash0: flash@2000000 {
compatible = "soc-nv-flash";
reg = <0x02000000 DT_SIZE_M(2)>;
};
};
};
};

357
dts/arm/renesas/ra/ra8/ra8x1.dtsi
View file

@ -30,6 +30,8 @@
};
soc {
interrupt-parent = <&nvic>;
sram0: memory@22000000 {
compatible = "mmio-sram";
reg = <0x22000000 DT_SIZE_K(896)>;
@ -41,6 +43,223 @@
status = "okay";
};
pinctrl: pin-controller@40400800 {
compatible = "renesas,ra8-pinctrl";
reg = <0x40400800 0x3c0>;
status = "okay";
};
ioport0: gpio@40400000 {
compatible = "renesas,ra8-gpio";
reg = <0x40400000 0x20>;
port = <0>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport1: gpio@40400020 {
compatible = "renesas,ra8-gpio";
reg = <0x40400020 0x20>;
port = <1>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport2: gpio@40400040 {
compatible = "renesas,ra8-gpio";
reg = <0x40400040 0x20>;
port = <2>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport3: gpio@40400060 {
compatible = "renesas,ra8-gpio";
reg = <0x40400060 0x20>;
port = <3>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport4: gpio@40400080 {
compatible = "renesas,ra8-gpio";
reg = <0x40400080 0x20>;
port = <4>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
vbatts_pins = <2 3 4>;
status = "disabled";
};
ioport5: gpio@404000a0 {
compatible = "renesas,ra8-gpio";
reg = <0x404000a0 0x20>;
port = <5>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport6: gpio@404000c0 {
compatible = "renesas,ra8-gpio";
reg = <0x404000c0 0x20>;
port = <6>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport7: gpio@404000e0 {
compatible = "renesas,ra8-gpio";
reg = <0x404000e0 0x20>;
port = <7>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport8: gpio@40400100 {
compatible = "renesas,ra8-gpio";
reg = <0x40400100 0x20>;
port = <8>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport9: gpio@40400120 {
compatible = "renesas,ra8-gpio";
reg = <0x40400120 0x20>;
port = <9>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioporta: gpio@40400140 {
compatible = "renesas,ra8-gpio";
reg = <0x40400140 0x20>;
port = <10>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioportb: gpio@40400160 {
compatible = "renesas,ra8-gpio";
reg = <0x40400160 0x20>;
port = <11>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
sci0: sci0@40358000 {
compatible = "renesas,ra-sci";
interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
interrupt-names = "rxi", "txi", "tei", "eri";
reg = <0x40358000 0x100>;
clocks = <&sciclk>;
status = "disabled";
uart {
compatible = "renesas,ra8-uart-sci-b";
channel = <0>;
status = "disabled";
};
};
sci1: sci1@40358100 {
compatible = "renesas,ra-sci";
interrupts = <8 1>, <9 1>, <10 1>, <11 1>;
interrupt-names = "rxi", "txi", "tei", "eri";
reg = <0x40358100 0x100>;
clocks = <&sciclk>;
status = "disabled";
uart {
compatible = "renesas,ra8-uart-sci-b";
channel = <1>;
status = "disabled";
};
};
sci2: sci2@40358200 {
compatible = "renesas,ra-sci";
interrupts = <12 1>, <13 1>, <14 1>, <15 1>;
interrupt-names = "rxi", "txi", "tei", "eri";
reg = <0x40358200 0x100>;
clocks = <&sciclk>;
status = "disabled";
uart {
compatible = "renesas,ra8-uart-sci-b";
channel = <2>;
status = "disabled";
};
};
sci3: sci3@40358300 {
compatible = "renesas,ra-sci";
interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
interrupt-names = "rxi", "txi", "tei", "eri";
reg = <0x40358300 0x100>;
clocks = <&sciclk>;
status = "disabled";
uart {
compatible = "renesas,ra8-uart-sci-b";
channel = <3>;
status = "disabled";
};
};
sci4: sci4@40358400 {
compatible = "renesas,ra-sci";
interrupts = <20 1>, <21 1>, <22 1>, <23 1>;
interrupt-names = "rxi", "txi", "tei", "eri";
reg = <0x40358400 0x100>;
clocks = <&sciclk>;
status = "disabled";
uart {
compatible = "renesas,ra8-uart-sci-b";
channel = <4>;
status = "disabled";
};
};
sci9: sci9@40358900 {
compatible = "renesas,ra-sci";
interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
interrupt-names = "rxi", "txi", "tei", "eri";
reg = <0x40358900 0x100>;
clocks = <&sciclk>;
status = "disabled";
uart {
compatible = "renesas,ra8-uart-sci-b";
channel = <9>;
status = "disabled";
};
};
flash-controller@407fe000 {
reg = <0x407fe000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
};
option_setting_ofs: option_setting_ofs@300a100 {
compatible = "zephyr,memory-region";
reg = <0x0300a100 0x18>;
@ -62,144 +281,6 @@
status = "okay";
};
};
pinctrl: pin-controller@40400800 {
compatible = "renesas,ra8-pinctrl";
reg = <0x40400800 0x3c0>;
status = "okay";
};
ioport0: gpio@40400000 {
compatible = "renesas,ra8-gpio";
reg = <0x40400000 0x20>;
port = <0>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport1: gpio@40400020 {
compatible = "renesas,ra8-gpio";
reg = <0x40400020 0x20>;
port = <1>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport2: gpio@40400040 {
compatible = "renesas,ra8-gpio";
reg = <0x40400040 0x20>;
port = <2>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport3: gpio@40400060 {
compatible = "renesas,ra8-gpio";
reg = <0x40400060 0x20>;
port = <3>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport4: gpio@40400080 {
compatible = "renesas,ra8-gpio";
reg = <0x40400080 0x20>;
port = <4>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
vbatts_pins = <2 3 4>;
status = "disabled";
};
ioport5: gpio@404000a0 {
compatible = "renesas,ra8-gpio";
reg = <0x404000a0 0x20>;
port = <5>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport6: gpio@404000c0 {
compatible = "renesas,ra8-gpio";
reg = <0x404000c0 0x20>;
port = <6>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport7: gpio@404000e0 {
compatible = "renesas,ra8-gpio";
reg = <0x404000e0 0x20>;
port = <7>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport8: gpio@40400100 {
compatible = "renesas,ra8-gpio";
reg = <0x40400100 0x20>;
port = <8>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioport9: gpio@40400120 {
compatible = "renesas,ra8-gpio";
reg = <0x40400120 0x20>;
port = <9>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioporta: gpio@40400140 {
compatible = "renesas,ra8-gpio";
reg = <0x40400140 0x20>;
port = <10>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
ioportb: gpio@40400160 {
compatible = "renesas,ra8-gpio";
reg = <0x40400160 0x20>;
port = <11>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
flash-controller@407fe000 {
reg = <0x407fe000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@2000000 {
compatible = "soc-nv-flash";
reg = <0x02000000 DT_SIZE_M(2)>;
};
};
};
&nvic {

21
dts/bindings/serial/renesas,ra8-uart-sci-b.yaml Normal file
View file

@ -0,0 +1,21 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
description: Renesas RA SCI_B UART controller
compatible: "renesas,ra8-uart-sci-b"
include: [pinctrl-device.yaml, uart-controller.yaml]
properties:
channel:
type: int
required: true
tx-dtc:
type: boolean
description: Enable dtc support for transmit
rx-dtc:
type: boolean
description: Enable dtc support for receive

10
modules/Kconfig.renesas_fsp
View file

@ -7,3 +7,13 @@ config HAS_RENESAS_RA_FSP
bool
help
Enable Renesas RA FSP support
config USE_RA_FSP_SCI_B_UART
bool
help
Enable RA FSP SCI-B UART driver
config USE_RA_FSP_DTC
bool
help
Enable RA FSP DTC driver

22
tests/drivers/uart/uart_async_api/boards/ek_ra8m1.overlay
View file

@ -3,10 +3,26 @@
* SPDX-License-Identifier: Apache-2.0
*/
dut: &sci2 {
compatible = "renesas,ra-uart-sci-b";
current-speed = <115200>;
&pinctrl {
sci2_default: sci2_default {
group1 {
/* tx */
psels = <RA_PSEL(RA_PSEL_SCI_2, 10, 3)>;
drive-strength = "medium";
};
group2 {
/* rx */
psels = <RA_PSEL(RA_PSEL_SCI_2, 10, 2)>;
};
};
};
&sci2 {
pinctrl-0 = <&sci2_default>;
pinctrl-names = "default";
status = "okay";
dut: uart {
current-speed = <115200>;
status = "okay";
};
};