Removes resource reservation for cpuflpr from the cpuapp build and
only applies it when either of the flpr snippets are used
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This change renames the Infineon BT-HCI UART driver source
and binding file to allow reuse across all Infineon AIROC
connectivity chips that use HCI UART transport.
No functional changes
Signed-off-by: Merin George <merin.george@infineon.com>
Add the `ranges` property to the flash node on RP2040-based boards to
correctly specify the base address and size for child nodes. This aligns
the board device trees with expected Zephyr DT conventions and ensures
proper address translation for flash partitions and other child nodes.
Signed-off-by: David Schneider <schneidav81@gmail.com>
- Adds the common dtsi files based on memory configuration and pin
configuration
- Adds the gpio nodes in pic32cm_pl10 series
- Adds the list of supported socs
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
Signed-off-by: Muhammed Asif <muhammed.asif@microchip.com>
- Add `max-bitrate-supported` property to indicate the maximum
bitrate that the channel can support.
- Update `max-bitrate-supported` property value for all Renesas RA
devices
- Update driver i2c_renesas_ra_iic.c to check `clock-frequency`
property and bitrate runtime configure is correct
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
The GINT peripheral provides grouped GPIO interrupt
functionality, allowing multiple pins to be combined
into a single interrupt source.
Support the peripheral in interrupt controller
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
add initial version of devicetree for amebaG2 SOC.
amebaG2 devicetree file is main platform dtsi file, which should
be included from board dts (e.g rtl8721f_evb.dts)
Signed-off-by: zjian zhang <zjian_zhang@realsil.com.cn>
Add missing clock property to spi00 nodes. Add missing clock property to
uart00 node in nrf7120.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Since, commit 2f7d13840f ("kconfig: Fix CONFIG_FLASH_LOAD_OFFSET for non-0
starting addresses"), the way to compute offsets in the flash memory has
changed.
With this change, the arguments passed to siwx91x_isp_prepare.py were not
correct anymore and "west flash" ended up with:
ERROR: Waiting for flashloader failed: 108 - Checksum error
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Add property for overriding the maximum number of hardware message buffers
used for RX filters on a per-instance basis.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The maximum number of RX filters is limited by the number of message
buffers, which cannot exceed 128. Add a range to the Kconfig option
imposing this.
Remove artificial build-time check on CONFIG_CAN_MCUX_FLEXCAN_MAX_FILTERS
being larger than zero, as transmit-only configuration is otherwise fully
supported.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The flash0 physical address in the node name did not
match the starting address in the reg property. This
part implements 352KB code SRAM starting at 0xC0000.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Fix mismatch between unit address of the power domain nodes and the value
passed via the "reg" property.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add device tree node for the Broadcom iProc RNG200 hardware
random number generator found on BCM2711 SoC
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Now that STM32WBA6 also uses the st,stm32n6-otghs compatible, reword the
description to better fit its use.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Update hal_stm32 revision so that SPI pinctrl are configured with a
very-high-speed slew rate by default.
Rename debug_jtrst_pb4 to debug_njtrst_pb4 for U5 and WBA. For WBA65,
remove the now useless swj_port redefinition.
For WBA65, remove the USB OTG pinctrl. As per RefMan RM0515, "PD6 and PD7
provide USB OTG_HS functions, but they cannot be used for any other
function, including GPIO. When USB OTG_HS is not used, PD6 and PD7 must be
kept in analog mode."
Change the compatible to the N6 one which do not require pinctrl.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add devicetree binding for the SiFli SF32LB series eFuse OTP memory
controller. The eFuse provides 128 bytes (4 banks x 32 bytes) of
one-time programmable storage.
Signed-off-by: Haoran Jiang <halfsweet@halfsweet.cn>
Correct GIC addresses to match ARM Cortex-R8 TRM PERIPHBASE specification.
GIC must be at fixed offsets from PERIPHBASE (0xAE000000)
- Distributor: 0xAE001000 (PERIPHBASE + 0x1000)
- CPU Interface: 0xAE000100 (PERIPHBASE + 0x100)
Updated device tree, MPU regions, and Renode configuration to use
correct addresses and add required memory protection.
Signed-off-by: Raja Shahzaib <rshahzaib077@gmail.com>
Correct a clock initialization ordering issue where IMO, an internal
high speed oscillator, was being setup before ILO. This does not match
the MTB initialization order and would cause the part to fault.
Sets up the default clock configuration on the part to be 48MHz. Adjusts
the default WCO (low speed external crystal source) to be 32768 as the
eval board has this crystal on it. Enables common clock elements
(hf_clk, clock_pump) as needed in the part dts rather than the board.
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Correct a clock initialization ordering issue where IMO, an internal
high speed oscillator, was being setup before ILO. This does not match
the MTB initialization order and would cause the part to fault.
Sets up the default clock configuration on the part to be 48MHz. Adjusts
the default WCO (low speed external crystal source) to be 32768 as the
eval board has this crystal on it. Enables common clock elements
(hf_clk, clock_pump) as needed in the part dts rather than the board.
Signed-off-by: Tom Burdick <thomas.burdick@infineon.com>
The GPIO interrupts were incorrectly set to priority 4 on an m0 with
only 4 priorities, max is 3. Several of the gpio ports were missing
their interrupt property as it is a shared interrupt number but the
driver seems to account for this. Added the missing interrupt property
on these ports.
Signed-off-by: Tom Burdick <thomas.burdick@infineon.com>
We converted the QMSPI-LDMA driver to linux style with a local
register header in the driver folder. This is part of the long
term plan to remove the MEC5 HAL and have common drivers for
as many SoC's as possible. QMSPI register definitions are in
the SoC layer to be shared with other drivers (MSPI). The driver
was also updated based on changes in the SPI config structure.
The lastest SPI config structure changes force hardware controlled
chip selects and GPIO controlled chip selects to be mutually exclusive.
NOTE: driver works with the flash driver sample
and passes the common flash driver test.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Before that commit spi was not available for the soc sy1xx.
With this commit a basic usage of spi is possible.
Signed-off-by: Sven Ginka <s.ginka@sensry.de>
Co-authored-by: Fin Maaß <f.maass@vogl-electronic.com>
This change adds optional reset via GPIO support to u-blox M8 driver.
This is useful if host is reset separately from the u-blox M8 GNSS
receiver.
Signed-off-by: Vytautas Virvičius <vytautas@virvicius.dev>
reg attribute is supposed to hold start address and size
instead of start address and end address. This caused
a crash in malloc_prepare().
Signed-off-by: Damian Krolik <damian.krolik@nordicsemi.no>
The out-div binding was removed as dts setting now aligns
literal value, not register value. This commit updates
the out-div node entry to be the literal values as the
translation is now handled in the driver.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
