Commit graph

8801 commits

Author SHA1 Message Date
Gerard Marull-Paretas
3d3dce61b6 dts: common: nordic: nrf54h20: define BICR node
BICR (Board Information Configuration Registers) are located within the
application UICR region (ref. MRAM mapping, table 38).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-12-18 12:46:20 +01:00
Gerard Marull-Paretas
2db20cd00e dts: bindings: misc: add nordic,nrf-bicr
Add binding for the Nordic nRF BICR memory.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-12-18 12:46:20 +01:00
Benjamin Bigler
f1087d2042 drivers: adc: tla202x: add support for tla2022 and tla2024
This extends the tla2021 driver to support tla2022 and tla2024

Signed-off-by: Benjamin Bigler <benjamin.bigler@securiton.ch>
2024-12-18 08:33:49 +01:00
Neil Chen
a12bfa6c09 dts: arm/nxp: Add ctimer nodes to NXP MCXA156 dtsi file
Add ctimer nodes to NXP MCXA156 dtsi file

Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
2024-12-18 08:32:03 +01:00
Jiafei Pan
3e09f72bfd dts: mimx8mp: add gpio device node
Add GPIO dts nodes for imx8mp.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2024-12-18 08:31:52 +01:00
Stoyan Bogdanov
92aeb787c7 drivers: gpio: max22190: Add MAX22190 octal input with diagnostics
Add max22190 gpio driver with input functionality, since device
support only input without output.

Implemented diagnostic functionality for all 8 channels
which include various check to over/under voltage and wire break.
Filtering configuration is done from devicetree on per channel
bases and is configured on chip start.

In case some fault condition occure FAULT pin drive LOW which
prop to FAULT registers to be read. Data is stored in data structure
for furter analizes and ERR message is printed in console.

Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
2024-12-18 03:04:46 +01:00
Aurelie Fontaine
78c62d495f dts: bindings: sensor: Add invensense icm42670 properties
Add the power mode, accel and gyro filtering options,
 and apex features. Add -p and -s compatible.

Signed-off-by: Aurelie Fontaine <aurelie.fontaine@tdk.com>
2024-12-18 03:04:31 +01:00
Lucien Zhao
08b8b160a9 dts: arm: nxp: add two i3c instances for RT1180
add i3c instances
enable i3c clock under soc folder

Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
2024-12-18 01:01:37 +01:00
Gerson Fernando Budke
01fc0a750a dts: atmel: samr21: Use samd21 as base
The samr21 is a samd21 with a builtin at86rf233 radio. Use the samd21 as
base for these SoC and drop all duplicated nodes.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2024-12-18 01:01:09 +01:00
Gerson Fernando Budke
34fc01e008 dts: atmel: saml2x: Define USB node
The saml2x series provide USB to all SoC series. This moves the USB node
from saml21.dtsi to the base file saml2x.dtsi.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2024-12-18 01:01:09 +01:00
Gerson Fernando Budke
2e7599eac6 dts: atmel: saml21: Exclude DMA node
The DMA is already defined on the base header. This exclude the
duplicated node.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2024-12-18 01:01:09 +01:00
Gerson Fernando Budke
748bbd012b dts: atmel: sam0: Fix aliases and chosen nodes
Reorder and add missing aliases and chosen nodes.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2024-12-18 01:01:09 +01:00
Gerson Fernando Budke
162f728787 dts: atmel: sam0: Explicity disable nodes
When running tests on sam0 platform was detected that pinctrl for ADC
were not defined for some boards. To force an error at build time
nodes should be explicity disabled. This explicity disable nodes on
devicetree that require some user configuration.

In addition, the adc feature were excluded in some boards and
samr21-xpro was correct updated.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2024-12-18 01:01:09 +01:00
Gerson Fernando Budke
6f1f598a72 dts: atmel: sam0: Normalize dtsi nodes
Keep a consistent order on the nodes definitions to make it easy to read
between all the SoC series.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2024-12-18 01:01:09 +01:00
Teresa Zepeda Ventura
972c76bbf6 dts: pwm: add a binding for the SAM0 TC in PWM mode
Add a binding for the TC in PWM mode.

Signed-off-by: Teresa Zepeda Ventura <teresa.zvent@gmail.com>
2024-12-17 23:14:32 +01:00
Mikhail Siomin
a5a955d024 fs: littlefs: add littlefs disk version selection
Add the ability to select littlefs disk version
to maintain backward compatibility
with existing littlefs
with the same major disk version.

Signed-off-by: Mikhail Siomin <victorovich.01@mail.ru>
2024-12-17 20:55:51 +01:00
Michal Smola
6e7b335873 soc: nxp mcxc: fix LinkServer flashing
LinkServer can flash only the first time, cannot flash again.
Fix it by setting default mcu security status as unsecure.

Signed-off-by: Michal Smola <michal.smola@nxp.com>
2024-12-17 17:53:05 +01:00
Raffael Rostagno
4f61ce738b dts: soc: esp32: Counter driver update
Add clocks field to dts for clock control.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-12-17 15:23:38 +01:00
Bjarki Arge Andreasen
777adf4231 dts: bindings: update nrf-hsfll to nrf-hsfll-local
The nrf-hsfll was previously the only supported HSFLL clock, hence it
was not namespaced fully. Since we added nrf-hsfll-global, we should
add the namespace to nrf-hsfll as well.

Updates drivers and devicetree uses of HSFLL as well.

Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
2024-12-17 15:22:37 +01:00
Bjarki Arge Andreasen
82bb6fc121 dts: nordic: specify device model of global hsfll clock
Add specific device model for global hsfll clock and update dts tree
to use specific model. The clock is not fixed, and configurable at
runtime to predefined frequencies specified by the platform.

Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
2024-12-17 15:22:37 +01:00
Iuliana Prodan
d9caf60add dts: xtensa: nxp: imx8ulp: fix sram address
Fix addresses for sram0 and sram1.

Fixes: a7b7364c4e ("dts/xtensa/nxp: Add dtsi for imx8ulp")
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2024-12-17 11:38:06 +00:00
Hao Luo
63904f3a19 drivers: rtc: add rtc support for apollo3&3p
Add RTC support for Apollo3 and Apollo3 Plus Soc

Signed-off-by: Hao Luo <hluo@ambiq.com>
2024-12-17 05:48:58 +01:00
Jiafei Pan
888bf137b4 dts: arm64: nxp_mimx93_a55: remove duplicated header file
Removed duplicated header file.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2024-12-17 05:48:45 +01:00
Girisha Dengi
fbdf6e3463 dts: arm64: intel: Remove hard-coded clock values
Remove hard-coded clock values from device tree nodes,
instead read the clock values from the clock controller
during run time.

Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
2024-12-16 17:12:34 -05:00
Corey Wharton
3e82647ba6 drivers: i2c_dw: add devicetree property to offset clock settings
The actual clock speed of the bus is partially determined by the
rising/falling edges of the SCL. These settings allow applications
to tune the clock based on board characteristics.

Signed-off-by: Corey Wharton <xodus7@cwharton.com>
2024-12-16 20:51:32 +01:00
Neil Chen
ba572cc25e dts: arm/nxp: Add lpi2c nodes to NXP MCXA156 dtsi file
Add lpi2c nodes to NXP MCXA156 dtsi file

Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
2024-12-16 20:50:37 +01:00
Michał Stasiak
ab001888d3 dts: common: nordic: Add PDM to nrf54h20 dts
Added pdm0 node to nrf54h20 devicetree with proper bindings.

Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
2024-12-16 18:26:08 +01:00
Martin Hoff
4c3c67bf24 dts: arm/silabs: add dma node for efr32(mg2x/bg2x)
Update dts for efr32mg2x and efr32bg2x board that support silabs ldma

Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
2024-12-16 18:24:51 +01:00
Neil Chen
725c28ec4e dts: arm/nxp: Add usb nodes to NXP MCXA156 dtsi file
Add usb nodes to NXP MCXA156 dtsi file

Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
2024-12-16 10:52:51 +01:00
Danh Doan
535e3472df boards: renesas: add board support entropy driver using SCE5
add support SCE5 for board: ek_ra4w1

Signed-off-by: Danh Doan <danh.doan.ue@bp.renesas.com>
2024-12-16 10:52:16 +01:00
Danh Doan
4d6ff5660b drivers: entropy: Add support for SCE5 to entropy driver
add support SCE5 to entropy driver for Renesas RA

Signed-off-by: Danh Doan <danh.doan.ue@bp.renesas.com>
2024-12-16 10:52:16 +01:00
Nathan Olff
c152453a72 drivers: pwm: implement fake-pwm driver
implement fake-pwm driver with binding using fff

Signed-off-by: Nathan Olff <nathan@kickmaker.net>
2024-12-14 16:14:57 +01:00
Fabio Baltieri
f3eb5280c8 dts: arm: st: h7: add a template for stm32h743Xg
Same as stm32h743Xi.dtsi, half the flash.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2024-12-13 21:50:52 +01:00
Francois Ramu
7044876b0b dts: arm: stm32f412 device has a clock 48MHz multiplexer
Add a clk48Mhz node to the stm32f412 serie.
This clock is sourced by PLL_Q (default) or PLLI2S_Q
That 48MHz clock is used by the USB /SDMMC/RNG peripherals.
The sdmmc/SDIO clock is sourced by this CK48 (default)
or by the SYSCLOCK.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2024-12-13 20:05:11 +01:00
Francois Ramu
fcc5f9dac1 dts: bindings: pll i2s for the stm32f412 has a Q divider
There is a Q-divider factor [2..15] for the stm32f412 serie
which supplies the 48MHz clock.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2024-12-13 20:05:11 +01:00
Laurentiu Mihalcea
3651725316 dts: xtensa: nxp_imx8: add edma power domains
Add power domains for EDMA0's channels 6, 7, 14, and 15.
For QM these are identified as IMX_SC_R_DMA_2_*, while
for QXP thy are identified as IMX_SC_R_DMA_0_*.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2024-12-13 20:05:00 +01:00
Laurentiu Mihalcea
2eecf88698 dts: xtensa: nxp_imx8: move up the definition of system-controller
This has no address space and doesn't belong between peripheral
nodes. Move it up the DTSI for better visibility. No functional
change.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2024-12-13 20:05:00 +01:00
Laurentiu Mihalcea
c8a984708c dts: xtensa: add imx8qm and imx8qxp DTSI variants
imx8qm and imx8qxp have a couple of differences regarding
the peripheral address spaces and how the DT nodes are
configured, which is why using a generic DTSI (nxp_imx8.dtsi)
for the both of them is not right.

One of the differences between the two, which affects Zephyr
is the fact that irqstr's address space is different. Up until
now this has been dealt with at the board level (i.e:
imx8qxp_mek_mimx8qx6_adsp.dts), which is not right as this is not
board-specific, but rather soc-specific. Additionally, this
causes the following warning during compilation:

"unit address and first address in 'reg' (0x51080000) don't
match for /interrupt-controller@510a0000"

To fix this, add two new DTSIs: nxp_imx8qm and nxp_imx8qxp.
Each board (i.e: imx8qm_mek and imx8qxp_mek) will have to include
the DTSI for their soc instead of the generic DTSI (i.e: nxp_imx8).

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2024-12-13 20:05:00 +01:00
Rafał Kuźnia
413ca65d65 dts: common: nordic: nrf54l20: set timer frequency to 64MHz
The timer counter frequency is set to 64MHz as a workaround.

Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
2024-12-13 20:04:51 +01:00
Lothar Felten
c552379f0e drivers: input: cap12xx, support 3 to 8 channels
The Microchip CAP12xx series are available in 3, 6 or 8 channel versions.

Co-authored-by: Benjamin Cabé <kartben@gmail.com>

Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
2024-12-13 17:44:35 +01:00
Lothar Felten
058f107089 drivers: input: cap1203, rename to cap12xx
rename cap1203 to cap12xx to support 3 to 8 channels

Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
2024-12-13 17:44:35 +01:00
Ricardo Rivera-Matos
6d30055809 dts: charger: bq24190: Documents the ce-gpio
Documents the charge enable (ce) gpio.

Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
2024-12-13 11:35:17 +01:00
Tuomas Parttimaa
342c25924d dts: nordic: Add SUIT storage partition for nRF9280 SiP
Add definition of the SUIT storage partition for the nRF9280 SiP.

Signed-off-by: Tuomas Parttimaa <tuomas.parttimaa@nordicsemi.no>
2024-12-13 11:34:55 +01:00
Xudong Zheng
d2010e7750 dts: arm: rpi_pico: remove default startup-delay-multiplier from .dtsi
The default is defined in dts/bindings/clock/raspberrypi,pico-xosc.yaml.

Signed-off-by: Xudong Zheng <7pkvm5aw@slicealias.com>
2024-12-13 11:34:14 +01:00
Marcio Ribeiro
674529e11b dts: esp32: fix sram0 start address for esp32c2 and esp32c3
Changes the sram0 start address from 0x4037_0000 to 0x4037_C000 for:
- esp32c2
- esp32c3

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-12-12 19:59:44 +01:00
Miguel Gazquez
d0785cc39b dts: bindings: add DT binding for the Nintendo Nunchuk joystick
Add a binding for the Nintendo Nunchuk joystick through the I2C bus.

Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
2024-12-12 18:38:06 +01:00
The Nguyen
be28d391fe dts: arm: renesas: add support for UDC on Renesas RA SoC
Add device node to support UDC driver on these SoC: RA6M3,RA6M5,
RA8M1, RA8D1

Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
2024-12-12 16:23:48 +01:00
The Nguyen
2cfd6065dd drivers: udc: add support for Renesas RA USB device
First commit to support UDC on Renesas RA USBHS module

Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
2024-12-12 16:23:48 +01:00
Gerard Marull-Paretas
e41919abb3 dts: arm: nordic: nrf54l05/10/15: fix cpuapp_vevif_rx reg
The reg address was not equal to the one in the node name, producing
a build warning.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2024-12-12 16:20:31 +01:00
Marek Matej
a7a05b9e7f dts: espressif: Update AMP sram nodes for ESP32 and ESP32-S3
Set AMP dts nodes (ipm, mbox, ...) to use fixed locations in reserved
memory areas. Those areas memories are delimited in the `memory.h`.
Size of the occupied areas can be calculated but the dts nodes addresses
needs to be set manually in every case.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-12-12 11:38:22 +01:00