Update the memory layout of nrf54lm20a for TF-M builds so that
it does not reserve any memory for FLPR since it is not supported
with TF-M.
This affects both the SRAM and the RRAM partitioning.
I moved the SRAM partitioning to the nrf54lm20a_ns_partition.dtsi
and removed it from individual board files so it can be updated
for all the platforms in one place.
Signed-off-by: Georgios Vasilakis <georgios.vasilakis@nordicsemi.no>
Update the memory layout of nrf54l15 for TF-M builds so that
it does not reserve any memory for FLPR since it is not supported
with TF-M.
This affects both the SRAM and the RRAM partitioning.
To do that I refactored the dts files, specifically:
1) I created new files for the _ns targets since they have
different available RRAM/SRAM sizes now.
2) I moved the SRAM partitioning to the nrf54l15_ns_partition.dtsi
and removed it from individual board files so it can be updated
for all the platforms in one place.
Signed-off-by: Georgios Vasilakis <georgios.vasilakis@nordicsemi.no>
Add zephyr,entropy and sets to TRNG0. This is needed by
the random subsys when using entropy device.
Signed-off-by: Flavio Ceolin <flavio@hubblenetwork.com>
Implement interrupt settings to expand the driver to RZ/V2H, V2N SoCs
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Add phyCORE-1170 SOM dtsi for streamlined inclusion on carrier
boards and uses a dual-core NXP i.MX RT1170 SoC as a basis.
Signed-off-by: Florijan Plohl <florijan.plohl@norik.com>
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Move the ethernet controller clocks from mac node to controller node.
This change simplifies how clocks are gathered and handled in STM32
ethernet drivers.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add a new sleep-mode-enable property for the Cirque Pinnacle input driver,
to enable the sleep-mode for those peripherals, which will go into a lower
power state after 5 seconds with no fingers detected.
Signed-off-by: Peter Johanson <peter@peterjohanson.com>
Add boolean properties to control whether the reference voltage buffers are
enabled or not. After reset the positive reference buffer is enabled and
the negative is disabled.
Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
Add input-channels and inputmux-connections properties to the
nxp,sctimer-pwm device tree binding to support SCTimer input
capture configuration.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Clarify that the prescaler value divides the clock by (prescaler + 1),
not by the prescaler value directly. This helps users understand the
actual clock division behavior.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add device tree binding properties for PWM input capture filtering
functionality to the NXP i.MX PWM driver binding.
New properties added:
- input-filter-count: Configure number of consecutive samples
required before accepting input transitions
- input-filter-period: Set sampling period in IPBus clock cycles
for input capture filtering
These properties enable configuration of input filtering to reduce
noise and improve signal integrity for PWM capture operations.
Setting filter period to 0 bypasses the input filter entirely.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Adding support for running Zephyr OS as a guest virtual machine
in the QNX Hypervisor environment.
This change introduces a new board configuration for ARM64-based
QNX Hypervisor VM.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
In order to make some basic tests on the OTP API, add an OTP memory
emulator driver. It implements the .program() and .read() APIs.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
To add support for LTR553, we will migrate device-tree
properties to new ones and mark the old ones as deprecated.
We will also refactor variable names accordingly.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This is a workaround to fix a bug that failed
to access registers of display irqsteer when
display mix is in power off state.
- Display irqsteer is in display mix, need to
power on display mix firstly.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
We updates all the UART hardware nodes for all MEC parts with
properties used by the new, common UART driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
We modified the Microchip MEC UART driver to be HAL
independent and be usuable on all MEC SoCs. The only
hardware difference is an extra register in the MEC174x/5x
family providing TX FIFO full and current byte count.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add proper support for the 1-bit CAN protocol engine clock multiplexer
present in some NXP FlexCAN instances.
Both possible input clocks are now represented as named clocks in the
devicetree nodes ("clksrc0" and "clksrc1") and the existing devicetree
property "clk-source" now selects the correct clock in addition to setting
the multiplexer bit (CLKSRC) in the FlexCAN CTRL1 register.
Fixes: #94517
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Make the clk-source property of the NXP FlexCAN devicetree nodes optional
as not all FlexCAN instances have an internal clock multiplexer.
Remove the clk-source property from the SoCs where the internal clock
multiplexer is not present, limit the values this property can be assigned,
and default the clock selection bit to 0 in the driver.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The TI AM62L is a low-power ARM Cortex-A53 based SoC with display for
IOT, HMI and general purpose applications. More information here:
https://www.ti.com/product/AM62L
Add initial SoC and DTS support here.
Signed-off-by: Andrew Davis <afd@ti.com>
- add some necessary static parameter for pit instances
- Enable counter_basic_api case by using pit0 instance
- Test counter_basic_api passed
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
In order to comply to NIST SP800-90B, the STM32 RNG should set its
registers as documented in Application Note AN4230 (Rev12, Table 3) [1].
To that effect, some values have been modified to match the table, and some
have been added.
For STM32H7R/S and WBA, configure the RNG as per configuration C of the
Reference Manual since the NSCR register is not available yet (internal
issues 221082 and 221083).
[1]: https://www.st.com/resource/en/application_note/dm00073853.pdf
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Some STM32 series need to configure the RNG source noise control register
for NIST SP800-90B compliance.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add DT properties to select CK48M source for GD32 RCU.
Apply CK48M source selection during early SoC init.
Signed-off-by: Aleksandr Senin <al@meshium.net>
Add MAX31331 RTC driver, an ultra-low-power real-time clock (RTC)
that provides timekeeping with
extremely low current consumption (65 nA).
Signed-off-by: Francis Roi Manabat <francisroi.manabat@analog.com>
Replaced display-controller.yaml with lcd-controller.yaml
Deleted pixel format property, replacing it with the
property on lcd-controller.yaml. Replace ILI9XXX RGB macro
with PANEL RGB macro. Also, added condition to verify pixel
format is RGB565, BRG565 or RGB888, otherwise it will show error
Replaced <zephyr/dt-bindings/display/ili9xxx.h> with
<zephyr/dt-bindings/display/panel.h> and
ILI9XXX_PIXEL with PANEL_PIXEL in some Devicetrees
and files that contained both elements. Fixed some
script sintax. Deleted drivers/display/display_ili9xxx.c
Signed-off-by: Nicolas Moreno <niko722795@gmail.com>
ILI9341 is not deploying correctly the display sample.
The screen looks mirrored vertically and the color
doesn't match with the sequence expected. To fix it,
change the Memory Access Control configuration data.
Signed-off-by: Nicolas Moreno <niko722795@gmail.com>
Update EDMA device tree nodes for NXP MCXE31B platforms to align
with the unified EDMA driver implementation.
Signed-off-by: Qiang Zhang <qiang.zhang_6@nxp.com>
