Add EDAC driver for NXP MECC64 IP providing ECC functionality
for On-Chip RAM (OCRAM). The driver supports:
- 4 independent OCRAM banks with ECC protection
- Single-bit error correction and double-bit error detection
- Error injection for testing purposes
- Interrupt-driven error reporting
- Device tree based configuration
- Standard Zephyr EDAC API implementation
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
Enable the on-chip BLE controller on BL60x boards (bl604e_iot_dvk,
ai_wb2_12f_kit): include bl60x_em_8kb.dtsi to reduce sram0 to 168 KB
(8 KB exchange memory carved from the top of SRAM, GLB_EM_SEL=3),
add zephyr,bt-hci chosen, and activate the bt-hci and TRNG nodes.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add devicetree binding for the TE Connectivity MS5637 digital
pressure and temperature sensor. The sensor communicates via I2C
at fixed address 0x76.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Remove leading zero from main_timer0_pd power domain unit address.
The Device Tree Compiler warns about unit addresses with leading zeros:
Warning (unit_address_format): /power-domains/power-domain@0f:
unit name should not have leading 0s
Signed-off-by: Soumya Tripathy <s-tripathy@ti.com>
Add System Clock Controller for the M480 nuvoton MCU.
This only adds the base driver to setup HIRC, HXT, LIRC, LXT and
PLL. Configuring the PLL driver from a target frequency with
calculating values to best match this frequency.
Signed-off-by: Fiona Behrens <me@kloenk.dev>
Add missing `0x` prefix to the RTC base address in `r7fa4l1bx`
and `ra4-cm33-common` SoC devicetree. This ensures the reg
property is interpreted as a hexadecimal value.
Signed-off-by: Khai Cao <khai.cao.xk@renesas.com>
ppib121 node was missing offset that need to be applied when
setting up a connection between DPPI130 and DPPI120.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Both STM32F1 and STM32C5 series have RTC interrupt going through EXTI.
Add the corresponding property to these series' root DTSI.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
enable thermal_cap for cpu_freq subsystem, which allows
CPU frequency to be reduced when the die temperature
exceeds certain thresholds.
This is useful for preventing overheating and maintaining
system stability under high load or in high ambient
temperatures.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Remove st,stm32-sdio devicetree binding and extend
st,stm32-sdmmc to cover the SDHC/SDIO host-controller use case.
This keeps a single STM32 SDMMC hardware compatible in devicetree
and avoids interface-specific compatible selection.
Signed-off-by: Sara Touqan <zephyr@exalt.ps>
Signed-off-by: Sarah Younis <zephyr@exalt.ps>
Signed-off-by: Mohammad Odeh <zephyr@exalt.ps>
This introduces APIs for input capture on the STM32.
Rename callback in data to alarm_cb to prevent confusion with other
callbacks.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Add bt-hci node to bl61x.dtsi using the shared bflb,bt-hci binding.
Add exchange memory overlays for 32 KB and 64 KB configurations
that reduce WRAM available to the application when BLE is enabled.
Signed-off-by: William Markezana <william.markezana@gmail.com>
The RT1020, RT1024, and RT1050 SoC variants do not include a third
FlexCAN controller (flexcan3) in hardware. The current device tree
definitions incorrectly inherit this node from the base RT10xx device
tree.
This patch removes the flexcan3 node (can@401d8000) from the following
SoC-specific device tree files:
- nxp_rt1020.dtsi
- nxp_rt1024.dtsi
- nxp_rt1050.dtsi
Signed-off-by: William Tang <william.tang@nxp.com>
Add devicetree binding for the TE Connectivity HTU31D digital
humidity and temperature sensor. The sensor communicates over I2C
at address 0x40 or 0x41 depending on the ADDR pin configuration.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add devicetree nodes for the MSPM0 watchdog peripherals and
set them disabled by default.
Signed-off-by: Sanjay Vallimanalan <sanjay@linumiz.com>
Signed-off-by: Jackson Farley <j-farley@ti.com>
Add the device tree file for the SoC AB1C1F4M51820PH0. This file
will host the SoC specific peripheral instances in addition to the
common resources inherited from balletto_common.dtsi.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add the pinctrl node for the balletto family. Balletto shares the
pin control architecture with Alif Ensemble.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add clock controller node for the balletto family. Balletto
family shares the same clock module architecture with Ensemble
differing only in the absence of the HP core configuration
region (m55_cfg).
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Make the m55hp_cfg register block optional to support single-core
Alif SoCs (such as from the Balletto family) that only have the
Cortex-M55 HE subsystem. Multi-core SoCs that have both RTSS-HE
and RTSS-HP subsystems require all 7 register blocks.
Update the binding documentation accordingly.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add fixed-clock nodes for some of the Balletto family root clocks.
These clocks serve as input sources for peripheral clocks managed
by the clock controller.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Balletto SoCs have a peripheral region at 0x1A000000 (8 MB)
that hosts peripherals such as pinmux and clock control registers.
This deviates from the standard Cortex-M memory map and requires
explicit MPU configuration with device memory attributes.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
The Alif Balletto family of processors contain a single
Cortex-M55 core residing in the High Efficiency Real Time
Subsystem (RTSS-HE).
Add a common device tree file that serves as the foundation
for all SoCs in the Balletto family. This file currently defines
the CPU, MPU, TCM and NVIC nodes that are common across the family.
Peripheral instances shared across all Balletto SoCs will be
added to this file as driver support is introduced in future
patches.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
The ocram1_available address is ocram1+0x4000.
According to DTSpec v0.3, Section 2.3.8:
> If the property is defined with an empty value, it specifies
that the parent and child address spaces are identical, and
no address translation is required.
If the property is not present in a bus node, it is assumed that
no mapping exists between the child address space and the parent
address space.
So should add empty range. Otherwise the ocram1_available address
is 0x4000.
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
The PCA series GPIO driver was updated to allow disabling automatic
reset. This feature would enable GPIO expander ports to retain states
which could be helpful for situations where certain pins are configured
in the bootloader and their states need to be retained when switching to
application code.
Signed-off-by: Lay Desai <lay.desai@he360.com>
The examples used "xlnx,versal-ipi-mailbox" and
"xlnx,versal-ipi-dest-mailbox" which do not match the actual
compatible strings defined in the binding.
Signed-off-by: Harini T <harini.t@amd.com>
Set the OSPI memory mapped timeout period to avoid keeping the chip
select line asserted indefinitely after memory mapped accesses.
This is needed when OSPI1 and OSPI2 operate simultaneously with shared
IO0-IO3 and CLK lines, and both instances use memory mapped mode.
The timeout period follows the recommendation from the STM32U575xx and
STM32U585xx device errata, ES0499 section 2.6.4.
Allow dqs-port to be set to 0. The STM32 HAL uses value 0 to indicate
that the DQS port is not used.
Update the debug log printed when CONFIG_STM32_MEMMAP is not enabled,
because stm32_ospi_set_memorymap() is not called in that case.
Signed-off-by: Kirill Shypachov <kshypachov@outlook.com>
