make riscv,isa dt prop no longer required,
as it is is not really used by anyrhing in zephyr
and we now have a alternative (riscv,isa-base
and riscv,isa-extensions).
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add power domain for irqsteer in display mix.
Must power on the display mix before accessing
registers of display irqsteer.
When disp_irqsteer node is enabled, please
enable option CONFIG_PM_DEVICE.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Add initial support for the Versal Gen 2 SoC APU, which is based on
the Arm Cortex-A78 processor. It includes basic wiring for memory
regions, UART, interrupt controller, and timer.
The versal2_apu.dtsi file defines peripherals shared across the SoC,
while versal2_a78.dtsi captures peripherals private to the Cortex-A78
processor. These device trees lay the groundwork for further APU-based
development on the Versal Gen 2 platform.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
The compatible for the last GPIO banks in Microchip MEC5
chip DTSI was not changed when the GPIO driver was updated.
We changed the compatible to the correct name.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
The new node is called "npu_cache".
This way a possibility is offered to choose - thru an overlay - if to
enable the NPU cache or not.
This new node has a dependency with node "npu", so the NPU cache's
status is taken into account only in case node "npu" has status "okay".
Default status value of "npu_cache" is "okay"
(i.e. enable the NPU cache).
Signed-off-by: Wolfgang Betz <wolfgang.betz@st.com>
Mark unused pinctrl and wuc nodes in it8xxx2 with /omit-if-no-ref/,
so that they are omitted from the final devicetree when not referenced.
After this change, test: "west build -p always -b it8xxx2_evb" shows a
reduction in devicetree size:
Before:
build/zephyr/zephyr.dts 164,449 bytes
build/zephyr/include/generated/zephyr/devicetree_generated.h
3,125,359 bytes
After:
build/zephyr/zephyr.dts 124,108 bytes
build/zephyr/include/generated/zephyr/devicetree_generated.h
1,892,313 bytes
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit prefixes pre-generated nodes with
`/omit-if-no-ref/` to keep the generated devicetree
C headers minimal.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
- add SDHC driver code to support both SDMMC and SDIO fucntion
- add SDHC dts node and Kconfig
- add clock configuration for SDHC
Signed-off-by: Kevin Chan <kevin.chan3@infineon.com>
Add devicetree support for PSOC 4100S Max series including:
- Base SoC dtsi with GPIO, UART, HSIOM peripherals
- 100-TQFP package dtsi for pin multiplexing
- CY8C4149AZI-S598 MPN-specific devicetree include
- Updated compatible strings for PSOC 4 support
- Clock structure with clk_hf and clk_pump nodes
- Simplified peripheral clock naming (peri_clk_div)
- PSOC4xx clock source definitions and bindings
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
- Add the rtc node for the stm32u3
- This enables RTC support for STM32U3 platforms once enabled
Signed-off-by: Antoine Pradoux <antoine.pradoux@st.com>
- There was a mistake with the CM33 core. It does
not have ITCM/DTCM. Only the CM55 core does.
- Also enabled ITCM/DTCM in the cm55 board file.
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Microchip MEC1653B has 416KB of SRAM. ARM ICCM SRAM is 356KB
starting at 0xC0000. ARM DCCM SRAM is 64KB starting at 0x118000.
Chip DTS file had incorrect ICCM starting address.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This is technically a workaround for a limitation in the Pygments DTS
lexer causing the highlighting to break when rendering this example
in the documentation, but this is also an excuse to plug the label that
is used in the official auxdisplay sample.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The STM32N6 has a BSEC peripheral for the OTP management, add it to the
SoC device tree file. Moreover, there are 4 OTP words dedicated for
Ethernet MAC addresses, describe them in the NVMEM layout.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Introduce the Boot and SECurity(BSEC) control driver. The BSEC
peripheral manages the accesses to an embedded one time
programmable(OTP) array of fuses. Those fuses are used to store
on-chip, non-volatile data like boot and security parameters (e.g:
secret keys, non-volatile counters, etc...).
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
