dts: xtensa: add imx8qm and imx8qxp DTSI variants
imx8qm and imx8qxp have a couple of differences regarding the peripheral address spaces and how the DT nodes are configured, which is why using a generic DTSI (nxp_imx8.dtsi) for the both of them is not right. One of the differences between the two, which affects Zephyr is the fact that irqstr's address space is different. Up until now this has been dealt with at the board level (i.e: imx8qxp_mek_mimx8qx6_adsp.dts), which is not right as this is not board-specific, but rather soc-specific. Additionally, this causes the following warning during compilation: "unit address and first address in 'reg' (0x51080000) don't match for /interrupt-controller@510a0000" To fix this, add two new DTSIs: nxp_imx8qm and nxp_imx8qxp. Each board (i.e: imx8qm_mek and imx8qxp_mek) will have to include the DTSI for their soc instead of the generic DTSI (i.e: nxp_imx8). Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
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5 changed files with 167 additions and 79 deletions
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@ -6,7 +6,7 @@
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/dts-v1/;
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#include <nxp/nxp_imx8.dtsi>
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#include <nxp/nxp_imx8qm.dtsi>
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#include "imx8qm_mek_mimx8qm6_adsp-pinctrl.dtsi"
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/ {
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@ -6,7 +6,7 @@
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/dts-v1/;
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#include <nxp/nxp_imx8.dtsi>
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#include <nxp/nxp_imx8qxp.dtsi>
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#include "imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi"
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/ {
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@ -31,7 +31,3 @@
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pinctrl-0 = <&sai1_default>;
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pinctrl-names = "default";
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};
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&irqsteer {
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reg = <0x51080000 DT_SIZE_K(64)>;
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};
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@ -32,79 +32,6 @@
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};
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};
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irqsteer: interrupt-controller@510a0000 {
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compatible = "nxp,irqsteer-intc";
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reg = <0x510a0000 DT_SIZE_K(64)>;
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power-domains = <&irqstr_pd>;
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#size-cells = <0>;
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#address-cells = <1>;
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master0: interrupt-controller@0 {
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compatible = "nxp,irqsteer-master";
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 19 0 0>;
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};
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master1: interrupt-controller@1 {
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compatible = "nxp,irqsteer-master";
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reg = <1>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 20 0 0>;
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};
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master2: interrupt-controller@2 {
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compatible = "nxp,irqsteer-master";
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reg = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 21 0 0>;
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};
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master3: interrupt-controller@3 {
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compatible = "nxp,irqsteer-master";
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reg = <3>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 22 0 0>;
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};
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master4: interrupt-controller@4 {
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compatible = "nxp,irqsteer-master";
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reg = <4>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 23 0 0>;
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};
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master5: interrupt-controller@5 {
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compatible = "nxp,irqsteer-master";
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reg = <5>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 24 0 0>;
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};
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master6: interrupt-controller@6 {
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compatible = "nxp,irqsteer-master";
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reg = <6>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 25 0 0>;
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};
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master7: interrupt-controller@7 {
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compatible = "nxp,irqsteer-master";
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reg = <7>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 26 0 0>;
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};
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};
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sram0: memory@92400000 {
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device_type = "memory";
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compatible = "mmio-sram";
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83
dts/xtensa/nxp/nxp_imx8qm.dtsi
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83
dts/xtensa/nxp/nxp_imx8qm.dtsi
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@ -0,0 +1,83 @@
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/*
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* Copyright 2021, 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nxp/nxp_imx8.dtsi>
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/ {
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irqsteer: interrupt-controller@510a0000 {
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compatible = "nxp,irqsteer-intc";
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reg = <0x510a0000 DT_SIZE_K(64)>;
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power-domains = <&irqstr_pd>;
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#size-cells = <0>;
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#address-cells = <1>;
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master0: interrupt-controller@0 {
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compatible = "nxp,irqsteer-master";
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 19 0 0>;
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};
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master1: interrupt-controller@1 {
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compatible = "nxp,irqsteer-master";
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reg = <1>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 20 0 0>;
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};
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master2: interrupt-controller@2 {
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compatible = "nxp,irqsteer-master";
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reg = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 21 0 0>;
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};
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master3: interrupt-controller@3 {
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compatible = "nxp,irqsteer-master";
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reg = <3>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 22 0 0>;
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};
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master4: interrupt-controller@4 {
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compatible = "nxp,irqsteer-master";
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reg = <4>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 23 0 0>;
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};
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master5: interrupt-controller@5 {
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compatible = "nxp,irqsteer-master";
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reg = <5>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 24 0 0>;
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};
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master6: interrupt-controller@6 {
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compatible = "nxp,irqsteer-master";
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reg = <6>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 25 0 0>;
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};
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master7: interrupt-controller@7 {
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compatible = "nxp,irqsteer-master";
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reg = <7>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 26 0 0>;
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};
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};
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};
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82
dts/xtensa/nxp/nxp_imx8qxp.dtsi
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82
dts/xtensa/nxp/nxp_imx8qxp.dtsi
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@ -0,0 +1,82 @@
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/*
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* Copyright 2021, 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nxp/nxp_imx8.dtsi>
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/ {
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irqsteer: interrupt-controller@51080000 {
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compatible = "nxp,irqsteer-intc";
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reg = <0x51080000 DT_SIZE_K(64)>;
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power-domains = <&irqstr_pd>;
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#size-cells = <0>;
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#address-cells = <1>;
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master0: interrupt-controller@0 {
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compatible = "nxp,irqsteer-master";
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 19 0 0>;
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};
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master1: interrupt-controller@1 {
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compatible = "nxp,irqsteer-master";
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reg = <1>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 20 0 0>;
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};
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master2: interrupt-controller@2 {
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compatible = "nxp,irqsteer-master";
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reg = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 21 0 0>;
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};
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master3: interrupt-controller@3 {
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compatible = "nxp,irqsteer-master";
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reg = <3>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 22 0 0>;
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};
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master4: interrupt-controller@4 {
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compatible = "nxp,irqsteer-master";
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reg = <4>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 23 0 0>;
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};
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master5: interrupt-controller@5 {
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compatible = "nxp,irqsteer-master";
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reg = <5>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 24 0 0>;
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};
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master6: interrupt-controller@6 {
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compatible = "nxp,irqsteer-master";
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reg = <6>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 25 0 0>;
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};
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master7: interrupt-controller@7 {
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compatible = "nxp,irqsteer-master";
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reg = <7>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 26 0 0>;
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};
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};
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};
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