Allow using other references by removing the hard requirement on it being
internal. To be able to use internal voltage, the DT property ti,vrefp can
be used, otherwise it is ignored.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
For othre Nordic targets we are chosing and enabling the controller
for the dts/arm/nordic DTS files. But this was not how it was added
for the nrf54lm20.
Let's move these to the same place, for consistency, and so that it
is also enabled in the same way for the simulated nrf54lm20bsim
(whose board file includes these same dtsi files)
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Only 511 kB of RAM is available for usage currently
on nRF54LM20A. The non-secure variant used the full 512
which causes boot loops. Reduce the non-secure ram down to
252 to reduce below the 511 kB while still following
the 4 kB page alignment requirements in TF-m
Signed-off-by: Dag Erik Gjørvad <dag.erik.gjorvad@nordicsemi.no>
Some SoC series allow USB controller to be disabled temporarily
on unplug, and then enabled back on re-plug. Add support for such
configuration option in DT and UDC driver.
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
This commit adds sample amp-talk to demonstrate the openamp communication
between DSP and CM core.
It also uses multiple openamp instances on primary core to communicate with
other CM core and also DSP core.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
Add pwm-mode device tree property to allow configuration of TPM PWM
operation mode. Supports edge-aligned (0) and center-aligned (1) PWM
modes. Defaults to edge-aligned PWM if not specified.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Fixes various issues with how these have been used:
- Reserved memory was wrongfully used to describe an RRAM area
for a CPU
- Reserved memory was wrongfully used to describe an SRAM area
for a CPU
- A partition described using reserved memory did not have the
required NVM erase size and write size parameters set for it
- RRAM partitions were not correctly setting ranges properties
- RRAM validation wrongly took the "base flash controller" into
considering because it was not using unit addresses
- RRAM partitions incorrect set up so that they collided with
one another for different cores
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Drop the leading article from the 'zephyr' vendor name in
vendor-prefixes.txt so vendor names sort more naturally in the Supported
Boards[1] lists.
[1]: https://docs.zephyrproject.org/latest/boards/index.html
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Add a base binding for interrupt and io-channel nexus nodes.
This makes the implicit definitions explicit.
Replace existing individual map definitions with this.
This file does not define a specific `compatible` on its own,
So you should include this file before using it practically.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
They must be `array` type to match the existing `interrupt-map-mask`
and `interrupt-map-pass-thru`.
And also, updating descriptions.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Adds a new clock destination binding to the Infineon scb and tcpwm
peripherals. This field is used to connect the peripheral to a
peripheral clock.
Signed-off-by: John Batch <john.batch@infineon.com>
- Change base register for TCPWM to 0x40200000
which controls the entire IP block.
- Enabling/Disabling counters and handling
global interrupts.
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Add initial support for the Versal SoC APU, which is based on
the Arm Cortex-A72 processor. It includes basic wiring for memory
regions, UART, interrupt controller, and timer.
This commit introduces the SoC definition and MMU configuration
required for APU-based development on the Versal platform.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
This commit adds support for the Xilinx AXI Ethernet Lite device,
also known as the emaclite.
The emaclite is a light-weight 10/100 MII Ethernet device.
It foregoes a DMA to reduce chip area.
Instead, it uses memory-mapped transmit/receive buffers.
A selection of features can optionally be enabled:
- a second ("pong") RX/TX Buffer
- MDIO support
- Interrupt support
This driver handles the MAC functionality of the core;
a driver for the MDIO part is introduced separately
as an MDIO driver.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
This commit adds support for the Xilinx AXI Ethernet Lite device,
also known as the emaclite.
The emaclite is a light-weight 10/100 MII Ethernet device.
It can optionally be configured to include an MDIO.
The MMIO interface is controlled via MMIO registers and requires
the software to busy-wait until completion.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
