Correct a clock initialization ordering issue where IMO, an internal
high speed oscillator, was being setup before ILO. This does not match
the MTB initialization order and would cause the part to fault.
Sets up the default clock configuration on the part to be 48MHz. Adjusts
the default WCO (low speed external crystal source) to be 32768 as the
eval board has this crystal on it. Enables common clock elements
(hf_clk, clock_pump) as needed in the part dts rather than the board.
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Correct a clock initialization ordering issue where IMO, an internal
high speed oscillator, was being setup before ILO. This does not match
the MTB initialization order and would cause the part to fault.
Sets up the default clock configuration on the part to be 48MHz. Adjusts
the default WCO (low speed external crystal source) to be 32768 as the
eval board has this crystal on it. Enables common clock elements
(hf_clk, clock_pump) as needed in the part dts rather than the board.
Signed-off-by: Tom Burdick <thomas.burdick@infineon.com>
The GPIO interrupts were incorrectly set to priority 4 on an m0 with
only 4 priorities, max is 3. Several of the gpio ports were missing
their interrupt property as it is a shared interrupt number but the
driver seems to account for this. Added the missing interrupt property
on these ports.
Signed-off-by: Tom Burdick <thomas.burdick@infineon.com>
We converted the QMSPI-LDMA driver to linux style with a local
register header in the driver folder. This is part of the long
term plan to remove the MEC5 HAL and have common drivers for
as many SoC's as possible. QMSPI register definitions are in
the SoC layer to be shared with other drivers (MSPI). The driver
was also updated based on changes in the SPI config structure.
The lastest SPI config structure changes force hardware controlled
chip selects and GPIO controlled chip selects to be mutually exclusive.
NOTE: driver works with the flash driver sample
and passes the common flash driver test.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Before that commit spi was not available for the soc sy1xx.
With this commit a basic usage of spi is possible.
Signed-off-by: Sven Ginka <s.ginka@sensry.de>
Co-authored-by: Fin Maaß <f.maass@vogl-electronic.com>
This change adds optional reset via GPIO support to u-blox M8 driver.
This is useful if host is reset separately from the u-blox M8 GNSS
receiver.
Signed-off-by: Vytautas Virvičius <vytautas@virvicius.dev>
reg attribute is supposed to hold start address and size
instead of start address and end address. This caused
a crash in malloc_prepare().
Signed-off-by: Damian Krolik <damian.krolik@nordicsemi.no>
The out-div binding was removed as dts setting now aligns
literal value, not register value. This commit updates
the out-div node entry to be the literal values as the
translation is now handled in the driver.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
The out_div dts setting differs to the register setting
causing the frequency calcuation to be incorrect.
This was originally intended to be fixed in NRFX but
this requires further investigation on how to approach
translation of literal values to enums in NRFX. This PR
adds a helper function for the conversion for now and
changes the devicetree bindings to align with the literal
value.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
Add pinctrl support to the bcm2711 aux UART driver to allow
uart pin configuration via the pinctrl driver.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
The BCM2711 GPIO controller provides 58 GPIO pins (0-57) that can be
configured for various functions including GPIO input/output and
alternate functions for peripherals like SPI, I2C, UART, PWM, etc.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Add support for separate XI and XO tuning capacitor values for HFXO.
If two values are set, they are used for XI and XO respectively. If
a single value is set, it is used for both.
Add support for enabling internal DC bias on the XI input when using
an external clock source.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Since the previous values of sram0 and sram1 exceeded the maximum
SRAM size, this update is needed to prevent the MCU from halting
when accessing a restricted region.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Add device tree binding for ADH Technology GT5X series optical
fingerprint sensors (GT-511C1R, GT-511C3, GT-521F32, GT-521F52).
Signed-off-by: Siratul Islam <email@sirat.me>
Add Devicetree properties to configure I2C spike suppression length
for DesignWare I2C controllers.
The new properties allow specifying spike suppression values in terms
of the controller input clock cycles, in line with the I2C-bus
specification.
Signed-off-by: Shreehari HK <shreehari.hk@alifsemi.com>
The `clocks` property should always be provided, even if the driver does
not consume it for now. Mark property as required in binding and add it to
the STM32F723 DTSI where it is missing. While at it, add an example showing
how to override the `clocks` property in the binding.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
1. Reorganize LPC DTSI files into lpc subdirectory
2. Update boards/lpc devicetree references to use new paths
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
1. Reorganize IMX RT DTSI files into imxrt subdirectory
2. Update boards/imxrt devicetree references to use new paths
3. Update samples/imxrt overlay references to use new paths
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
1. Reorganize MCX DTSI files into mcx subdirectory
2. Update boards/mcx devicetree references to use new paths
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
1. Reorganize RW DTSI files into rw subdirectory
2. Update boards/rw devicetree references to use new paths
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
1. Reorganize IMX DTSI files into imx subdirectory
2. Update boards/imx devicetree references to use new paths
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
1. Reorganize S32 DTSI files into s32 subdirectory
2. Update boards/s32 devicetree references to use new paths
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
The current stm32 drivers will only enable soft NSS support if
the device is using a Zephyr managed GPIO for CS, or if the
CONFIG_SPI_STM32_USE_HW_SS flag is set. Neither of these are
actually appropriate for a peripheral, which doesn't control CS.
With this change, it is possible for the SPI interface to be
configured as a peripheral but still use soft NSS -- otherwise,
short of creating a "fake" GPIO configuration, the peripheral
will always use hard NSS, and for some boards/configurations,
that is unworkable. In the case of a board where the CS
is not hooked up, we can use soft NSS to allow the peripheral
to assume CS and be driven by the SPI clock signal alone.
Our board has only three signals (clock, COPI, POCI) enabled
on one of the SPI interfaces (it is communicating with another
MCU on the same board), and works with this change. Without
the change, we must enable a "fake" GPIO driver configuration
(which is never used for anything, and really makes little
sense for a peripheral, but it just happens to force the
driver to go down that code path). We cannot disable the
CONFIG_SPI_STM32_USE_HW_SS mechanism, as that impacts ALL
interfaces, and we have a second interface in controller
mode that speaks to flash and requires the NSS_HARD codepath.
Signed-off-by: Rob Newberry <rob@zenomoto.com>
Use lowercase 'a' instead of uppercase 'A' in hexadecimal notation
for consistency with coding style conventions.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
New binding added for the hfxo to define a startup-time-us.
Placeholder used based on fixed wait time and chirpTime,
xtallSettleTime, biasSearch defined in the IP.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
Binding for nrf71 HFXO support where startup-time-us prop
defaults, which will be replaced with optimal values at board level
in the future, as they depend on the specific crystal in use.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
Fix incorrect register base mapping in nxp_mcxaxx6_common.dtsi where
lpuart1 was erroneously mapped to the lpi2c0 base address (0x4009a000).
Correct the lpuart1 register base to 0x400a0000 to match the MCX A-series
reference manual.
The incorrect mapping caused duplicate unit-address warnings between
lpuart and i2c nodes and could lead to invalid register access and early
HardFault when lpuart1 is enabled.
The issue was not detected on reference boards as lpuart1 is not used
there
Signed-off-by: Siegurt Skoda <skoda@ph2.uni-koeln.de>
