Commit 57723cf405 ("dts: arm: st: Refactor DTSI files to use macro"),
which replaced raw hex codes by using STM32_CLOCK macro, causes
regression in the case of the CAN device where the previous raw value
contained more than one bit set to 1. The macro is in fact correct only
for values with a single bit set. In all other cases, raw values must
continue to be used.
Tested on STM32F429I-DISC1 board
Fixes: 57723cf405
Co-authored-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
The current nxp_mcxc141.dtsi sets the SRAMs base address
to 0x1FFF_F000. This leads to the mcxc141 faulting during
initialization when the first write to SRAM occurs:
z_prep_c -> z_bss_zero -> z_early_memset -> memset
The correct base address is 0x1FFF_F800. This information
is not obvious in the "MCX C24X Sub-Family Reference Manual,
Rev. 1, 07/2024". The address was taken from an MCUXpresso
IDE sample project.
Link: https://www.nxp.com/webapp/Download?colCode=MCXC24XP64M48RM
Signed-off-by: Maximilian Werner <maximilian.werner96@gmail.com>
ADC2 is no longer supported on ESP32C3 due to HW limitations.
Check silicon errata on Espressif website for more details.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Add clocks property to CPUs. nRF54Lx series is using hfpll as clock
source for CPU (and fast peripherals). CPU clock frequency can be
derived from frequency of the source clock so clock-frequency property
is removed from cpu as it is redundant.
nrfx/MDK expects that NRF_CONFIG_CPU_FREQ_MHZ define is set to correct
CPU frequency. Modified nrfx CMakeLists.txt to use clock frequency of
hfpll instead of CPU clock-frequency property.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add DT property to configure the LPSPI instance to use tristated output
instead of retained output when PCS is negated.
Turn on the config on a couple boards for test coverage.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Example for creating ICM42688 dt node uses old dt option names.
Fix by changing to newest dt option names.
Signed-off-by: Nikola Petrovic <nikolaptr6@gmail.com>
Improve the documentation of the IOMUXC GPR binding so that it is
clear what the cells in the specifier space of "pinmux" space mean. And
change the names of the cells to be more appropriate. "offset" instead
of "pin" and "mask" instead of "function" describes more precisely what
the cells in the specifier mean.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
- remove calculation of pinmux value for stm32 in device tree binding
documentation.
- stm32-pinctrl.yaml contains wrong calculation as can be compared to
#define STM32_PINMUX in stm32-pinctrl.h.
- stm32f1-pinctrl.yaml also contains different wrong calculation
compared to #define STM32F1_PINMUX in stm32f1-pinctrl.h.
Signed-off-by: Andreas Klinger <ak@it-klinger.de>
Add wsen_tids_2521020222501 driver with
the corrected name and compatibility with
the hal update as well as added new features.
Signed-off-by: Wajdi ELMuhtadi <wajdi.elmuhtadi@we-online.com>
Initial commit for a STM32L152 based GPIO expansion chip.
The mfxstm32l152 driver offers GPIO controller fonctions.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
To prevent duplication of include lines across tests, move DMA binding
include into max32655.dtsi.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Add a interface-name string for the CDC-ACM node, this allow setting a
string that is then set as iInterface, which can then be used downstream
in an udev rule such as:
SUBSYSTEM=="tty", ACTION=="add",
ATTRS{interface}=="my interface descriptor",
SYMLINK+="tty-my-device"
To create known aliases for these ports.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The exit latency and min residency is handled by sl_power_manager.
This improve power consumption by letting the device sleep longer.
Signed-off-by: Bastien Beauchamp <bastien.beauchamp@silabs.com>
Add TI OMAP interprocessor mailbox nodes for AM62X A53,
the user ID assignment is as per thec corresponding mailbox
interrupt assignment for the core. Also while at it update the
supported feature list in corresponding boards.
More details can be found in the device TRM Mailbox section:
https://www.ti.com/lit/ug/spruiv7a/spruiv7a.pdf
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Add TI OMAP interprocessor mailbox nodes for AM62X M4,
the user ID assignment is as per thec corresponding mailbox
interrupt assignment for the core.
More details can be found in the device TRM Mailbox section:
https://www.ti.com/lit/ug/spruiv7a/spruiv7a.pdf
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
TI OMAP mailbox is the inter-processor mailbox IP found in TI
K3 devices (AM62X, AM64X, J721E .etc). The mailbox hardware uses
a queued mailbox interrupt mechanism that provides a communication
channel between processors through a set of registers and their
associated interrupt signals by sending and receiving messages.
The interrupt/bank associated with each processor entity is found
through the usr_id property from device tree.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Switch the default entropy driver for 54L05/10/15 devices to the new
CRACEN based one.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Change the property names in the bindings and overlay
to use hyphens(-) for separation instead of underscores(_).
Signed-off-by: James Roy <rruuaanng@outlook.com>
Add a new binding for STM32 RNG instances without interrupt lines,
such as the one present in the STM32WB05/06/07 SoCs.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
The enet2 node in nxp_rt1060.dtsi incorrectly references &enet_ptp_clock
for its nxp,ptp-clock property. This commit updates the reference to
&enet2_ptp_clock.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Add `#address-cells = <0>;` to interrupt provider nodes in
the NXP S32 device tree to resolve warnings: e.g.
Warning (interrupt_provider): /soc/interrupt-controller@47800000: Missing
Warning (interrupt_provider): /soc/siul2@40520000/eirq0@40520010: Missing
This ensures compliance with device tree specifications and
eliminates build warnings.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This commit replaces a bunch of ifdefs and bindings with a single
extensible binding, and makes all standard mtime system timers consistent.
Signed-off-by: Camille BAUD <mail@massdriver.space>
In order to allow a custom disk name same as with the standard
sdmmc driver an additional device-tree property was introduced.
Signed-off-by: Carlo Kirchmeier <carlo.kirchmeier@zuehlke.com>
Split the USART driver into separate implementations for Silabs Series 2
and Series 0/1 boards. This change improves maintainability (especially
with the support of pin-ctrl and clock-ctrl on series 2 boards).
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
