Remove the "cpus" node from the SoC device tree. The Zynq-7000
comes with either 1 or 2 CPU cores. While all the different
models within this SoC family have different capabilities in
particular when it comes to the programmable logic part and
I/O pins, there is no difference between the XC7Zxxx (2 cores)
and XC7ZxxxS (1 core) models when it comes to the peripherals
integrated in the SoC. Therefore, it makes little sense to
add a zynq7000s.dtsi next to the existing zynq7000.dtsi whose
only difference is the CPU count. Instead, the "cpus" node,
containing the appropriate CPU core definitions for the SoC
the respective target is equipped with, shall be specified at
the board level instead.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
Build shows warning due to incompatible
CPU vendor name. This fixes it and applies
necessary changes in files.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Initial implementation of a simple GPIO controlled power domain.
It exposes no API of its own, all functionality is contained inside
the runtime power management callbacks.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add support for power domains on Zephyr. Power domains are implemented
as simple devices so they can use the existent Zephyr API, for resume
and suspend sync and async and also reference count.
The pm subsystem will ensure that domains are resumed before and
suspended after devices using them. For device runtime power
management, every time the device is got or released the same actions
is done to the domain it belongs.
As domains are implemented as simple devices, it is totally acceptable
a domain belongs to another domain.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Adds power state definitions for RT1170. Min residency times are loosely
derived from transition times into similar power states in the datasheet
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds power state definitions for RT1160. Min residency times are loosely
derived from transition times into similar power states in the datasheet
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enables basic power management for the RT11xx series SOCs. The following
power saving measures are currently implemented:
- system reduces core voltage during sleep
- core clock can be gated in deep sleep
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for disabling automatic retransmission of CAN frames
(similar to CAN "one-shot" mode in the Linux kernel).
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Pin controller address is the same for all member of the
GEN3 SoC Series, but pinmux configuration is SoC specific.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Renesas R-Car series contains a PFC (Pin Function Controller).
This module consists of registers for selecting the function of
the multiplexed pins and controls the pull-up resistor on each pin.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Remove the unused base binding for CAN bus devices (as in devices
present on a CAN bus). This binding should have been removed in
2269408572
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
On some platforms, HPET is not wired to trigger IRQ 2.
This would make HPET non-functional if the legacy
interrupt routing bit is set in the global config
register. This adds a DTS flag so the driver won't
set the bit to enable legacy interrupt.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Fix the interrupt setting in the fvp_baser_aemv8r dts:
- The correct interrupt number is 5, not 0.
- The interrupt priority and type are swapped.
This patch also enables interrupt driven mode for this platform as this
is the ideal setting for a Fast Models based platform.
Issue-ID: SCM-4037
Signed-off-by: Filipe Rinaldi <filipe.rinaldi@arm.com>
Change-Id: Ic4815f5afe4c9df9d8fe373d47d2773d64087c96
dts/bindings/timer/riscv,machine-timer must have compatible name
riscv,machine-timer. nuclei,machine-timer is wrong, correct it.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This PR adds the different handling of temperature sensor for the
STM32L5 soc. In this soc, there are some calibration settings which
need to be applied for temperature conversion.
Signed-off-by: Wouter Cappelle <wouter.cappelle@crodeon.com>
The dts binding general rules document states that the property
description should explain why the default value was selected
(e.g. "default is the value at power-on").
See comment in #41143
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Add fragment:
io-channel-cells:
- input
to binding of the "ite,it8xxx2-adc" and "zephyr,adc-emul" compatible.
It is necessary to use io-channels property.
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Certain stm32 soc's have a single shared irq for all adc channels
on those soc's only a single channel is supported.
Added a Kconfig that enables a shared irq for stm32f2x, stm32f4x,
stm32f7x soc's. The shared IRQ uses a flag to limit the number of
interrupts defined to only 1. A shared irq handler is added which
determines which ADC instance the interrupt is for, it then calls
into the existing interrupt.
Signed-off-by: Marius Scholtz <mariuss@ricelectronics.com>
The default I2C channel 3 is used by alternate function of GPIO H1/H2
Krabby uses GPIO F2/F3 as I2C channel 3, so we need to add the
compatibility of the GPIO F2/F3.
TEST=test on it8xxx2_evb:
zmake configure -b zephyr/projects/it8xxx2_evb/
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
An additional devicetree poperty `single-wire` is added
to uart and usart bindings of stm32. The driver checks this value
during initialization and enables the single wire mode when set.
Signed-off-by: Jonathan Hahn <Jonathan.Hahn@t-online.de>
The leon3 SoCs were missing definitions of the CPU node. This node is
now required for PM, so that power states can be defined.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Better setting a default value there so DT_PROP() will return something
relevant whether the property is set or not.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add timer and pwm nodes. The structure follows a similar approach to the
one used by STM32. Timer nodes store all timer information (e.g.
pre-scaler), whereas the pwm nodes are children of the timer node
indicating a specialization of the multiple timer functionalities.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
