'reg' attribute removed from overall stm32l1 dts,
so eeprom size has to be specified for each SoC
in stm32l1x series.
Adds remaining stm32l1x SoCs that didn't have eeprom size specified yet.
Eeprom size added in stm32l151Xb-a & stm32l151X8-a dtsi files,
(based on device overview in datasheet DocID024330 Rev 5).
Eeprom size added in stm32l151Xb dtsi file (based on
device overview in datasheet DocID17659 Rev 12).
Signed-off-by: Noelle Clement <noelleclement@hotmail.com>
In npcx7 series, the Timer and Watchdog module (TWD) generates the
clocks and interrupts used for timing periodic functions in the system.
It also provides watchdog reset signal generation in response to a
failure detection.
The CL also includes:
— Add npcx watchdog device tree declarations.
— Zephyr watchdog api implementation.
— Add Watchdog definitions for npcx7 series in
tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c for
supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This commit is about the it8xxx2 i2c master driver which
includes six SMBus channels. The enhanced channel i2c3,
i2c4, i2c5 are controller which are designed to support
the I2C protocol.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
In order to ease reuse on other series, set DMA as optional
and use IT if no DMA channel is specified in the qspi node.
Tested on disco_l475_iot1
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add device tree description for qspi node on STM32L4 and
signals on whole family.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Setting clock-frequency as required (the driver does not build without
it) and dropping definitions that are already specified in
i2c-controller.yaml.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Replace few instances of space before colon in the binding files, not
functional, just for coherency.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
STM32L152xC SoC differs from other L1 SoCs in RAM (32KiB) and
flash (256KiB) size, EEPROM size (8Kib) and amount of interrupts
(57, see STM32Cube). Devicetree and Kconfig support.
Signed-off-by: Noelle Clement <noelleclement@hotmail.com>
after 7c699348a8
Convert drivers to new DT device macros
now the device name is aligned with label so we need
align them to default config
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
This patch adds IRQ priority support for SiFive PLIC by device-tree.
Some IRQ sources of plic use Kconfig to set priority of their IRQ.
- AON: no driver
- I2C, SPI, PWM: not use IRQ
- GPIO, UART: default 1
So this patch specifies IRQ priority 1 for all sources.
Currently these drivers (gpio and uart) do not support that they get
and use IRQ priority from device-tree. We need more patches.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
The npcx7m6fb dts defines i2c controller and ports, where the controller
is a property in the port node definition and the device nodes should be
defined as subnodes of the port.
This changes the binding definitions to reflect that, defining the port
as an i2c-controller so that in can inherit sub-nodes for i2c devices,
and the controller as a generic node.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
jedec,jesd216.yaml has properties for any memory device that conforms
to the JESD216 specification. This file at a minimum should be
included in the binding for any driver that interacts with such a
device.
jedec,spi-nor-common.yaml extends jedec,jesd216 with additional
parameters useful for memory devices that are not available from
standard JESD216 parameter tables. This file may be included instead
of jedec,jesd216.yaml if a driver is able to support additional
functionality related to the extended description.
jedec,spi-nor.yaml remains the binding for the Zephyr SPI_NOR driver
alone.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Add binding for the Nordic ECB (AES electronic codebook mode
encryption) peripheral and corresponding devicetree nodes for
nRF SoCs that feature this peripheral.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Since MDK was updated and now it contains the definition of QDEC
peripheral for nRF52805, the DT node representing this peripheral
can be processed normally.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
"st,mem2mem" property is supposed to be limited to dma-v1.
Remove its use in dma-v2 components.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2 versions of DMA hardware blocks could be found across stm32 series.
In order to simplify the handling of matching Kconfig symbols,
make this visible in dts files by creating "st,stm32-dma-v1" and
"st,stm32-dma-v2" and set them accordingly in dtsi files.
Duplicate and update related bindings to reflect that new state.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Tigerlake H has less RAM and fewer cores. Both should be
supported, selectable at the board level. For now use the H
configuration as more readily available for testing.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The STM32F105xx is effectively an STM32F107xx without Ethernet. As such,
it's possible to include the STM32F105's device tree from STM32F107, and
add in any additional nodes (currently just DMA2, though according to
the datasheet, this may be supported by the STM32F105xx and other parts
too).
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Create a common binding file that will be included by all bindings
handled by iis2dlpc driver. For now this includes optional drdy-gpios
property and it is shared by the i2c and spi version of the driver.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The interrupt numbers for two socs for the gpio peripheral was wrong.
This commits corrects this issue for the relevant socs.
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
The watchdog and rng nodes were a sub-node of the gpio node.
This commits corrects this issue for the relevant socs.
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
Adds support for ADC on G0 series.
Simple implementation: sequencer not fully configurable,
and only one common sampling time.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
There are some drivers in the tree that support devices on multiple
different buses, although so far this has not been represented in
device tree using the bus concept. In order to convert these drivers &
bindings to refer to a formal bus in device tree we need to be able to
match bindings which lack an explicit "on-bus: ..." value against any
parent bus. This will also be needed for any external bindings, since
those would not be aware of on-bus (as it's a Zephyhr-specific
extension).
The two drivers I'm particularly targeting is the ns16550 UART driver
(drivers/serial/uart_ns16550.c) and the DW I2C driver
(drivers/i2c/i2c_dw.c). They both support devices with a fixed MMIO
address as well as devices connected and discovered over PCIe. The
only issue is that instead of encoding the bus information the proper
DT way these bindings use a special "pcie" property in the DT node
entries to indicate whether the node is on the PCIe bus or not.
Being able to convert the above two drivers to use the DT bus concept
allow the removal of "hacks" like this:
if DT_INST_PROP(0, pcie) || \
DT_INST_PROP(1, pcie) || \
DT_INST_PROP(2, pcie) || \
DT_INST_PROP(3, pcie)
to the more intuitive:
if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
This also has the benefit that the driver doesn't need to make any
arbitrary assumptions of how many matching devices there may be but
works for any number of matches. This is already a problem now since
e.g. the ns16550 driver assumes a maximum of 4 nodes, whereas
dts/x86/elkhart_lake.dtsi defines up to 9 different ns16550 nodes.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
This patch adds the driver for Omnivision OV7725
Color CMOS VGA Sensor.
The driver currently provides a simple capture
function, the output format only provides
RGB565,640x480.
Signed-off-by: Frank Li <lgl88911@163.com>
This patch enables the rtc clock on the stm32g4 soc
from STMicroelectronics.
Even if the set by default (reset value of theRCC_APB1ENR)
the bit is marked as 1.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Instead of hard-coded values for interrupt priorities in DT nodes, use
a macro that additionally can be overridden at the board or application
level. This allows, for instance, changing the interrupt priorities for
all but one peripheral without using a lengthy overlay file.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
