Commit graph

8801 commits

Author SHA1 Message Date
Erwan Gouriou
d55905b2f7 drivers/disk: sdmmc: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
956afc3a08 drivers/dac: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
65d222b0ab drivers/fdcan: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
337c9b96e9 drivers/can: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
93956b2073 drivers/adc: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Gerard Marull-Paretas
21a271962c drivers: serial: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-26 11:36:42 +01:00
Krzysztof Chruscinski
9886bdc0c8 drivers: pwm: pwm_nrf5_sw: Use runtime resources allocation
Use nrfx_gpiote and nrfx_ppi allocators to allocate channels
at runtime instead of fixed, device-tree based allocation which
is harder to maintain.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2021-11-26 09:31:54 +01:00
Neil Armstrong
3f68124c56 bindings: pcie: add pci-host-ecam-generic bindings
Add bindings for a generic PCIe Controller in ECAM mode.

ECAM stands for PCI Express Enhanced Configuration Access Mechanism
where the PCIe config space is flat memory-mapped.

An optional msi-parent phandle is added to link to an optional
MSI/MSI-X Interrupt Message Translation HW component.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-11-25 18:37:15 +01:00
Neil Armstrong
e636f149aa dts: arm64: qemu-virt: switch to 64bit addressing in DT
The qemu arm64 virt machine PCIe controller config space needs a
64bit adressing, so switch the entire qemu-virt-a53 and
qemu_cortex_a53 board dts to address-cells & size-cells to 2
to accommodate for 64bit addresses.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-11-25 18:37:15 +01:00
Sam Hurst
ffce28ad6f dts: arm: stm32u5: Add UCPD1
This commit adds UCPD1 dts bindings for stm32u5xx

Signed-off-by: Sam Hurst <sbh1187@gmail.com>
2021-11-24 14:21:04 -05:00
Sam Hurst
d26979b11a dts: arm: stm32l5: Add UCPD1
This commit adds UCPD1 dts bindings for stm32l5xx

Signed-off-by: Sam Hurst <sbh1187@gmail.com>
2021-11-24 14:21:04 -05:00
Sam Hurst
0d3caff318 dts: arm: stm32g4: Add UCPD1
This commit adds UCPD1 dts bindings
for stm32g4xx

Signed-off-by: Sam Hurst <sbh1187@gmail.com>
2021-11-24 14:21:04 -05:00
Sam Hurst
72c4a89570 dts: arm: stm32g0: Add UCPD1 and UCPD2
This commit adds UCPD1 and UCPD2 dts bindings
for stm32g071, stm32g081, stm32g0b1, and stm32g0c1.

Signed-off-by: Sam Hurst <sbh1187@gmail.com>
2021-11-24 14:21:04 -05:00
Sam Hurst
cc1cedb82e dts: bindings: Add yaml file for STM32 TCPC support to DT
Add yaml files to DT for initial support of STM32 TypeC
Port Controller (TCPC)

Signed-off-by: Sam Hurst <sbh1187@gmail.com>
2021-11-24 14:21:04 -05:00
Johann Fischer
503b7e6f9f dts: same70: default USB HS controller to high-speed
USB HS controller is high-speed capable, default it to high-speed.

Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
2021-11-24 12:28:02 +01:00
HaiLong Yang
5e035b0f4e drivers: serial: gd32 usart add interrupt support
Add interrupt support for gd32 usart driver.

Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
2021-11-23 13:25:43 -05:00
Andy Ross
cb73032a32 soc/intel_adsp: Unify/dtsify L2 local memory control block
These registers were hardwired in the platform layer.  Move to
devicetree, via a struct interface that looks like the pre-existing
shim layer.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
ef372d055d soc/intel_adsp: Unify host window register interface
These registers are identical on all platforms, the only difference
being that cAVS 1.5 places them at a different address.

Create a devicetree node to track the register block, and replace the
platform header code with a global API defined once (it works like the
pre-existing shim struct).

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
ed9434c812 soc: intel_adsp: Clean up shim driver
Each platform was defining its own shim.h header, with slightly
variant field definitions, for a register block that is almost
completely compatible between versions.  This is made worse by the
fact that these represent an API imported fairly early from SOF, the
upstream version of which has since diverged.

Move the existing shim struct into a header ("cavs-shim.h") of its
own, remove a bunch of unused symbols, fill in definitions for some
registers that were left out, correct naming to match the hardware
docs in a few places, make sure all hardware dependencies are source
from devicetree only, and modify existing usage to use the new API
exclusively.

Interestingly this leaves the older shim.h header in place, as it
turns out to contain definitions for a bunch of things that were never
part of the shim register block.  Those will be unified in separate
patches.

Finally: note that the existing IPM_CAVS_IDC driver (soon to be
removed from all the intel_adsp soc's) is still using the old API, so
redeclare the minimal subset that it needs for the benefit of the
platforms in transition.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
ab1baca03f drivers/ipm: Remove intel_adsp_mailbox driver
This is dead code.  It's based on the cAVS "IPC" mechanism to allow
communication to and from the host CPU.  But there is no test rig in
the Zephyr tree for the protocol defined.  And in fact the only
Zephyr-based user of the IPC mechanism (Sound Open Firmware) has its
own IPC driver and speaks its own protocol with the host kernel.  That
driver needs to migrate into Zephyr soon and this legacy bit is just
confusing.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Guillaume Lager
4c986a266f drivers: sensor: tmp112: Add default device initialization
This allow to have a smaller driver footprint when a single
configuration is required.

Signed-off-by: Guillaume Lager <g.lager@innoseis.com>
2021-11-23 13:12:39 +01:00
Carlo Caione
983d4606ff ipc_service: Add new RPMsg with static VRINGs backend
Introduce a new RPMsg with static VRINGs backend. This new backend makes
easy to generate and use IPC instances backed by OpenAMP using the DT.

Each instance is defined in the DT as (for example):

  ipc: ipc {
          compatible = "zephyr,ipc-openamp-static-vrings";
          shm = <&sram_ipc0>;
          mboxes = <&mbox 0>, <&mbox 1>;
          mbox-names = "tx", "rx";
          role = "primary";
          status = "okay";
  };

It is then possible to register an send data through endpoints using the
IPC service APIs.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-11-22 23:03:23 -05:00
Peter Johanson
d99de305ce dts: bindings: Add generic Xiao interconnect
* With existence of Adafruit Qt Py boards, and upcoming wireless
  Xiao from Seeeduino, define nexus node and peripheral node
  labels for use with shields that accept any Xiao format board.
* Adds `&xiao_d`, `&xiao_spi`, `&xiao_i2c` and `&xiao_serial` generic
  node labels.
* Add new 'seeed-xioa-header.yaml` to document new nexus node.

Signed-off-by: Peter Johanson <peter@peterjohanson.com>
2021-11-22 22:25:20 -05:00
Gerard Marull-Paretas
285f55899b drivers: serial: gd32: use pinctrl
Use the pinctrl API to configure peripheral pins.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Gerard Marull-Paretas
1f74c01daa dts: arm: gigadevice: gd32f403: add afio and pinctrl
Add afio, pinctrl and gpioa...g entries for the GD32F403 series.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Gerard Marull-Paretas
f8017dc5ad drivers: pinctrl: gd32: initial support for AFIO based SoCs
Add a pin control driver for GD32 SoCs using the AFIO model.

Thanks to Gerson Fernando Budke for testing and implementation
suggestions.

Co-authored-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Gerard Marull-Paretas
63321e7f73 dts: arm: gd32f4xx: add pinctrl and gpio nodes
Add definitions for the pinctrl and gpio nodes.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Gerard Marull-Paretas
543a3843ff drivers: pinctrl: gd32: initial support for AF based SoCs
Add a pin control driver for GD32 SoCs using the AF model.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Wealian Liao
5a9bc389f0 driver: gpio: nct38xx: Add NCT38XX gpio driver support
NCT38XX series, which are i2c-based chips, support a different number
of GPIO functionality. For NCT3807, it has 2 GPIO ports on the same i2c
device address. For NCT3808, it has 2 GPIO ports on different i2c
device addresses. This commit adds NCT38XX GPIO driver support &
provides the interrupt handler for the share alert pin.

The following is NCT3807 devicetree node example:
```
&i2c0_0 {
	nct3807_0: nct3807@70 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nuvoton,nct38xx-gpio";
		reg = <0x70>;
		label = "NCT3807_0";

		gpio@0 {
			compatible = "nuvoton,nct38xx-gpio-port";
			reg = <0x0>;
			label = "NCT3807_0_GPIO0";
			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <8>;
			pin_mask = <0xff>;
			pinmux_mask = <0xf7>;
		};

		gpio@1 {
			compatible = "nuvoton,nct38xx-gpio-port";
			reg = <0x1>;
			label = "NCT3807_0_GPIO1";
			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <8>;
			pin_mask = <0xff>;
		};
	};
};
```

Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
2021-11-20 08:00:38 -05:00
Ruibin Chang
3ab081efe9 ITE drivers/pwm: cleanup it8xxx2 pwm driver
1.Putting the PWM_CHANNEL_X, PWM_PRESCALER_CX information
  in the description.
2.Use the common definition EC_FREQ.
3.Use the common macro IT8XXX2_DT_ALT_ITEMS_LIST.
4.Stop using DRV_CONFIG, DRV_REG macro.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2021-11-19 10:24:11 -06:00
Tomasz Bursztyka
4bd5935302 dts/bindings: Add a dedicated property for duplex mode on SPI device
Users will have to include dt-bindings/spi/spi.h in order to use the
relevant flags fol this property. For instance:

    ...
    duplex = <SPI_HALF_DUPLEX>;
    ....

By default all SPI device are configured to be full duplex so the
property is optional. This property makes sense only for devices that
can be configured on either modes. Which, in such case, it will need to
use DT_INST_PROP(<instance number>, duplex) macro call to retrieve the
property value. Others can fully ignore it.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2021-11-19 11:50:38 +01:00
Tomasz Bursztyka
20b8d74d42 dts/bindings: Update HTS221 bindings to enable both i2c and SPI bus
HTS221 is now supported on both buses so let's make DTS aware of it.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2021-11-19 11:50:38 +01:00
Gerard Marull-Paretas
1832d68e01 tests: lib: devicetree: add tests for DT_INST_ENUM_IDX(_OR)
Add tests for the instance based enum macros DT_INST_ENUM_IDX and
DT_INST_ENUM_IDX_OR.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-18 19:12:07 -05:00
Gerard Marull-Paretas
13b011afb9 dts: arm: gigadevice: add support for gd32f450ik
Add support for the IK variant (256K SRAM, 3072K ROM).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-18 17:42:57 +01:00
Gerard Marull-Paretas
c34f41b22d dts: arm: gigadevice: add initial support for gd32f4xx
Add initial support for GD32F4XX (405, 407 and 450).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-18 17:42:57 +01:00
Gerard Marull-Paretas
809c35d430 dts: arm: gigadevice: organize dts files in folders
Create a folder for each of the series.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-18 17:42:57 +01:00
David Leach
a09ba37334 MXRT600: Fix secure/non-secure definition for FLEXSPI
The Flexspi memory address defines the location of the externally
attached flash to the MXRT600 based board. The flexspi has two
different memory spaces for secure and non-secure access that are
not aligned for the Flexspi register space and the memory map
address space. The normal method of handling this via the two
different dts files for secure/non-secure is not able to handle
this because a base address is applied uniformly across multiple
reg items.

Changes include:

- pull flexspi out of peripherals block to allow it to be explicitly
expressed in the respective secure/non-secure SOC DTS files.
- move the flash size definition to the board level definition and
use the size of the actual flash device found on the board.
:
Signed-off-by: David Leach <david.leach@nxp.com>
2021-11-18 14:29:53 +01:00
Tim Lin
e29a15c0e3 ITE: drivers/serial: add the UART driver for the PM callback function
IT8XXX2 uses shared ns16550.c driver which does not provide a power
management callback(pm_action_cb), so create driver to handle
IT8XXX2 specific UART features.

note: pm_action_cb(old name: pm_control_fn)

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-11-16 21:23:42 -05:00
Alexandre Bourdiol
37ffd01f8c dts: arm: stm32: TIM6 and TIM7 doesn't support PWM capability
TIM6 and TIM7 doesn't have comparator, nor pin output.
Thus they can't support PWM.

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2021-11-16 09:55:30 -06:00
Alexandre Bourdiol
7f3423ae48 dts: arm: st: stm32: move "st,prescaler" to timers instead of pwm
Prescaler was misplaced in pwm binding, instead of timers binding.
For example, TIM6/TIM7 doesn't have PWM capability,
but have a prescaler.
This change also prepares the introduction of timer based counter
(which requires prescaler at timer level)

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2021-11-16 09:55:30 -06:00
Alexandre Bourdiol
37175e8643 dts: bindings: stm32: move "st,prescaler" to timers instead of pwm
Prescaler was misplaced in pwm binding, instead of timers binding.
For example, TIM6/TIM7 doesn't have PWM capability,
but have a prescaler.
Also prescaler is common to all PWM channels of the same timer.
This change also prepares the introduction of timer based counter
(which requires prescaler at timer level)
For compatibility reason temporarily keep pwm binding to avoid
breaking boards out of tree.
Block st,prescaler property in lptim binding
as lptim doesn't use this property for now.

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2021-11-16 09:55:30 -06:00
Lukas Gehreke
0544f5dbc3 drivers: gpio: Added mcp230xx GPIO driver.
Added driver for the mcp230xx series I2C-based GPIO chips.

Signed-off-by: Lukas Gehreke <lk.gehreke@gmail.com>
2021-11-16 10:13:14 -05:00
Dino Li
6d8f1bf6d9 soc: it8xxx2: add support for eSPI driver
This supports eSPI slave, virtual wire, and peripheral functions.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-11-12 14:51:10 +01:00
Felipe Neves
b50cb2a537 drivers: counter: esp32: add support for esp32c3
to the unified esp32 counter driver.

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-11-11 19:14:15 -05:00
Martí Bolívar
d2ba94bbea dts: nordic,nrf-radio: add fem property
This will be used to take a phandle to a FEM device, either a generic
two pin device or an nRF21540. Keep the nRF21540 binding example up to
date.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2021-11-11 21:52:24 +01:00
Martí Bolívar
a930bebb42 dts: bindings: improve nordic,nrf21540-fem docs
The way the nRF21540 device is configured makes sense once you
understand it, but it's quite unusual: a single peripheral is
configured with two separate devicetree nodes linked by a phandle.

Since this risks entering "exploding head" territory for beginners, it
deserves a thorough example. Add one to the binding's description.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2021-11-11 21:52:24 +01:00
Martí Bolívar
9bbaccc8ed dts: bindings: add generic-fem-two-ctrl-pins
This is a helper binding for radio front-end modules that have a
two-pin control interface, where one pin is used to turn on an power
amplifier (PA) for TX, and another is used to turn on a low-noise
amplifier (LNA) for RX.

Such hardware is already supported by the Bluetooth subsystem, but via
PA/LNA Kconfig settings. Since this is hardware configuration, it is
better to move this to devicetree instead.

Add a binding that makes it possible to define nodes which contain the
same information, along with a bit of extra information related to the
gain in dB of each amplifier not currently available from Kconfig.
This is similar to the existing binding for the nordic,nrf21540-fem
compatible.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Signed-off-by: Andrzej Kuros <andrzej.kuros@nordicsemi.no>
2021-11-11 21:52:24 +01:00
Martí Bolívar
3eb2377c58 dts: sitronix,st7789v: fix binding whitespace
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2021-11-10 17:28:17 -05:00
Carlo Caione
74b701065d bindings: nrf-ipc: Enable DT helpers
Make the MBOX NRF IPC instances referenceable using the MBOX DT helpers.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-11-10 10:28:14 -06:00
Jonathan Rico
4f2762d7da dts: Add external coexistence pointer to nrf-radio
This is to support upcoming external radio coexistence implementations,
see binding documentation for more info.

Signed-off-by: Jonathan Rico <jonathan.rico@nordicsemi.no>
2021-11-10 16:11:41 +01:00