Create a common properties file that will be included by all DT
bindings (as i2c and spi) handled by lis2ds12 driver.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Add a dedicated compatible for STM32MP1 clock control node.
Since, on such platform, clock configuration is done on A9
side, only the clock-frequency property is available.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add dtsi file for i.MX8MP board.
This has one HiFi4 core, from Cadence, lx6 compatible
and 2 System RAM.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Add a DTS description of timer5 to: STM32G474, STM32G484, STM32G473,
STM32G483, and STM32G471
Add a DTS description of timer5 to: STM32G474, STM32G484, STM32G473,
STM32G483, STM32G491, and STM32G4A1
Signed-off-by: Pete Dietl <petedietl@gmail.com>
Add general mboxes, mbox-names to base.yaml to be utilized by any
clients that use mailboxes.
Additionally add mailbox-controller.yaml for common properties shared
by all mailbox controller devices.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add devicetree nodes for the NEORV32 GPIO device.
The GPIO port is 64 bits wide, but Zephyr only supports up to 32 bit
wide GPIO ports. The GPIO device is therefore handled as two Zephyr GPIO
devices with a nexus devicetree node mapping pins 0 to 31 to the device
handling the lower half, and pins 32 to 63 to the device handling the
upper half.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Currently all the *-names and *-cells properties are derived from the
name of the base <name>s property. This is a limitation because:
- It forces the base property name to be plural ending in -s
- It doesn't allow the english exception of plural words ending in -es
With this patch we add one additional property 'specifier-space' that
can be used to explicitly specify the base property name.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Suggested-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
1) Allow use of interrup driven instance.
ROM implementation could be selected via dts compatiable.
2) Use UART rx fifo and timeout interrupt for end of message detection.
Added to decrease interrupts count on data reception
3) Use ESP_LL api.
Signed-off-by: Pavlo Hamov <p.hamov@venstar.com>
Adds SPI support on LPSPI1 to the RT1010. LPSPI1 is available on pins
6, 8, 10, and 12 of J57 on the evaluation board
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit enables the LPSPI1 peripheral on the RT1015 EVK. LPSPI pins
are not populated by default, but headers can be added to J19 on the EVK
to access these signals
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add device tree for Intel SoC FPGA Agilex initial bring up. This is the
first version of device tree which enable single CPU core and basic
drivers that needed by hello_world example.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
The shared multi-heap memory pool manager uses the multi-heap allocator
to manage a set of reserved memory regions with different capabilities /
attributes (cacheable, non-cacheable, etc...) defined in the DT.
The user can request allocation from the shared pool specifying the
capability / attribute of interest for the memory (cacheable /
non-cacheable memory, etc...)
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add specific properties to enable remap for PA11/PA12, which is a
possibility on STM32G0/F0 SoCs.
These properties only have effect when defined.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This name should be the same as cpus node in dtsi. After the power
policy is added, the cpu-power-states in the CPU properties can
be used.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
AHB prescaler is a value which divides the SYSCLOCK
to provide the HCLK. The HCLK supplies the core, AHB bus, memory.
On the stm32wb and stm32wl, the HCLK for CPU1 is HCLK1
with cpu1-prescaler.
By default the value is 1, else the HCLK must be correctly set.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
interrupt controller, also places its relevant
peripheral sources allowing drivers to use the
DT macros instead of espressif headers.
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
This reverts commit d3a558591f.
We shouldn't be adding vendor prefixes for things we don't have
upstream bindings for unless we've inherited them from Linux.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
If supported by the SPI instance and soc, this property will
configure the frame-format to be compliant with the TI mode.
By default, if supported, the frame-format is Motorola mode.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The maximum supported speed according to the SX126x datasheet (I have
not found that information in the STM32WL datasheet or reference
manual). Increase the Sub-GHz SPI frequency from 1 Mhz to to 12 MHz,
which corresponds to a baud rate prescaler of 4 with a 48 MHz clock. It
also matches what is done the the STM32CubeWL package.
This reduces the time the MCU is kept running, thus reducing the global
power consumption.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This adds the uart4 device to the stm32f3_disco board
based on the stm32f303 device from STMicroelectronics
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit adds stm32f103xd series dts file that was missing.
Also, changed stm32f103xe.dts for highlighting the differences between
f103xd and f103xe series.
Signed-off-by: Deimantas Aukštkalnis <deimantas.aukstkalnis@teltonika.lt>
Add DT bindings for the optional Interrupt Translation Service module
of the ARM GICv3 Interrupt Controller.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Implements a shim layer driver using st hal for
I3G4250D gyro, mounted for example on stm32f3_disco_E.
No support for triggers included yet.
Signed-off-by: Jonathan Hahn <Jonathan.Hahn@t-online.de>
