This file defines some of the most important properties in the
devicetree, including core concepts like 'compatible', 'reg', and
'interrupts'. For some reason, we've never prioritized writing up
proper descriptions that indicate their importance or show where the
user can get more information about them in the specs or elsewhere.
Give this file a once-over to improve the situation.
Signed-off-by: Martí Bolívar <mbolivar@amperecomputing.com>
Signed-off-by: Martí Bolívar <marti.bolivar@oss.qualcomm.com>
Add properties for describing RX and TX fifo sizes.
Also reformat some descriptions and fix the description of the
transfer-delay property which was incorrect. Since zephyr spi bufs are
not continuous, every possible Zephyr LPSPI driver must use
continuous transfer mode, for which the meaning of this delay has
nothing to do with the chip select.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
There is no such thing as associating a compatible to a child binding
so remove this from the nxp,dmic binding definition and devicetree files
that incorrectly set one.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The GPIO peripheral on Silabs Series 2 devices is responsible for
allocating analog buses to analog peripherals. Enable support for
this in the pinctrl driver. Since these bus allocations are not
digital pins, introduce a new property silabs,analog-bus for this
purpose.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
- Update the overlapping irq number between port_irq4 and spi1
- Remove irq number for sci9 as it exceeds the limit (32 irq numbers)
Now users will define the irq numbers themselves
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
There is a HW bug in nPM1300 LDO which causes the LDO output voltage to
reach its target very slowly in specific cases. This is worked around by
performing an additional i2c read shortly after an LDO is enabled.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
This PR adds support for BQ32002 RTC chip.
Supported functionalities:
* Time setting/reading
* Alarm setting/reading
* Calibration setting/reading
* IRQ frequency configuration
Tested on nRF52833-DK board.
Signed-off-by: Marcin Lyda <elektromarcin@gmail.com>
After a recent change for the imx gpr binding, the i2s driver was
changed to reflect the new names of the cells, but apparently also the
sai node can refer to itself with a phandle and need cells names to
match also.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Commit 57723cf405 ("dts: arm: st: Refactor DTSI files to use macro"),
which replaced raw hex codes by using STM32_CLOCK macro, causes
regression in the case of the CAN device where the previous raw value
contained more than one bit set to 1. The macro is in fact correct only
for values with a single bit set. In all other cases, raw values must
continue to be used.
Tested on STM32F429I-DISC1 board
Fixes: 57723cf405
Co-authored-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
The current nxp_mcxc141.dtsi sets the SRAMs base address
to 0x1FFF_F000. This leads to the mcxc141 faulting during
initialization when the first write to SRAM occurs:
z_prep_c -> z_bss_zero -> z_early_memset -> memset
The correct base address is 0x1FFF_F800. This information
is not obvious in the "MCX C24X Sub-Family Reference Manual,
Rev. 1, 07/2024". The address was taken from an MCUXpresso
IDE sample project.
Link: https://www.nxp.com/webapp/Download?colCode=MCXC24XP64M48RM
Signed-off-by: Maximilian Werner <maximilian.werner96@gmail.com>
ADC2 is no longer supported on ESP32C3 due to HW limitations.
Check silicon errata on Espressif website for more details.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Add clocks property to CPUs. nRF54Lx series is using hfpll as clock
source for CPU (and fast peripherals). CPU clock frequency can be
derived from frequency of the source clock so clock-frequency property
is removed from cpu as it is redundant.
nrfx/MDK expects that NRF_CONFIG_CPU_FREQ_MHZ define is set to correct
CPU frequency. Modified nrfx CMakeLists.txt to use clock frequency of
hfpll instead of CPU clock-frequency property.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add DT property to configure the LPSPI instance to use tristated output
instead of retained output when PCS is negated.
Turn on the config on a couple boards for test coverage.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Example for creating ICM42688 dt node uses old dt option names.
Fix by changing to newest dt option names.
Signed-off-by: Nikola Petrovic <nikolaptr6@gmail.com>
Improve the documentation of the IOMUXC GPR binding so that it is
clear what the cells in the specifier space of "pinmux" space mean. And
change the names of the cells to be more appropriate. "offset" instead
of "pin" and "mask" instead of "function" describes more precisely what
the cells in the specifier mean.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
- remove calculation of pinmux value for stm32 in device tree binding
documentation.
- stm32-pinctrl.yaml contains wrong calculation as can be compared to
#define STM32_PINMUX in stm32-pinctrl.h.
- stm32f1-pinctrl.yaml also contains different wrong calculation
compared to #define STM32F1_PINMUX in stm32f1-pinctrl.h.
Signed-off-by: Andreas Klinger <ak@it-klinger.de>
Add wsen_tids_2521020222501 driver with
the corrected name and compatibility with
the hal update as well as added new features.
Signed-off-by: Wajdi ELMuhtadi <wajdi.elmuhtadi@we-online.com>
Initial commit for a STM32L152 based GPIO expansion chip.
The mfxstm32l152 driver offers GPIO controller fonctions.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
