To support both 8-bit and 32-bit Control/Status register variants, register
offsets need to be calculated from device tree.
Updated register data in device tree to the 32-bit CSR variant.
Renamed defines to be similar to other LiteX drivers.
Changed frequencies in clock-outputs nodes, so i2s/litex sample works.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Correct width when accessing LITEETH_RX_LENGTH register.
Also update register data in device tree to the 32-bit CSR variant.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Make driver take register info from device tree so it can work with both
8-bit and 32-bit CSRs.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Adds few missing zephyr/ prefixes to leftover #include statements that
either got added recently or were using double quote format.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This sensor is virtually identical to the lsm6dso. The only difference
is the accelerometer ranges are double those of the lsm6dso.
Use the same driver. The difference is detected by using "st,lsm6dso32"
as the first compatible entry, followed by "st,lsm6dso".
An bit flag in the existing accel_range config field is used to check if
the chip is the doubled range or not.
Signed-off-by: Trent Piepho <trent.piepho@igorinstitute.com>
Fix various board fixed-partition definitions where the devicetree cell
has been defined oddly, such as 9 nibbles (which makes no sense since
the cells are 32 bit) or 7 nibbles where all the others are 8.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix PM minimum residency time and exit latency for rt11xx to reflect
actual delays when entering and exiting low power modes.
Fixes#45750
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Set the priority of the wwdg instance to 6
else a build error happens :
static assertion failed: "Invalid interrupt priority.
Values must not exceed IRQ_PRIO_LOWEST"
Signed-off-by: Francois Ramu <francois.ramu@st.com>
LPC55sx6 SOC has NXP Manufacturing Programmed Area(NMPA) stored at
offsets 0x3EC00-0x3FDFF. Correct uuid offset to be within this region.
Fixes#43870
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
All the SPI1,2,3 clock of the stm32h7x mcus
are sourced by the PLL1_Q by default. This must be set
in the DTS to have a valid clock rate calculation.
The pll1_q is divided by the <div-q> property of the pll node.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Config pwm open-drain mode without enabling STORE_REG. This CL
collects all active PWM's base address and related index in an
array. Then, pinctrl driver configs its open-drain mode by
finding the corresponding 'channel' index.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This PR Fixes the Audio PLL Rate Calculation (there was an additional
divide / 8 which is not necessary and does not appear in similar
calculations in example code from the SDK).
Additionally, it adjusts the SAI .dtsi to more correctly configure the
mclk rate, and adds comments specifying what the regististers mean.
Signed-off-by: Nickolas Lapp <nickolaslapp@gmail.com>
Pinmux is depricated (see #39740) and shouldn't be used anymore
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Pinmux is deprecated (see #39740) so let's get rid of
it's usage for HSDK board.
As we call pinmux only once at init phase we simply do
register setup in platform code instead of pinmux.
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
The binding was erroneously changed in commit 988fe8d, which led to
build failures. This commit reverts the change.
Signed-off-by: Martin Jäger <martin@libre.solar>
Add inclusions of header files with devicetree related ADC definitions
to the nRF SoC dtsi files so that those definitions can be used also
for nRF SoC based boards.
Provide definitions of nRF ADC and SAADC analog inputs suitable
for use in devicetree.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Extend the common ADC controller binding with a child binding that
allows specifying configuration of ADC channels.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
On Espressif SoCs, the pin controller is a virtual device.
Pin settings are actually controlled in a distributed way.
Therefore, that node does not belong to the SoC bus.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Add 'inversion-on' property to st7735r.
Issue INVON(21h) command on initializing if inversion-on was enabled.
As a result of this command, the display color is inverted.
Otherwise, INVOFF(20h) will be issued.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add partial pin control support for the imx8mp. Since the UART driver is
not currently enabled, pin control cannot be tested on this platform.
Therefore, only the DTS definitions required to set the pinmux options
are present for this platform, and are not being applied (since
CONFIG_PINCTRL=n).
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add initial pin control support for the A53 core of the imx8mm. Since
the UART console driver is not currently enabled for this platform,
there is no way to test the full pin control enablement. Therefore,
CONFIG_PINCTRL is still not selected for this platform, although the
required DTS definitions and pin control headers are present.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for IOMUXC peripheral present
on mimx8ml8_m7 soc. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a
new header and compatible binding to handle the
different register layout on this SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for IOMUXC peripheral present
on mimx8mq6_m4 soc. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a
new header and compatible binding to handle the
different register layout on this SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for mcimx7_m4 SOC. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a new header and
compatible binding to handle the different register layout on this SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for mcimx6x. The IOMUXC peripheral present on
this SOC is identical to the one used on the iMX RT10xx series, so the
dts bindings are reused.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add the DTS binding for OCTOSPI interface for the stm32 devices
from STMicroelectronics.
This corresponds to a NOR octo SPI flash.
In this config, there is only on NOR-flash device.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in npcx eSPI and host_subs driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in npcx adc driver. Please notice users need to
configure the corresponding pinctrl nodes in 'pinctrl-0' property in the
adc0 DT node. For example, if ADC0 and ADC2 channels are selected for
the application, please add the follwoings in your board DT layout file.
&adc0 {
status = "okay";
/* Use adc0 channel 0 and 2 for 'adc_api' driver tests */
pinctrl-0 = <&adc0_chan0_gp45
&adc0_chan2_gp43>;
pinctrl-names = "default";
};
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in npcx tachometer driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in ps2 driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in pwm driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
